CN117674830A - Voltage signal conversion module and phase-locked loop structure - Google Patents
Voltage signal conversion module and phase-locked loop structure Download PDFInfo
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Abstract
The invention provides a voltage signal conversion module and a phase-locked loop structure, comprising: a discharge control unit generating a control signal; one end of the discharging switch unit is connected with the upper polar plate of the capacitor, the other end of the discharging switch unit is connected with one end of the pull-down unit, and the control end of the discharging switch unit is connected with a control signal; the pull-down unit is controlled by the input signal; a charging switch unit, one end of which is connected with the power supply voltage, the other end of which is connected with the upper polar plate of the capacitor, and the control end of which is connected with the connection node of the discharging switch unit and the pull-down unit; the potential adjusting unit is connected with the lower polar plate of the capacitor; and one end of the grid voltage bootstrapping switch unit is connected with the lower polar plate of the capacitor, the other end of the grid voltage bootstrapping switch unit receives the bias voltage, and the grid electrode is connected with the connection node of the discharging switch unit and the pull-down unit and outputs an output signal. The invention can solve the level conversion requirement in a high-frequency high-speed scene; the method has the advantages of high response speed, small duty ratio error, low delay and the like; and only one low voltage domain is needed, which is convenient for the preparation, layout and control of the device.
Description
Technical Field
The present invention relates to the field of radio frequency circuits, and in particular, to a voltage signal conversion module and a phase-locked loop structure.
Background
Currently, as the trend of advanced processes evolves toward high speed and low voltage, the reliability of analog rf circuits presents a better challenge. In the advanced process, a standard low-voltage tube and a thick gate high-voltage tube are commonly used in a matched mode; the standard low-voltage transistor has the advantages of high speed, small parasitic, high cut-off frequency and the like, but has lower withstand voltage; thick gate high voltage tubes can operate at high power domain voltages, but it is difficult to meet the high speed high frequency response speed requirements. In some use scenarios of level shifting for low voltage to high voltage, a level shifting circuit (level shifter) is generally used, but the level shifting circuit still has a problem of insufficient shifting speed.
For example, in the actual production design process related to the present invention, as shown in fig. 1, for an analog phase-locked loop, when the phase frequency detector 1 (PFD) and the charge pump 2 (CP) are in the same voltage domain, no voltage conversion is required; however, when the phase frequency detector 1 outputs a voltage control signal in a low voltage domain and the charge pump 2 needs a higher control voltage to turn on or off an internal switching transistor module (as shown in fig. 2), this means that level conversion needs to be performed between the phase frequency detector 1 in the low voltage domain and the charge pump 2 in the high voltage domain, and when the clock is up to GHz, the low-voltage high-speed transistor cannot directly drive the switching transistor of the charge pump 2, so that high-speed voltage conversion needs to be performed, and meanwhile, a larger delay and error with a larger duty ratio cannot be introduced.
Fig. 3 shows a structure of a conventional low-to-high level conversion circuit 3, which includes two voltage domains, namely, a power supply voltage vdd_dig of a low voltage domain and a power supply voltage vdd_ana of a high voltage domain. After the input CLK signal passes through the two-stage inverters in the low voltage domain, two grid voltages with opposite phases are respectively provided for the NMOS transistors N1 and N2, the sources of the NMOS transistors N1 and N2 are grounded, and the drains are respectively connected with the sources of the NMOS transistors N3 and N4; the gates of the NMOS tubes N3 and N4 receive bias voltage Vbias, and the drains are respectively connected with the drains of the PMOS tubes P1 and P2; the PMOS tubes P1 and P2 are cross-coupled (the grid electrode and the drain electrode are cross-connected with each other), and the source electrode is connected with the VDD_ANA; the PMOS transistor P3 and the NMOS transistor N5 form an inverter structure (power supply voltage vdd_ana) and output the signal Vout. The input CLK signal is a square wave pulse signal with a certain duty ratio, the low level is 0, and the high level is VDD_DIG; the output signal Vout is a square wave pulse signal having the same duty ratio as the input CLK signal, and has a low level of 0 and a high level of vdd_ana; the main difference is that vdd_ana is greater than vdd_dig, and finally, the conversion from a low-voltage domain square wave pulse signal to a high-voltage domain square wave pulse signal is realized, and in the ideal case, the pulse width duty ratio is kept unchanged, and the output signal is not delayed compared with the input signal. As shown in fig. 4, when the square wave pulse signal output by the phase frequency detector 1 works at the upper GHz frequency and is a waveform with a narrower duty ratio, the level conversion circuit 3 has a poor signal conversion effect, and there is a large delay and degradation of the duty ratio, which can not accurately give the phase difference after the phase frequency detection to the charge pump 2, and finally has a large influence on the loop locking function and noise spurious of the phase-locked loop.
Therefore, how to provide a high-speed voltage signal conversion module with a faster conversion speed, a lower delay and a smaller duty cycle conversion error has become one of the problems to be solved by those skilled in the art.
It should be noted that the foregoing description of the background art is only for the purpose of providing a clear and complete description of the technical solution of the present invention and is presented for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background of the invention section.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an objective of the present invention is to provide a voltage signal conversion module and a phase-locked loop structure, which are used for solving the problems of the prior art that the high-speed voltage signal conversion effect is not ideal, and there is a large delay and a deteriorated duty ratio.
To achieve the above and other related objects, the present invention provides a voltage signal conversion module, including at least:
the device comprises a discharge control unit, a discharge switch unit, a pull-down unit, a charging switch unit, a capacitor, a potential regulating unit and a grid voltage bootstrap switch unit;
the discharging control unit is connected between the power supply voltage and the lower polar plate of the capacitor, receives an input signal and an output signal and is used for generating a control signal of the discharging switch unit;
one end of the discharge switch unit is connected with the upper polar plate of the capacitor, the other end of the discharge switch unit is connected with one end of the pull-down unit, and the control end of the discharge switch unit is connected with the output end of the discharge control unit; the other end of the pull-down unit is grounded and controlled by the input signal;
one end of the charging switch unit is connected with the power supply voltage, the other end of the charging switch unit is connected with an upper polar plate of the capacitor, and a control end of the charging switch unit is connected with a connection node of the discharging switch unit and the pull-down unit;
the potential regulating unit is connected with the lower polar plate of the capacitor and is controlled by the input signal;
one end of the grid voltage bootstrap switch unit is connected with the lower polar plate of the capacitor, the other end of the grid voltage bootstrap switch unit receives bias voltage, and the grid electrode is connected with the connection node of the discharge switch unit and the pull-down unit and outputs the output signal;
when the input signal is at a low level, the pull-down unit and the charging switch unit are turned on, the discharging switch unit is turned off, the potential regulating unit is turned on and pulls down the lower polar plate of the capacitor to the ground, and the output signal is consistent with the input signal level; when the input signal is at a high level, the pull-down unit, the charging switch unit and the potential regulating unit are turned off, the discharging switch unit is turned on, and the level of the output signal is the sum of the level of the input signal and the bias voltage.
Optionally, the discharge control unit includes a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor;
the grid electrodes of the first PMOS tube and the first NMOS tube are connected with the input signal; the source electrode of the first PMOS tube is connected with the power supply voltage, and the drain electrode of the first PMOS tube is connected with the drain electrodes of the first NMOS tube and the second NMSO tube and outputs the control signal of the discharge switch unit; the source electrode of the first NMOS tube and the source electrode of the second NMOS tube are connected with the lower polar plate of the capacitor; and the grid electrode of the second NMOS tube is connected with the output signal.
More optionally, the discharging switch unit includes a second PMOS transistor, where a source of the second PMOS transistor is connected to an upper plate of the capacitor, a drain of the second PMOS transistor is connected to the pull-down unit, and a gate of the second PMOS transistor is connected to an output terminal of the discharging control unit.
More optionally, the charging switch unit includes a third PMOS transistor, where a source of the third PMOS transistor is connected to the power supply voltage, a drain of the third PMOS transistor is connected to an upper plate of the capacitor, and a gate of the third PMOS transistor is connected to an output terminal of the discharging switch unit.
Optionally, the pull-down unit includes at least two NMOS transistors connected in series, wherein a gate of each of the NMOS transistors is connected to a signal opposite to the input signal or the power supply voltage, respectively.
Optionally, the potential regulating unit includes a third NMOS transistor, where a drain electrode of the third NMOS transistor is connected to a lower plate of the capacitor, a gate electrode of the third NMOS transistor is connected to an inverse signal of the input signal, and a source electrode of the third NMOS transistor is grounded.
Optionally, the gate voltage bootstrapping switch unit includes a fourth NMOS, where a drain electrode of the fourth NMOS is connected to a lower electrode plate of the capacitor, a source electrode of the fourth NMOS is connected to the bias voltage, and a gate electrode of the fourth NMOS is connected to a connection node of the discharge switch unit and the pull-down unit and is used as an output end of the voltage signal conversion module.
Optionally, the frequency of the input signal is greater than or equal to 0.2GHz.
To achieve the above and other related objects, the present invention also provides a phase locked loop structure, including at least:
a phase frequency detector, a charge pump, a low pass filter, a voltage controlled oscillator, a frequency divider and a voltage signal conversion module according to any one of claims 1-8;
the input end of the phase frequency detector is connected with a reference signal and a feedback signal, and the phase difference of the reference signal and the feedback signal is output;
the voltage signal conversion module is connected to the output end of the phase frequency detector and is used for converting the output signal of the phase frequency detector from a low voltage domain to a high voltage domain;
the charge pump is connected to the output end of the voltage signal conversion module and generates a control signal based on the output signal of the voltage signal conversion module;
the low-pass filter is connected to the output end of the charge pump and is used for carrying out low-pass filtering on the output signal of the charge pump;
the voltage-controlled oscillator is connected to the output end of the low-pass filter, and generates and outputs an oscillating signal with corresponding frequency based on the control signal after low-pass filtering;
the frequency divider is connected to the output end of the voltage-controlled oscillator, divides the frequency of the oscillation signal and feeds the frequency-divided oscillation signal back to the phase frequency detector as a feedback signal;
the phase frequency detector and the voltage signal conversion module are in a low voltage domain, and the charge pump is in a high voltage domain.
Optionally, the phase-locked loop structure further includes a sigma-delta modulator, and the sigma-delta modulator is connected to the output end of the frequency divider, performs sigma-delta modulation based on the output signal of the frequency divider to determine a frequency division coefficient of the frequency divider, and feeds back to the frequency divider.
As described above, the voltage signal conversion module and the phase-locked loop structure of the present invention have the following beneficial effects:
the voltage signal conversion module and the phase-locked loop structure can solve the level conversion requirement in a high-frequency high-speed scene; the method has the advantages of high response speed, small duty ratio error, low delay and the like; and only one low voltage domain is needed, which is convenient for the preparation, layout and control of the device.
Drawings
Fig. 1 shows a schematic diagram of a phase frequency detector and a charge pump in the same voltage domain.
Fig. 2 shows a schematic diagram of a configuration of a level shifter circuit for setting the phase frequency detector and the charge pump in different voltage domains.
Fig. 3 is a schematic diagram showing the structure of the level shifter circuit.
Fig. 4 is a schematic structural diagram of a voltage signal conversion module according to the present invention.
Fig. 5 is a schematic waveform diagram of an input signal and an output signal of the voltage signal conversion module according to the present invention.
Fig. 6 is a schematic diagram of a phase locked loop structure according to the present invention.
Fig. 7 is a schematic diagram showing a connection relationship between the voltage signal conversion module and the pll structure according to the present invention.
Description of element reference numerals
1. Phase frequency detector
2. Charge pump
3. Level conversion circuit
4. Voltage signal conversion module
4a discharge control unit
4b discharge switch unit
4c pull-down unit
4d charging switch unit
4e potential regulating unit
4f grid voltage bootstrapping switch unit
5. Low pass filter
6. Voltage controlled oscillator
7. Frequency divider
8. Sigma-delta modulator
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 4-7. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
The level conversion module with the traditional structure can realize a low-speed conversion function, and the highest level conversion function generally reaches the working range of hundred MHz frequency; in an operating scenario with too high a frequency, the slew rate may be insufficient, resulting in a large delay, and inconsistent deterioration of the duty cycle under process variations and temperature variations. Based on the above-mentioned problems, the present invention provides a voltage signal conversion module 4, as shown in fig. 4, the voltage signal conversion module 4 includes:
a discharge control unit 4a, a discharge switch unit 4b, a pull-down unit 4C, a charge switch unit 4d, a capacitor C, a potential adjustment unit 4e, and a gate voltage bootstrap switch unit 4f.
As shown in fig. 4, the discharge control unit 4a is connected between the power voltage VDD and the lower plate of the capacitor C, and receives an input signal and an output signal Vout for generating a control signal of the discharge switch unit 4 b.
Specifically, in the present embodiment, the input signal of the voltage signal conversion module 4 is a square wave pulse signal (denoted by CLK in the figure), and any signal that needs to be level-converted in practical use is suitable for the present invention, which is not limited to the present embodiment.
Specifically, the discharge control unit 4a provides a control signal to the discharge switch unit 4b, and controls the discharge switch unit 4b to be turned off when the input signal CLK is at a low level; when the input signal CLK is at a high level, the discharge switch unit 4b is controlled to be turned on. As an example, as shown in fig. 4, the discharge control unit 4a includes a first PMOS transistor MP1, a first NMOS transistor MN1, and a second NMOS transistor MN2. The gates of the first PMOS MP1 and the first NMOS MN1 are connected to the input signal CLK. The source electrode of the first PMOS MP1 is connected to the power supply voltage VDD, and the drain electrode is connected to the drain electrodes of the first NMOS MN1 and the second NMSO MN2, and outputs the control signal of the discharge switch unit 4 b. The sources of the first NMOS transistor MN1 and the second NMOS transistor MN2 are connected with the lower polar plate of the capacitor C. The gate of the second NMOS MN2 is connected to the output signal Vout. In practical use, any circuit structure capable of generating a control signal for turning off the discharge switch unit 4b when the input signal CLK is at a low level and generating a control signal for turning on the discharge switch unit 4b when the input signal CLK is at a high level is suitable for the present invention, and will not be described in detail herein.
As shown in fig. 4, one end of the discharging switch unit 4b is connected to the upper electrode plate of the capacitor C, the other end is connected to one end of the pull-down unit, and the control end is connected to the output end of the discharging control unit 4 a.
Specifically, in this embodiment, the discharge switch unit 4b includes a second PMOS transistor MP2, where a source of the second PMOS transistor MP2 is connected to the upper plate of the capacitor C, a drain of the second PMOS transistor MP is connected to the pull-down unit 111, and a gate of the second PMOS transistor MP is connected to the output end of the discharge control unit 4 a. In practical use, the structure of the discharge switch unit may be set according to needs, which is not limited to the present embodiment.
As shown in fig. 4, one end of the pull-down unit 4c is connected to the output end of the discharge switch unit 4b, and the other end is grounded and controlled by the input signal CLK.
Specifically, the pull-down unit 4c is configured to provide a pull-down path when the input signal CLK is at a low level, that is, the pull-down unit 4c is turned on when the input signal CLK is at a low level; when the input signal CLK is at a high level, the pull-down unit 4c is turned off; in the present embodiment, the pull-down unit 4c receives the inverse signal CLKB of the input signal, and controls the pull-down unit 4c to be turned on or off based on the inverse signal CLKB of the input signal. As an example, the pull-down unit 4c includes at least two NMOS transistors connected in series, wherein the gate of each NMSO transistor is connected to the counter signal CLKB of the input signal or the power supply voltage VDD, respectively; in this example, the pull-down unit 4c includes two NMOS transistors, namely a fifth NMOS transistor MN5 and a sixth NMOS transistor MN6; the drain electrode of the fifth NMOS tube MN5 is connected with the output end of the discharge switch unit 4b, the grid electrode is connected with the power supply voltage VDD, and the source electrode is connected with the drain electrode of the sixth NMOS tube MN6; the gate of the sixth NMOS transistor MN6 receives the inverse signal CLKB of the input signal, and the source is grounded; the fifth NMOS MN5 is in a normally-on state, and is configured to divide the voltage so that the drain-source voltage of the sixth NMOS MN6 (typically, a low voltage tube with a high-speed switching characteristic) does not exceed the maximum voltage that the sixth NMOS MN6 can withstand; the number of the NMOS transistors connected in series in the pull-down unit 4c may be set according to the requirement, and is not limited to this embodiment.
As shown in fig. 4, one end of the charging switch unit 4d is connected to the power voltage VDD, the other end is connected to the upper electrode plate of the capacitor C, and the control end is connected to the connection node of the discharging switch unit 4b and the pull-down unit 4C.
Specifically, the charging switch unit 4d is controlled by the voltage of the connection node of the discharging switch unit 4b and the pull-down unit 4c, the charging switch unit 4d is turned on when the input signal CLK is at a low level, and the charging switch unit 4d is turned off when the input signal CLK is at a high level. In this embodiment, the charging switch unit 4d includes a third PMOS MP3, where a source of the third PMOS MP3 is connected to the power supply voltage VDD, a drain of the third PMOS MP3 is connected to the upper plate of the capacitor C, and a gate of the third PMOS MP is connected to a connection node between the discharging switch unit 4b and the pull-down unit 4C. In practical use, the structure of the charging switch unit may be set as required, which is not limited to the present embodiment.
As shown in fig. 4, the potential adjusting unit 4e is connected to the lower plate of the capacitor C and is controlled by the input signal CLK.
Specifically, when the input signal CLK is at a low level, the potential regulating unit 4e is turned on, and pulls down the lower plate potential of C of the capacitor to ground; when the input signal CLK is at a high level, the potential regulating unit 4e is turned off, and the lower plate potential of the capacitor C is provided by the gate voltage bootstrap switch unit 4 f; in the present embodiment, the potential adjusting unit 4e receives the inverse signal CLKB of the input signal, and controls the potential adjusting unit 4e to be turned on or off based on the inverse signal CLKB of the input signal. As an example, the potential adjusting unit 4e includes a third NMOS transistor MN3, where a drain of the third NMOS transistor MN3 is connected to a lower plate of the capacitor C, a gate is connected to a counter signal CLKB of the input signal, and a source is grounded. In practical use, any circuit structure capable of realizing the adjustment of the potential of the lower polar plate of the capacitor is suitable for the present invention, and is not limited by the present embodiment.
As shown in fig. 4, one end of the gate voltage bootstrap switch unit 4f is connected to the lower electrode plate of the capacitor C, the other end receives the bias voltage Vbias, and the gate is connected to the connection node of the discharge switch unit 4b and the pull-down unit 4C and outputs the output signal Vout.
Specifically, the gate voltage bootstrapping switch unit 4f is configured to implement gate voltage bootstrapping, when the input signal CLK is at a low level, the output signal Vout is pulled down to ground by the pull-down unit 4c, and the output signal Vout is at a low level (consistent with the level of the input signal CLK, i.e., 0); when the input signal CLK is at a high level, the level of the output signal Vout is identical to the level of the upper plate of the capacitor C, and the output signal Vout is at a high level (i.e., vdd+vbias is the sum of the level of the input signal CLK and the bias voltage Vbias). As an example, the gate voltage bootstrap switch unit 4f includes a fourth NMOS transistor MN4, where a drain of the fourth NMOS transistor MN4 is connected to a lower plate of the capacitor C, a source of the fourth NMOS transistor is connected to the bias voltage Vbias, and a gate of the fourth NMOS transistor is connected to a connection node of the discharge switch unit 4b and the pull-down unit 4C and is used as an output end of the voltage signal conversion module 4. In practical use, any circuit structure capable of implementing the gate voltage bootstrap is suitable for the present invention, and is not limited by the present embodiment.
The operating principle of the voltage signal conversion module 4 of the present invention is as follows:
as an example, the input signal CLK of the voltage signal conversion module 4 is a square wave pulse signal, the inverse signal CLKB of the input signal and the input signal CLK are 180 ° inverted, the low level is 0, and the high level is the power supply voltage VDD (including but not limited to 0.8V) of the low voltage domain.
When the input signal CLK is at a low level (0), the fifth NMOS transistor MN5 is turned on with the sixth NMOS transistor MN6 (the pull-down unit 4C is turned on), the output signal Vout is 0, the fourth NMOS transistor MN4 is turned off, the third PMOS transistor MP3 is turned on (the charging switch unit 4d is turned on), the power supply voltage VDD charges the capacitor C via the third PMOS transistor MP3, and the upper plate of the capacitor C is charged to VDD. Meanwhile, the first NMOS transistor MN1 and the second NMOS transistor MN2 are turned off, the first PMOS transistor MP1 is turned on (the discharge control unit 4a outputs a high level), and the second PMOS transistor MP2 is turned off (the discharge switch unit 4b is turned off); and if the third NMOS MN3 is turned on (the potential adjusting unit 4e is turned on), the potential of the lower plate of the capacitor C is 0.
When the input signal CLK is at a high level (VDD), the sixth NMOS transistor MN6 is turned off (the pull-down unit 4c is turned off), and the third NMOS transistor MN3 is turned off (the potential adjusting unit 4e is turned off); the first NMOS transistor MN1 is turned on with the second NMOS transistor MN2, and the first PMOS transistor MP1 is turned off, so that the second PMOS transistor MP2 is turned on (the discharging switch unit 4b is turned on), and the capacitor C discharges through the second PMOS transistor MP 2; with the drain voltage of the second PMOS transistor MP2 continuously rising, the third PMOS transistor MP3 is turned off (the charging switch unit 4d is turned off), the fourth NMOS transistor MN4 is turned on, the lower plate potential of the capacitor C is raised from 0 to the bias voltage Vbias (given direct current signal), the upper plate potential of the capacitor C is raised to vdd+vbias, the gate voltage of the second NMOS transistor MN2 is raised to vdd+vbias (the second NMOS transistor is used for preventing the bias voltage Vbias from being transferred to the gate of the second PMOS transistor MP2 when the first NMOS transistor MN1 is in a poor conduction state in a scene with higher Vbias), so that the second PMOS transistor MP2 can still be normally turned on when the upper plate potential of the capacitor C is raised to vdd+vbias; meanwhile, the gate voltage of the fourth NMOS MN4 is also raised to vdd+vbias, so as to bootstrap the gate voltage of the fourth NMOS MN4, and the bootstrap gate voltage is output as the output signal Vout.
As shown in fig. 5, the voltage signal conversion module 4 of the present invention can perfectly convert the clock signal in the low voltage domain (i.e. the input signal Vin) into the clock signal in the high voltage domain (i.e. the output signal Vout), the duty ratio is unchanged, and the delay is very small; therefore, the invention has the advantages of high response speed and low delay. Moreover, unlike the level shift, which requires two voltage domains separately, the present invention requires only one low voltage domain, and can achieve boost conversion of the high-speed inversion signal by only one low power supply voltage and one dc bias with a lower level (of course, the bias voltage may also be higher than the power supply voltage of the low voltage domain, and set as needed). The invention can perfectly solve the level conversion requirement under the high-speed scene of high frequency (as an example, the frequency of the input signal is more than or equal to 0.2GHz, including but not limited to 0.5GHz, 1GHz, 2GHz and 3GHz, which are not described in detail herein).
As shown in fig. 6, the present invention further provides a phase-locked loop structure, which includes:
the phase frequency detector 1, the charge pump 2, the voltage signal conversion module 4, the low-pass filter 5, the voltage-controlled oscillator 6 and the frequency divider 7.
As shown in fig. 6, the input end of the phase frequency detector 1 is connected to a reference signal REF and a feedback signal FB, and outputs a phase difference between the reference signal REF and the feedback signal FB. Any circuit structure capable of implementing frequency discrimination and phase discrimination is suitable for the present invention, and is not described in detail herein.
As shown in fig. 6, the voltage signal conversion module 4 is connected to the output end of the phase frequency detector 1, and is configured to convert the output signal of the phase frequency detector 1 from a low voltage domain to a high voltage domain.
Specifically, the circuit structure and the working principle of the voltage signal conversion module 4 are referred to above, and are not described in detail herein. It should be noted that, as shown in fig. 7, if the phase frequency detector 1 outputs two paths of square wave pulse width signals up_l and dn_l with different duty ratios, two voltage signal conversion modules 4 are required to be correspondingly set, and each voltage signal conversion module works based on a differential signal (not shown in fig. 7) of a corresponding signal, which is not described in detail herein. The voltage signal conversion module 4 and the phase frequency detector 1 are positioned in a low voltage domain.
As shown in fig. 6, the charge pump 2 is connected to the output terminal of the voltage signal conversion module 4, and generates a control signal based on the output signal of the voltage signal conversion module 4.
Specifically, as shown in fig. 7, in the present embodiment, the charge pump 2 includes a first current source Iup, a second current source Idn, an operational amplifier, and four switching transistors. One end of the first current source Iup is connected with a power supply of a high-voltage domain, and the other end of the first current source Iup is connected with the first ends of the first switch and the second switch; the first switch is connected in series with the third switch, and the second switch is connected in series with the fourth switch; the other ends of the third switch and the fourth switch are connected with the first end of the second current source Idn; the second terminal of the second current source Idn is grounded; the first input end of the operational amplifier is connected with the connecting node of the second switch and the fourth switch, the second input end of the operational amplifier is connected with the output end, and the output end of the operational amplifier is connected with the connecting node of the first switch and the third switch. The connection node of the second switch and the fourth switch outputs the control signal (Iout in the present embodiment), and each switch is controlled by the output signal of the voltage signal conversion module 4. Any circuit structure capable of implementing the charge pump function is suitable for the present invention, and is not limited to this embodiment. The charge pump 2 is in the high voltage domain.
As shown in fig. 6, the low-pass filter is connected to the output end of the charge pump, and performs low-pass filtering on the output signal of the charge pump 2; any low pass filter structure is suitable for use in the present invention.
As shown in fig. 6, the voltage-controlled oscillator 6 is connected to the output end of the low-pass filter 5, and generates and outputs an oscillation signal OSC with a corresponding frequency based on the low-pass filtered control signal; any voltage controlled oscillator configuration is suitable for use with the present invention.
As shown in fig. 6, the frequency divider 7 is connected to the output end of the voltage-controlled oscillator 6, and divides the frequency of the oscillation signal OSC and feeds back the divided frequency as a feedback signal FB to the phase frequency detector 1. The frequency divider 7 is an integer frequency division or a fractional frequency division, and any frequency divider structure is suitable for the present invention.
As shown in fig. 6, as another implementation manner of the present invention, the phase-locked loop structure further includes a sigma-delta modulator 8, where the sigma-delta modulator 8 is connected to an output terminal of the frequency divider 7, performs sigma-delta modulation based on an output signal of the frequency divider 7 to determine a frequency division coefficient of the frequency divider 7, and feeds back to the frequency divider 7. Any circuit structure capable of obtaining the frequency division coefficient of the frequency divider is suitable for the invention, and is not described in detail herein.
It should be noted that, any application scenario where a signal in a low voltage domain needs to be converted into a signal in a high voltage domain may adopt the voltage signal conversion module 4 of the present invention, and the application scenario is not limited to the phase-locked loop structure listed in the present embodiment.
In summary, the present invention provides a voltage signal conversion module and a phase-locked loop structure, including: the device comprises a discharge control unit, a discharge switch unit, a pull-down unit, a charging switch unit, a capacitor, a potential regulating unit and a grid voltage bootstrap switch unit; the discharging control unit is connected between the power supply voltage and the lower polar plate of the capacitor, receives an input signal and an output signal and is used for generating a control signal of the discharging switch unit; one end of the discharge switch unit is connected with the upper polar plate of the capacitor, the other end of the discharge switch unit is connected with one end of the pull-down unit, and the control end of the discharge switch unit is connected with the output end of the discharge control unit; the other end of the pull-down unit is grounded and controlled by the input signal; one end of the charging switch unit is connected with the power supply voltage, the other end of the charging switch unit is connected with an upper polar plate of the capacitor, and a control end of the charging switch unit is connected with a connection node of the discharging switch unit and the pull-down unit; the potential regulating unit is connected with the lower polar plate of the capacitor and is controlled by the input signal; one end of the grid voltage bootstrap switch unit is connected with the lower polar plate of the capacitor, the other end of the grid voltage bootstrap switch unit receives bias voltage, and the grid electrode is connected with the connection node of the discharge switch unit and the pull-down unit and outputs the output signal; when the input signal is at a low level, the pull-down unit and the charging switch unit are turned on, the discharging switch unit is turned off, the potential regulating unit is turned on and pulls down the lower polar plate of the capacitor to the ground, and the output signal is consistent with the input signal level; when the input signal is at a high level, the pull-down unit, the charging switch unit and the potential regulating unit are turned off, the discharging switch unit is turned on, and the level of the output signal is the sum of the level of the input signal and the bias voltage. The voltage signal conversion module and the phase-locked loop structure can solve the level conversion requirement in a high-frequency high-speed scene; the method has the advantages of high response speed, small duty ratio error, low delay and the like; and only one low voltage domain is needed, which is convenient for the preparation, layout and control of the device. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. A voltage signal conversion module, the voltage signal conversion module comprising at least:
the device comprises a discharge control unit, a discharge switch unit, a pull-down unit, a charging switch unit, a capacitor, a potential regulating unit and a grid voltage bootstrap switch unit;
the discharging control unit is connected between the power supply voltage and the lower polar plate of the capacitor, receives an input signal and an output signal and is used for generating a control signal of the discharging switch unit;
one end of the discharge switch unit is connected with the upper polar plate of the capacitor, the other end of the discharge switch unit is connected with one end of the pull-down unit, and the control end of the discharge switch unit is connected with the output end of the discharge control unit; the other end of the pull-down unit is grounded and controlled by the input signal;
one end of the charging switch unit is connected with the power supply voltage, the other end of the charging switch unit is connected with an upper polar plate of the capacitor, and a control end of the charging switch unit is connected with a connection node of the discharging switch unit and the pull-down unit;
the potential regulating unit is connected with the lower polar plate of the capacitor and is controlled by the input signal;
one end of the grid voltage bootstrap switch unit is connected with the lower polar plate of the capacitor, the other end of the grid voltage bootstrap switch unit receives bias voltage, and the grid electrode is connected with the connection node of the discharge switch unit and the pull-down unit and outputs the output signal;
when the input signal is at a low level, the pull-down unit and the charging switch unit are turned on, the discharging switch unit is turned off, the potential regulating unit is turned on and pulls down the lower polar plate of the capacitor to the ground, and the output signal is consistent with the input signal level; when the input signal is at a high level, the pull-down unit, the charging switch unit and the potential regulating unit are turned off, the discharging switch unit is turned on, and the level of the output signal is the sum of the level of the input signal and the bias voltage.
2. The voltage signal conversion module of claim 1, wherein: the discharge control unit comprises a first PMOS tube, a first NMOS tube and a second NMOS tube;
the grid electrodes of the first PMOS tube and the first NMOS tube are connected with the input signal; the source electrode of the first PMOS tube is connected with the power supply voltage, and the drain electrode of the first PMOS tube is connected with the drain electrodes of the first NMOS tube and the second NMSO tube and outputs the control signal of the discharge switch unit; the source electrode of the first NMOS tube and the source electrode of the second NMOS tube are connected with the lower polar plate of the capacitor; and the grid electrode of the second NMOS tube is connected with the output signal.
3. The voltage signal conversion module according to claim 1 or 2, characterized in that: the discharging switch unit comprises a second PMOS tube, a source electrode of the second PMOS tube is connected with an upper polar plate of the capacitor, a drain electrode of the second PMOS tube is connected with the pull-down unit, and a grid electrode of the second PMOS tube is connected with an output end of the discharging control unit.
4. A voltage signal conversion module according to claim 3, characterized in that: the charging switch unit comprises a third PMOS tube, the source electrode of the third PMOS tube is connected with the power supply voltage, the drain electrode of the third PMOS tube is connected with the upper polar plate of the capacitor, and the grid electrode of the third PMOS tube is connected with the output end of the discharging switch unit.
5. The voltage signal conversion module of claim 1, wherein: the pull-down unit comprises at least two NMOS tubes connected in series, wherein the grid electrode of each NMSO tube is respectively connected with the counter signal of the input signal or the power supply voltage.
6. The voltage signal conversion module of claim 1, wherein: the potential regulating unit comprises a third NMOS tube, the drain electrode of the third NMOS tube is connected with the lower polar plate of the capacitor, the grid electrode of the third NMOS tube is connected with the inverse signal of the input signal, and the source electrode of the third NMOS tube is grounded.
7. The voltage signal conversion module of claim 1, wherein: the grid voltage bootstrapping switch unit comprises a fourth NMOS tube, the drain electrode of the fourth NMOS tube is connected with the lower polar plate of the capacitor, the source electrode of the fourth NMOS tube is connected with the bias voltage, and the grid electrode of the fourth NMOS tube is connected with the connection node of the discharge switch unit and the pull-down unit and serves as the output end of the voltage signal conversion module.
8. The voltage signal conversion module of claim 1, wherein: the frequency of the input signal is more than or equal to 0.2GHz.
9. A phase locked loop structure, the phase locked loop structure comprising at least:
a phase frequency detector, a charge pump, a low pass filter, a voltage controlled oscillator, a frequency divider and a voltage signal conversion module according to any one of claims 1-8;
the input end of the phase frequency detector is connected with a reference signal and a feedback signal, and the phase difference of the reference signal and the feedback signal is output;
the voltage signal conversion module is connected to the output end of the phase frequency detector and is used for converting the output signal of the phase frequency detector from a low voltage domain to a high voltage domain;
the charge pump is connected to the output end of the voltage signal conversion module and generates a control signal based on the output signal of the voltage signal conversion module;
the low-pass filter is connected to the output end of the charge pump and is used for carrying out low-pass filtering on the output signal of the charge pump;
the voltage-controlled oscillator is connected to the output end of the low-pass filter, and generates and outputs an oscillating signal with corresponding frequency based on the control signal after low-pass filtering;
the frequency divider is connected to the output end of the voltage-controlled oscillator, divides the frequency of the oscillation signal and feeds the frequency-divided oscillation signal back to the phase frequency detector as a feedback signal;
the phase frequency detector and the voltage signal conversion module are in a low voltage domain, and the charge pump is in a high voltage domain.
10. The phase locked loop structure of claim 9, wherein: the phase-locked loop structure further comprises a sigma-delta modulator, wherein the sigma-delta modulator is connected to the output end of the frequency divider, performs sigma-delta modulation based on the output signal of the frequency divider to determine the frequency division coefficient of the frequency divider, and feeds back the frequency division coefficient to the frequency divider.
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