CN113098455B - High-speed bootstrap switch with low on-resistance - Google Patents
High-speed bootstrap switch with low on-resistance Download PDFInfo
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- CN113098455B CN113098455B CN202110400292.8A CN202110400292A CN113098455B CN 113098455 B CN113098455 B CN 113098455B CN 202110400292 A CN202110400292 A CN 202110400292A CN 113098455 B CN113098455 B CN 113098455B
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Abstract
The invention discloses a high-speed bootstrap switch with low on-resistance, which comprises an input port IN, a bootstrap switch and a control circuit, wherein the input port IN is used for receiving input voltage; an output port OUT for outputting a voltage; the power supply voltage VDD, the timing switch CLK, the reverse clock voltages CLKR and CLKRB are used for controlling the timing on-off of the circuit together; 13 NMOS transistors, 2 PMOS transistors and four capacitors; the high-speed bootstrap switch integrally comprises a clock multiplication circuit, a charge pump circuit and a switch circuit. According to the invention, through the combination of clock multiplication and a charge pump, the gate-source difference of the MOS tube of the switch is increased from the basic VDD to 2VDD, so that the on-resistance of the switch tube is reduced, the voltage redundancy of the switch tube is improved, and the excellent working performance and high sampling rate of the bootstrap switch are realized.
Description
Technical Field
The invention relates to the field of analog integrated circuits, in particular to a high-speed bootstrap switch with low on-resistance, which is mainly used for a digital-to-analog conversion part of an integrated circuit in the fields of high-speed low-voltage A/D converters and the like.
Background
High-speed transmission systems have become a hot spot in research today, and 5G and emerging wireless standards have an increasing demand for high-speed and high-resolution ADCs in recent years. The bootstrap switch is used as a signal sampling module of the ADC, and plays an important role in the accuracy of signal processing and ADC conversion results.
As a mainstream ADC, a Pipeline analog-to-digital converter (Pipeline ADC) is widely used due to its advantages of high resolution, high sampling speed, and the like, where a signal sampling module plays a key role in subsequent analog-to-digital conversion. In general, in a switched capacitor circuit, an analog input signal is sampled using MOS switches or transmission gates. Under ideal conditions, the sampling value of an output signal is the same as that of an original signal, due to the fact that an MOS tube has an on-resistance in a CMOS process, the change of voltage difference of a grid source level can cause the change of the on-resistance, meanwhile, the linearity is poorer due to the fact that charge injection and clock feed-through phenomena are changed along with a clock, and the performance of a circuit is reduced.
The bootstrap switch solves the problem that the common MOS tube can be conducted only when the input voltage of the switch is greater than the threshold voltage, and has obvious circuit performance improvement compared with a common switch capacitor switch circuit.
The existing bootstrap switch design charges a sampling capacitor to VDD through clock low level, and transmits input voltage plus the voltage VDD in the sampling capacitor to a grid electrode of a switch tube through clock high level, so that the grid source voltage of the switch tube keeps stable VDD unchanged along with the change of the input voltage. However, existing bootstrapping does not well fulfill the technical requirements of operating at higher sampling rates.
Disclosure of Invention
The invention aims to provide a high-speed bootstrap switch with low on-resistance, which can improve the working performance of a circuit under the requirements of high speed and high precision.
In order to realize the task, the invention adopts the following technical scheme:
a high speed bootstrapped switch having a low on-resistance, comprising a clock multiplication circuit, a charge pump circuit, and a switching circuit, wherein:
the clock multiplication circuit comprises NMOS transistors M1 and M2, capacitors C1 and C2 and an inverter; the drain of M1 and the drain of M2 are connected with a power supply voltage VDD, the gate of M1 is connected with the source of M2 and the upper plate of a capacitor C2, the gate of M2 is connected with the source of M1 and the upper plate of a capacitor C1, the lower plate of C1 is connected with a reverse clock voltage CLKR, and the CLKR passes through the inverter and then is connected with the lower plate of C2;
the charge pump circuit comprises NMOS transistors M3, M4, M5, M6 and M7, and capacitors C3 and C4; the drain of M3 and the drain of M4 are connected with a power supply voltage VDD, the gate of M3 and the gate of M4 are connected with the source of M1, the source of M3 is connected with the upper plate of C3 and the drain of M5, and the source of M4 is connected with the upper plate of C4; the grid of M5 is connected with the upper electrode plate of M2, the source of M5 is connected with the lower electrode plate of C4 and the drain of M7, the lower electrode plate of C3 is connected with the drain of M6, the grid of M6 and the grid of M7 are connected with a reverse clock voltage CLKR, the source of M6 and the source grounding terminal VSS of M7;
the switch circuit comprises PMOS transistors M8 and M10, NMOS transistors M9, M11, M12, M13, M14 and M15, wherein the grid electrode of M8 and the grid electrode of M9 are connected with a timing switch CLK, the source electrode of M8 and the grid electrode of M12 are connected with a power supply voltage VDD, the drain electrode of M8 is connected with the drain electrode of M9, the drain electrode of M11 and the grid electrode of M10, the source electrode of M9 is connected with the lower pole plate of C3, the source electrode of M11 and the source electrode of M14; the source of M10 is connected with the upper electrode plate of C4, the drain of M10 is connected with the grid of M11, the drain of M12, the grid of M14 and the grid of M15, the source of M12 is connected with the drain of M13, the grid of M13 is connected with the reverse clock voltage CLKRB, and the source of M13 is connected with the ground terminal VSS; the drain of M14 is connected to the input ports IN and the drain of M15, and the source of M15 is connected to the output port OUT.
Further, one PMOS transistor M18 and one NMOS transistor M19 are used to generate the inverted clock voltage CLKR: the source of M18 is connected to the power voltage VDD, the gate of M18, the gate of M19 is connected to the timing switch CLK, the source of M19 is connected to ground, the drain of M18 and the drain of M19 are connected to generate the reverse clock voltage CLKR.
Further, one PMOS transistor M20 and one NMOS transistor M21 are used to generate the inverted clock voltage CLKB: the source of M20 is connected to the power supply voltage VDD, the gate of M20 and the gate of M21 are connected to the timing switch CLK, the source of M21 is connected to ground, the drain of M20 and the drain of M21 are connected to generate the reverse clock voltage CLKB.
Further, when the high-speed bootstrap switch operates in the hold state:
the time sequence switch CLK is turned off, the CLKR and the CLKRB are in high level, the M6 and the M7 grid electrodes are in high level conduction, and the C3 and the C4 lower plate electrodes are in low voltage; meanwhile, the C1 lower electrode plate is in a high level directly controlled by CLKR, the C1 upper electrode plate and the M1 source electrode are in a high level with the M2, M3 and M4 grid electrodes, the M2, M3 and M4 are conducted, VDD flows to the C2, C3 and C4 capacitor upper electrode plates through M2, M3 and M4 to charge the C2, C3 and C4 to VDD; m1, M2, C1, and C2 constitute a clock multiplication circuit, so that M3, M4 charge C3, C4;
the CLK controls M8 to be turned on and M9 to be turned off, namely the gate is high level to control M10 to be turned off; VDD is connected with the grid of M12 to enable the grid to be normally conducted, CLKRB is connected with the grid of M13 to enable the grid of M13 to be conducted, the source of M13 is grounded, M11, M14 and M15 are controlled to be turned off through M12, and M10 and M14 isolate a switch from C4; m15 is turned off as a switch tube, the input signal IN can not pass through M15, and the output is kept unchanged.
Further, when the high-speed bootstrap switch works in a sampling state:
the CLK is converted into a high level, the CLKR and the CLKRB are converted into a low level, the grid electrodes of M6 and M7 are turned off at a low level, the lower plate of C1 is at a low voltage, and the lower plate of C2 is at a high voltage; the upper polar plate of the C2, namely the grid of the M1 reaches 2 times of VDD, the M1 is conducted, and the VDD charges the C1;
m5 gate voltage is 2 times VDD, M5 is conducted to enable C3, C4 and M5 to form a charge pump structure, meanwhile CLKRB is low level to enable M13 to be turned off, CLK high level controls M8 to be turned off, M9 and M10 to be conducted, namely M11, M14 and M15 are conducted; the input signal VIN flows to the source output OUT through the M15 switch tube, and simultaneously flows to the C3 through the M14, the charge pump structures of the C3, the M5 and the C4 pump the voltage of the upper plate of the C4 to double VDD + VIN, the voltage difference of the upper grid and the source of the switch tube M15 is double VDD, and therefore the whole high-speed bootstrap switch follows the input change to obtain the output with high linearity.
Further, the power supply voltage VDD is 1.8V.
A high speed low voltage A/D converter employs a high speed bootstrapped switch having a low on-resistance.
Compared with the prior art, the invention has the following technical characteristics:
1. compared with the traditional bootstrap switch, the design of the invention utilizes the charge pump principle and the clock multiplication module to increase the grid source voltage of the switch tube to two times of VDD, reduces the on-resistance of the switch tube, improves the linearity, and realizes the circuit to work at higher sampling rate; under the condition that no additional clock switch is added, the grid source value of the original switching tube is improved, the on-resistance of the switch is reduced, the linearity is improved, the grid voltage of the control tube of the sampling capacitor is improved, and the charging and discharging speed of the sampling capacitor is improved.
2. The switching tube has high grid voltage, provides larger voltage redundancy, can achieve higher grid voltage under the environment of high sampling rate and clock CLK high level, and can realize better working performance. At a sampling rate of 100M, the significand ENOB of the present invention is 14.52 bits, whereas the prior art significand ENOB is 13.09 bits, with significant performance advantages.
Drawings
FIG. 1 is a schematic circuit diagram of a high-speed bootstrap switch according to the present invention;
FIG. 2 is a waveform diagram of the input signal, the output signal, and the clock signal of the bootstrap switch circuit in the embodiment of the present invention;
FIG. 3 is a comparison of the gate-to-source voltage difference of the switch tube of the bootstrap switch circuit in the embodiment of the present invention and the gate-to-source voltage difference of the switch tube of the conventional bootstrap switch circuit;
FIG. 4 is a comparison of the on-resistance of the bootstrap switch circuit in the embodiment of the present invention and the on-resistance of the conventional bootstrap switch circuit;
FIGS. 5 (a) and (b) are dynamic parameters of the bootstrap switch circuit in the embodiment of the present invention under 100M;
fig. 6 (a) and (b) show the dynamic parameters of the conventional bootstrap switch circuit at 100M.
Detailed Description
Referring to fig. 1, the invention discloses a high-speed bootstrap switch with low on-resistance, which increases the gate-source difference of a switch MOS transistor from a basic VDD to 2VDD by combining clock multiplication and a charge pump, thereby reducing the on-resistance of the switch transistor, increasing the voltage redundancy of the switch transistor, and realizing superior working performance and high sampling rate of the bootstrap switch.
The invention relates to a high-speed bootstrap switch with low on-resistance, which comprises an input port IN, a bootstrap switch and a control unit, wherein the input port IN is used for receiving input voltage; an output port OUT for outputting a voltage; the supply voltage VDD is 1.8V in the embodiment; the timing switch CLK, the reverse clock voltages CLKR and CLKRB are used for controlling the timing on-off of the circuit; 13 NMOS transistors M1, M2, M3, M4, M5, M6, M7, M9, M11, M12, M13, M14, M15, and 2 PMOS transistors M8, M10, four capacitors C1, C2, C3, C4; the high-speed bootstrap switch integrally comprises a clock multiplication circuit, a charge pump circuit and a switch circuit. The circuit structure of each part in the present invention will be described with reference to fig. 1.
The clock multiplication circuit comprises NMOS transistors M1 and M2, capacitors C1 and C2 and an inverter; the drain of M1 and the drain of M2 are connected with a power supply voltage VDD, the gate of M1 is connected with the source of M2 and the upper plate of a capacitor C2, the gate of M2 is connected with the source of M1 and the upper plate of a capacitor C1, the lower plate of C1 is connected with a reverse clock voltage CLKR, and the CLKR passes through the inverter and then is connected with the lower plate of C2.
The charge pump circuit comprises NMOS transistors M3, M4, M5, M6 and M7, and capacitors C3 and C4; the drain of M3 and the drain of M4 are connected with a power supply voltage VDD, the gate of M3 and the gate of M4 are connected with the source of M1, the source of M3 is connected with the upper plate of C3 and the drain of M5, and the source of M4 is connected with the upper plate of C4; the gate of M5 is connected to the top plate of M2, the source of M5 is connected to the bottom plate of C4 and the drain of M7, the bottom plate of C3 is connected to the drain of M6, the gates of M6 and M7 are connected to the reverse clock voltage CLKR, the source of M6 and the source ground VSS of M7.
The switch circuit comprises PMOS transistors M8 and M10, NMOS transistors M9, M11, M12, M13, M14 and M15, wherein the grid electrode of M8 and the grid electrode of M9 are connected with a timing switch CLK, the source electrode of M8 and the grid electrode of M12 are connected with a power supply voltage VDD, the drain electrode of M8 is connected with the drain electrode of M9, the drain electrode of M11 and the grid electrode of M10, the source electrode of M9 is connected with the lower pole plate of C3, the source electrode of M11 and the source electrode of M14; the source of M10 is connected with the upper electrode plate of C4, the drain of M10 is connected with the grid of M11, the drain of M12, the grid of M14 and the grid of M15, the source of M12 is connected with the drain of M13, the grid of M13 is connected with the reverse clock voltage CLKRB, and the source of M13 is connected with the ground terminal VSS; the drain of M14 is connected to the input ports IN and the drain of M15, and the source of M15 is connected to the output port OUT.
A PMOS transistor M18 and an NMOS transistor M19 are used to generate the inverted clock voltage CLKR: the source of M18 is connected to the power voltage VDD, the gate of M18, the gate of M19 is connected to the timing switch CLK, the source of M19 is connected to ground, the drain of M18 and the drain of M19 are connected to generate the reverse clock voltage CLKR.
Likewise, one PMOS transistor M20 and one NMOS transistor M21 are used to generate the inverted clock voltage CLKB: the source of M20 is connected to the power voltage VDD, the gate of M20, the gate of M21 is connected to the timing switch CLK, the source of M21 is connected to ground, the drain of M20 and the drain of M21 are connected to generate the reverse clock voltage CLKB.
The working mode of the high-speed bootstrap switch is divided into two working states: a hold state and a sample state.
In a holding state, the timing switch CLK is turned off, the CLKR and CLKRB are at high level, and the M6 and M7 gates are at high level, that is, the lower plates of the C3 and C4 are at low voltage; meanwhile, the C1 bottom plate is directly controlled by CLKR to be high level, because the C2 bottom plate is low level through the inverter, the C1 top plate and the M1 source are high level with the M2, M3 and M4 gates, M2, M3 and M4 are conducted, VDD flows to the C2, C3 and C4 capacitor top plates through M2, M3 and M4 to charge C2, C3 and C4 to VDD; m1, M2, C1, and C2 constitute a clock multiplication circuit, so that M3, M4 charge C3, C4;
the CLK controls M8 to be turned on and M9 to be turned off, namely the gate is high level to control M10 to be turned off; VDD is connected with a grid of an M12 to enable the grid to be normally conducted, CLKRB is connected with a grid of an M13 to enable an M13 to be conducted, a source of the M13 is grounded, M11, M14 and M15 are controlled to be turned off through M12, and the M10 and M14 isolate a switch from C4; m15 is turned off as a switch tube, the input signal IN can not pass through M15, and the output is kept unchanged.
In a sampling state, CLK is converted into high level, CLKR and CLKRB are converted into low level, M6 and M7 grid low level are switched off, C1 bottom plate low voltage and C2 bottom plate high voltage; since C2 is charged to VDD, the upper plate of C2, namely the grid of M1, can reach 2 times VDD, M1 is conducted, and VDD charges C1;
m5 gate voltage is 2 times VDD, M5 is turned on to enable C3, C4 and M5 to form a charge pump structure, meanwhile CLKRB is in a low level to enable M13 to be turned off, and CLK is in a high level to control M8 to be turned off and M9 and M10 to be turned on, namely M11, M14 and M15 are turned on. The input signal VIN flows to the source output OUT through the M15 switch tube and simultaneously flows to the C3 through the M14, so the charge pump structures of C3, M5 and C4 pump the voltage of the upper plate of the C4 to twice VDD + VIN (VIN is the input voltage at IN), that is, the difference between the voltages of the gate and the source on the switch tube M15 is twice VDD, and thus the whole system follows the input change to obtain the output with high linearity.
Example (b):
the invention uses Cadence software to carry out circuit design and simulation, adopts a TSMC 0.18 μm CMOS process, and the size of a basic MOS tube adopted in the circuit is consistent with that of the existing bootstrap switch. The schematic diagram of the design circuit is shown in fig. 1, and the circuit comprises a clock multiplication circuit, a charge pump circuit and a switch circuit module. In the existing bootstrap switch circuit, the gate-source voltage difference of the switch tube is single-time VDD.
The main parameters of the invention are set as follows:
the power supply voltage VDD is 1.8V, the sampling frequency is 100M, the input voltage is from 0.2 to 0.8V, and the load capacitance is 1pF, so that the circuit operation in the low-voltage input range at high speed is tested.
(1) Bootstrapping switch function emulation
The simulation results are shown in fig. 2: the signal output OUT is output along with the input signal IN when the sampling phase CLK is high, and is kept unchanged when the holding phase CLK is low, so that the function of a bootstrap switch is realized.
(2) Grid source voltage difference of switch tube of bootstrap switch
The higher grid-source extreme pressure difference of the switching tube can give a higher redundancy value to the switching tube, and the working effectiveness under the high sampling rate is ensured. As shown in fig. 3, the gate-source voltage difference of the switching tube of the circuit design provided by the invention is 3.41V, and the gate-source voltage difference of the existing bootstrap switch is 1.76V, which is increased by 1.65V.
(3) Switch tube on-resistance of bootstrap switch
As shown in fig. 1, the on-resistance of the switching tube of the bootstrap switch plays an important role in the linearity of the circuit, and the on-resistance of the switching tube M15 is:
where μ is the carrier mobility, CoxIs the capacitance of the gate oxide layer,is the width-to-length ratio of the switch tube, VGSIs the difference between the gate and source voltages, VTHIs the threshold voltage. The present invention is directed to increasing VGSDecrease the on-resistance Ron. Under the condition of the working parameter and the load resistor 1k omega, the on-resistance R of the bootstrap switch designed by the invention periodically changes along with the input voltage when the CLK is highonThe fluctuation range of the resistance is 266 omega to 291 omega, and the existing bootstrap switch is provided with a conducting resistor RonThe resistance fluctuation range is 310 Ω to 379 Ω. It can be seen that the bootstrap switch of the present invention has an on-resistance RonThe difference is 25 omega, which is about 36.2% of the existing design, and the linearity of the whole circuit is improved and the performance of the bootstrap switch is improved under the condition of lower on-resistance.
(4) Dynamic performance of bootstrap switch
By performing spectrum analysis on the simulation output result, under the simulation environment of 1024 sampling points and 5 harmonic numbers, the simulation result of the invention is shown in fig. 5, and the simulation result of the existing bootstrap switch is shown in fig. 6. The effective digit ENOB of the prior art is 13.09 bits, the effective digit of the output OUT of the invention is 14.52 bits, and 1.43 bits are improved. Meanwhile, dynamic performance parameters such as signal-to-noise ratio (SNR) and SFDR are improved. The performance of the bootstrap switch circuit is superior to that of the existing bootstrap switch circuit under the requirements of high speed and high precision.
The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (7)
1. A high speed bootstrapped switch having a low on-resistance, comprising a clock multiplication circuit, a charge pump circuit, and a switching circuit, wherein:
the clock multiplication circuit comprises NMOS transistors M1 and M2, capacitors C1 and C2 and an inverter; the drain of M1 and the drain of M2 are connected with a power supply voltage VDD, the gate of M1 is connected with the source of M2 and the upper plate of a capacitor C2, the gate of M2 is connected with the source of M1 and the upper plate of a capacitor C1, the lower plate of C1 is connected with a reverse clock voltage CLKR, and the CLKR passes through the inverter and then is connected with the lower plate of C2;
the charge pump circuit comprises NMOS transistors M3, M4, M5, M6 and M7, and capacitors C3 and C4; the drain of M3 and the drain of M4 are connected with a power supply voltage VDD, the gate of M3 and the gate of M4 are connected with the source of M1, the source of M3 is connected with the upper plate of C3 and the drain of M5, and the source of M4 is connected with the upper plate of C4; the grid of M5 is connected with the upper electrode plate of M2, the source of M5 is connected with the lower electrode plate of C4 and the drain of M7, the lower electrode plate of C3 is connected with the drain of M6, the grid of M6 and the grid of M7 are connected with a reverse clock voltage CLKR, the source of M6 and the source grounding terminal VSS of M7;
the switch circuit comprises PMOS transistors M8 and M10, NMOS transistors M9, M11, M12, M13, M14 and M15, wherein the grid electrode of M8 and the grid electrode of M9 are connected with a timing switch CLK, the source electrode of M8 and the grid electrode of M12 are connected with a power supply voltage VDD, the drain electrode of M8 is connected with the drain electrode of M9, the drain electrode of M11 and the grid electrode of M10, the source electrode of M9 is connected with the lower pole plate of C3, the source electrode of M11 and the source electrode of M14; the source of M10 is connected with the upper electrode plate of C4, the drain of M10 is connected with the grid of M11, the drain of M12, the grid of M14 and the grid of M15, the source of M12 is connected with the drain of M13, the grid of M13 is connected with the reverse clock voltage CLKRB, and the source of M13 is connected with the ground terminal VSS; the drain of M14 is connected to the input ports IN and the drain of M15, and the source of M15 is connected to the output port OUT.
2. The high-speed bootstrapped switch with low on-resistance of claim 1, wherein a PMOS transistor M18 and an NMOS transistor M19 are used to generate the inverted clock voltage CLKR: the source of M18 is connected to the power voltage VDD, the gate of M18, the gate of M19 is connected to the timing switch CLK, the source of M19 is connected to ground, the drain of M18 and the drain of M19 are connected to generate the reverse clock voltage CLKR.
3. The high-speed bootstrapped switch with low on-resistance of claim 1, wherein one PMOS transistor M20 and one NMOS transistor M21 are used to generate the inverted clock voltage CLKRB: the source of M20 is connected to the power voltage VDD, the gate of M20, the gate of M21 is connected to the timing switch CLK, the source of M21 is connected to ground, the drain of M20 and the drain of M21 are connected to generate the reverse clock voltage CLKRB.
4. The high speed bootstrap switch with low on-resistance as recited in claim 1, characterized in that when said high speed bootstrap switch is operated in hold state:
the time sequence switch CLK is turned off, the CLKR and the CLKRB are in high level, the M6 and the M7 grid electrodes are in high level conduction, and the C3 and the C4 lower plate electrodes are in low voltage; meanwhile, the C1 lower electrode plate is in a high level directly controlled by CLKR, the C1 upper electrode plate and the M1 source electrode are in a high level with the M2, M3 and M4 grid electrodes, the M2, M3 and M4 are conducted, VDD flows to the C2, C3 and C4 capacitor upper electrode plates through M2, M3 and M4 to charge the C2, C3 and C4 to VDD; m1, M2, C1, and C2 constitute a clock multiplication circuit, so that M3, M4 charge C3, C4;
the CLK controls M8 to be turned on and M9 to be turned off, namely the gate is high level to control M10 to be turned off; VDD is connected with a grid of an M12 to enable the grid to be normally conducted, CLKRB is connected with a grid of an M13 to enable an M13 to be conducted, a source of the M13 is grounded, M11, M14 and M15 are controlled to be turned off through M12, and the M10 and M14 isolate a switch from C4; m15 is turned off as a switch tube, the input signal IN can not pass through M15, and the output is kept unchanged.
5. The high-speed bootstrap switch with low on-resistance as recited in claim 1, characterized in that when said high-speed bootstrap switch is operated in the sampling state:
the CLK is converted into a high level, the CLKR and the CLKRB are converted into a low level, the grid electrodes of M6 and M7 are turned off at a low level, the lower plate of C1 is at a low voltage, and the lower plate of C2 is at a high voltage; the upper polar plate of the C2, namely the grid of the M1 reaches 2 times of VDD, the M1 is conducted, and the VDD charges the C1;
m5 gate voltage is 2 times VDD, M5 is conducted to enable C3, C4 and M5 to form a charge pump structure, meanwhile CLKRB is low level to enable M13 to be turned off, CLK high level controls M8 to be turned off, M9 and M10 to be conducted, namely M11, M14 and M15 are conducted; the input signal VIN flows to the source output OUT through the M15 switch tube, and simultaneously flows to the C3 through the M14, the charge pump structures of the C3, the M5 and the C4 pump the voltage of the upper plate of the C4 to double VDD + VIN, the voltage difference of the upper grid and the source of the switch tube M15 is double VDD, and therefore the whole high-speed bootstrap switch follows the input change to obtain the output with high linearity.
6. The high-speed bootstrapped switch with low on-resistance of claim 1, wherein the power voltage VDD is 1.8V.
7. A high-speed low-voltage A/D converter, characterized in that a high-speed bootstrap switch with low on-resistance according to any of claims 1 to 6 is used in the converter.
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CN101171558A (en) * | 2005-03-08 | 2008-04-30 | 德克萨斯仪器股份有限公司 | Bootstrapping circuit capable of sampling inputs beyond supply voltage |
KR20140086909A (en) * | 2012-12-28 | 2014-07-08 | 주식회사 실리콘웍스 | Charge pump apparatus |
CN103532534A (en) * | 2013-09-17 | 2014-01-22 | 电子科技大学 | Grid voltage bootstrapping switch circuit |
CN107612317A (en) * | 2017-09-26 | 2018-01-19 | 上海华虹宏力半导体制造有限公司 | A kind of charge pump circuit |
CN110635791A (en) * | 2019-09-06 | 2019-12-31 | 重庆邮电大学 | Grid voltage bootstrap sampling switch circuit adopting mirror image structure |
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