CN115987267A - High-linearity sampling switch circuit - Google Patents
High-linearity sampling switch circuit Download PDFInfo
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- CN115987267A CN115987267A CN202310123629.4A CN202310123629A CN115987267A CN 115987267 A CN115987267 A CN 115987267A CN 202310123629 A CN202310123629 A CN 202310123629A CN 115987267 A CN115987267 A CN 115987267A
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Abstract
A high-linearity sampling switch circuit comprises a charge discharging module, a charge pump module, a grid voltage bootstrap module, a sampling switch module, a complementary switch module and a sampling isolation module. In the holding stage, the charge pump module pre-charges the gate voltage bootstrap module circuit, and the charge discharge module turns off the sampling switch module. In the sampling stage, a bootstrap switch loop formed by the grid voltage bootstrap module and the sampling switch is conducted, and the grid voltage of the switch tube is raised to 2 times of the sum of the power supply voltage and the input signal, so that the conduction impedance is greatly reduced. A voltage follower is adopted to isolate a sampling switch from a capacitor plate, wherein the substrate of the sampling switch adopts a substrate bias elimination technology, so that the parasitic capacitance is effectively reduced compared with the traditional grid voltage bootstrap switch circuit, and the body effect of the switch tube is further optimized through the substrate bias elimination technology. The sampling isolation module isolates the influence of the change of the polar plate voltage on the sampling tube when the capacitor array of the digital-to-analog converter is switched through the voltage follower, and the linearity of the whole sampling switch circuit is improved.
Description
Technical Field
The invention relates to the technical field of analog integrated circuits, in particular to a high-linearity sampling switch circuit.
Background
With the rapid development of analog integrated circuits and digital signal processing technologies, analog-to-digital converters (ADCs) are further optimized as bridges for connecting the digital world and the analog world. The function of the analog-to-digital converter is to realize the function from an analog signal to a digital signal through sampling, quantization and coding.
The sampling switch is a critical module of the ADC, which has a great influence on the accuracy of the ADC, so the design of the sampling switch circuit is particularly critical. The ADC on the market has higher and higher precision, which puts high demands on the linearity of the sampling switch circuit. The sampling switch circuit is used for sampling an input signal at a high level and holding the input signal at a low level, and the duty ratio of a sampling clock is generally set to be 1:2. although the conventional single MOS switch tube has a simple structure, its on-resistance is easily changed by an input signal, and its on-resistance is affected to generate a nonlinear change. The bootstrap switching technique is proposed to solve the problem of on-resistance variation.
A conventional bootstrap switch model is shown in fig. 1. In the holding stage, S3 and S4 are closed, so that the upper electrode of the bootstrap capacitor is connected to the power voltage terminal, the ground terminal of the lower electrode is precharged to VDD, and S5 is closed at the same time, so that the sampling switch tube Ms is closed. In the sampling stage, S1 and S2 are closed to form a gate voltage bootstrap loop, and S5 is turned off at the same time, so that the gate voltage of the sampling switch tube is constant to VDD + VIN, and the gate-source voltage of the sampling switch tube Ms is kept at VDD. In the retention stage, CLKs is at low level, CLKsb is at high level, M2 tube is on, M6 tube is on, M1 and Mswitch are pulled to low level, switch tube is off, M3 tube is on, C1 is precharged to VDD. In the sampling stage, CLKs is at a high level, CLKsb is at a low level, the M2 tube is turned off, the M6 tube is turned off, the M4 tube is turned on, the M1 and Mswitch tubes are turned on, and VGS voltage of the switching tube is clamped at about VDD.
The expression of the sampling switch tube Ms is as follows:
in the formula,. Mu. n For carrier mobility, C ox Is a capacitance of a gate oxide layer,
is the width-to-length ratio, V, of the sampling switch tube Ms th Is the threshold voltage of the sampling switch tube Ms. The gate-source voltage of the switching tube is constant to be VDD in the sampling stage, but the threshold voltage change caused by the switching tube body effect is ignored, the voltage value of VG cannot achieve the expected effect under the condition that the voltage of a parasitic capacitor and a bootstrap capacitor in the sampling circuit is divided, and the linearity of the sampling switching tube is also influenced by the change of the voltage of a capacitor plate caused by the switching of a capacitor array of a digital-to-analog converter (DAC).
Disclosure of Invention
The invention aims to provide a high-linearity sampling switch circuit, which is used for solving the problems in the prior art, reducing parasitic capacitance in the circuit, increasing the grid voltage of a sampling tube to reduce on-resistance, and simultaneously reducing the influence of the substrate bias effect of the sampling switch tube and the change of the polar plate voltage on the sampling switch tube during the switching of a DAC capacitor array, thereby improving the linearity of the whole sampling switch circuit.
In order to achieve the above object, the present invention provides a high linearity sampling switch circuit, which includes a charge discharging module, a charge pump module, a gate voltage bootstrapping module, a sampling switch module, a complementary switch module, and a sampling isolation module. The sampling isolation module is used for isolating influence of voltage change of a DAC capacitor array plate on the sampling switch module, the charge pump module is used for conducting a grid voltage bootstrap module M4 deeply, grid voltage of a sampling tube is increased to 2VDD + VIN in a sampling stage, the charge discharge module is used for resetting the sampling circuit, and the grid voltage bootstrap module is used for enabling grid source voltage of the sampling switch tube to be constant. The complementary switch module can reduce the on-resistance when the frequency of the input signal is increased, and improve the linearity of sampling.
Further, the charge discharging module includes: an eighth NMOS transistor M8, a ninth PMOS transistor M9 and a tenth NMOS transistor M10;
the source electrode of the eighth NMOS transistor M8 is connected with the drain electrode of the seventh PMOS transistor M7, the gate electrode of the eighth NMOS transistor M8 is connected with the source electrode of the ninth PMOS transistor M9, and the drain electrode of the eighth NMOS transistor M8 is connected with the source electrode of the tenth NMOS transistor M10; the grid electrode of the ninth PMOS tube M9 and the grid electrode of the tenth NMOS tube M10 are connected with a clock control signal CLKSB, the drain electrode is connected with the drain electrode of the eighth NMOS tube M8 and the source electrode of the tenth NMOS tube M10, and the source electrode is connected with a power voltage end; and the drain electrode of the tenth NMOS transistor M10 is grounded, and the source electrode is connected to the drain electrode of the ninth PMOS transistor M9 and the drain electrode of the eighth NMOS transistor M8, respectively.
Further, the charge pump module includes: a second NMOS transistor M2, a third NMOS transistor M3, a seventeenth NMOS transistor M17, an eighteenth PMOS transistor M18, a first energy storage capacitor C1, and a second energy storage capacitor C2;
the grid electrode of the second NMOS tube M2 is connected with the source electrode of the third NMOS tube M3 and the upper electrode of the second energy storage capacitor C2, the drain electrode is connected with a power voltage end, and the source electrode is respectively connected with the upper electrode of the first storage capacitor C1 and the grid electrode of the third NMOS tube M3; the drain electrode of the third NMOS tube M3 is connected with a power voltage end, and the grid electrode of the third NMOS tube M3 is connected with the source electrode of the second NMOS tube M2, the source electrode of the seventeenth NMOS tube M17 and the drain electrode of the eighteenth PMOS tube M18; the source electrode of the seventeenth NMOS tube M17 is connected with the grid electrode of the third NMOS tube M3 and the drain electrode of the eighteenth PMOS tube M18, the drain electrode is connected with the source electrode of the eighteenth PMOS tube M18 and the grid electrode of the fourth NMOS tube M4, and the grid electrode is connected with a clock control signal CLKSB; the drain electrode of the eighteenth PMOS tube M18 is connected with the source electrode of the seventeenth NMOS tube M17 and the grid electrode of the third NMOS tube M3, the source electrode is connected with the drain electrode of the seventeenth NMOS tube M17 and the grid electrode of the fourth NMOS tube M4, and the grid electrode is connected with a clock control signal CLKS; (the upper electrode of the first energy storage capacitor C1, the source electrode is connected with the grid electrode of the second NMOS tube M2 and the upper electrode of the second storage capacitor C2) the upper electrode of the first storage capacitor is connected with the source electrode of the second NMOS tube M2, and the lower electrode is connected with a clock control signal CLKSB; the upper electrode of the second energy storage capacitor is connected with the source electrode of the third NMOS tube M3 and the grid electrode of the second NMOS tube M2, and the lower electrode is connected with a clock control signal CLKS.
Further, the gate voltage bootstrap module includes: a fourth NMOS transistor M4, a thirteenth NMOS transistor M13, a fifth PMOS transistor M5, a sixth NMOS transistor M6, a seventh PMOS transistor M7, a transmission gate composed of an eleventh PMOS transistor M11 and a twelfth NMOS transistor M12, and a bootstrap capacitor Ch;
the grid electrode of the fourth NMOS tube M4 is in short circuit with the drain electrode, the grid electrode is connected with the drain electrode of the seventeenth NMOS tube M17 and the source electrode of the eighteenth PMOS tube M18, the drain electrode is connected with the drain electrode of the seventeenth NMOS tube M17 and the source electrode of the eighteenth PMOS tube M18, and the source electrode is connected with the upper electrode of the bootstrap capacitor Ch and the source electrode of the seventh PMOS tube M7; the upper electrode of the bootstrap capacitor Ch is connected with the source electrode of the fourth NMOS tube M4, and the lower electrode is connected with the drain electrode of the thirteenth NMOS tube M13; a source electrode of the thirteenth NMOS transistor M13 is grounded, a gate electrode thereof is connected to the clock control signal CLKSB, and a drain electrode thereof is connected to the lower electrode of the bootstrap capacitor Ch; the grid electrodes of a fifth PMOS tube M5 and a sixth NMOS tube M6 are connected with a clock control signal CLKS, the source electrode of the fifth PMOS tube M5 is connected with a power voltage end, and the drain electrode is connected with the drain electrode of the sixth NMOS tube M6, the grid electrode of a seventh PMOS tube M7, the source electrode of an eleventh PMOS tube M11 and the drain electrode of a twelfth NMOS tube M12; the source electrode of the sixth NMOS transistor M6 is grounded, and the drain electrode is connected with the drain electrode of the fifth PMOS transistor M5, the gate electrode of the seventh PMOS transistor M7, the source electrode of the eleventh PMOS transistor M11 and the drain electrode of the twelfth NMOS transistor M12; the source electrode of the seventh PMOS tube M7 is connected with the source electrode of the fourth NMOS tube M4 and the upper electrode of the bootstrap capacitor Ch, the grid electrode of the seventh PMOS tube is connected with the drain electrode of the fifth PMOS tube M5 and the drain electrode of the sixth NMOS tube M6, the drain electrode of the seventh PMOS tube M7 is connected with the source electrode of the eighth NMOS tube M8, and the first NMOS tube M1 is connected with the grid electrode of the sampling switch tube Ms and the grid electrode of the twelfth NMOS tube M12; the grid electrode of the eleventh PMOS tube M11 is connected with a clock control signal CLKSB, the drain electrode of the eleventh PMOS tube M11 is connected with the source electrode of the twelfth NMOS tube M12, and the source electrode of the eleventh PMOS tube M11 is connected with the drain electrode of the twelfth NMOS tube M12; the drain electrode of the twelfth NMOS tube M12 is connected with the source electrode of the eleventh PMOS tube M11, the source electrode is connected with the drain electrode of the eleventh PMOS tube M11, and the grid electrode is connected with the grid electrode of the first NMOS tube M1, the grid electrode of the sampling switch tube Ms and the source electrode of the eighth NMOS tube M8.
Further, the sampling isolation module comprises: a voltage follower, a load capacitance CL; the positive phase end of the voltage follower is connected with the drain electrode of the sampling switch tube Ms and the source electrode of the sixteenth PMOS tube M16, the negative phase end of the voltage follower is connected with the output end of the voltage follower and the upper electrode of the load capacitor CL, and the output end of the voltage follower is connected with the upper electrode of the load capacitor CL and the negative phase end of the voltage follower.
Further, the sampling switch module includes: a first NMOS transistor M1, a fourteenth NMOS transistor M14, a fifteenth NMOS transistor M15, and a complementary switch module (Ms, M16); the source electrode of the first NMOS tube is connected with the drain electrode of an eleventh PMOS tube M11 and the source electrode of a twelfth NMOS tube M12, the grid electrode of the first NMOS tube is connected with the grid electrode of the twelfth NMOS tube M12, the source electrode of an eighth NMOS tube M8 and the grid electrode of a sampling switch tube Ms, and the drain electrode of the first NMOS tube is connected with the source electrode of the sampling switch tube Ms and the drain electrode of a sixteenth PMOS tube M16; the grid electrode of the fourteenth NMOS tube M14 is connected with a power voltage end, the drain electrode of the fourteenth NMOS tube M14 is respectively connected with the substrate of the first NMOS tube M1 and the sampling switch tube Ms, and the source electrode of the fourteenth NMOS tube M15 is connected with the drain electrode of the fifteenth NMOS tube M15; the gate of the fifteenth NMOS transistor M15 is connected to the clock control signal CLKSB, the source thereof is grounded, and the drain thereof is connected to the source of the fourteenth NMOS transistor M14.
Further, the complementary switch module comprises: a sampling switch tube Ms and a sixteenth PMOS tube M16; the grid electrode of the sampling switch tube Ms is connected with the grid electrode of the first NMOS tube M1, the grid electrode of the twelfth NMOS tube M12 and the source electrode of the eighth NMOS tube M8, the source electrode is connected with the drain electrode of the first NMOS tube M1, and the drain electrode is connected with the source electrode of the sixteenth PMOS tube M16 and the positive phase end of the voltage follower; the drain electrode of the sixteenth PMOS tube M16 is connected with the source electrode of the sampling switch tube Ms and the drain electrode of the first NMOS tube M1, the grid electrode is connected with a clock control signal CLKSB, and the source electrode is connected with the drain electrode of the sampling switch tube Ms and the positive phase end of the voltage follower;
the invention has the following beneficial effects:
(1) In the sampling stage, a bootstrap switch loop formed by the grid voltage bootstrap module and the sampling switch is conducted, and the grid voltage of the switch tube is raised to 2 times of the sum of the power supply voltage and the input signal, so that the conducting impedance is greatly reduced. (2) The sampling switch is isolated from the capacitor plate by the voltage follower, the substrate of the sampling switch adopts a substrate bias elimination technology, parasitic capacitance is effectively reduced compared with a traditional grid voltage bootstrap switch circuit, and the body effect of the switch tube is further optimized by the substrate bias elimination technology. (3) By using the sampling isolation module, the influence of the change of the plate voltage on the sampling tube when the DAC capacitor array is switched is isolated through the voltage follower, so that the linearity of the whole sampling switch circuit is greatly improved.
Drawings
FIG. 1 is a circuit diagram of a bootstrap switch in the background art of the present invention.
Fig. 2 is a circuit diagram of a conventional gate voltage bootstrapped switch in the background art of the invention.
Fig. 3 is a circuit diagram of a high linearity sampling switch according to an embodiment of the present invention.
Detailed Description
The technical scheme of the invention is further explained in detail by combining the drawings in the specification.
As shown in fig. 3, a high linearity sampling switch circuit includes a charge discharging module 10, a charge pump module 20, a gate voltage bootstrap module 30, a sampling switch module 40, a complementary switch module 401, and a sampling isolation module 50.
The charge discharging module 10 is composed of an eighth NMOS transistor M8, a ninth PMOS transistor M9, and a tenth NMOS transistor M10; the grid electrode of the eighth NMOS tube M8 and the source electrode of the ninth PMOS tube M9 are connected with a power voltage end in common, and the source electrodes are respectively connected with the drain electrode of the seventh PMOS tube M7, the grid electrode of the twelfth NMOS tube M12, the grid electrode of the first NMOS tube M1 and the grid electrode of the sampling switch tube Ms; the grid electrode of the ninth PMOS tube M9 and the grid electrode of the tenth NMOS tube are connected with a clock control signal CLKSB in common, and the drain electrode of the ninth PMOS tube M9 and the grid electrode of the tenth NMOS tube M10 are connected with the drain electrode of the eighth NMOS tube M8 and the source electrode of the tenth NMOS tube M10; the drain of the tenth NMOS transistor M10 is grounded, the gate is connected to the clock control signal CLKSB, and the source is connected to the drain of the eighth NMOS transistor M8 and the drain of the ninth PMOS transistor M9.
In the conventional structure, the node a shown in fig. 3 is pulled to ground during the holding phase a, and is turned off during the sampling phase M6, and the parasitic capacitance exists at the point a, so that the charge is separated by M5. In the existing structure, in the sampling stage, the M10 gate is led in a low level to turn off the M10 transistor, and the M9 gate is led in a low level M9 transistor to turn on, so that the voltage of the node a can be raised to the power supply voltage, and the influence of the parasitic capacitance at the point a can be reduced.
The charge pump module 20 shown in fig. 3 is composed of a second NMOS transistor M2, a third NMOS transistor M3, a seventeenth NMOS transistor M17, an eighteenth PMOS transistor M18, a first energy-storage capacitor C1, and a second energy-storage capacitor C2, wherein a drain of the second NMOS transistor M2 is connected to a power voltage terminal, a gate is connected to a source of the third NMOS transistor M3 and an upper electrode of the second energy-storage capacitor C2, and a source is connected to a gate of the third NMOS transistor M3 and an upper electrode of the first energy-storage capacitor C1; the grid electrode of the third NMOS tube M3 is connected with the source electrode of the second NMOS tube M2, the source electrode of the seventeenth NMOS tube M17, the drain electrode of the eighteenth PMOS tube M18 and the upper electrode of the first energy storage capacitor C1, and the source electrode is connected with the grid electrode of the second NMOS tube M2, the upper electrode of the second energy storage capacitor C2 and the drain electrode are connected with a power voltage end; the source electrode of the seventeenth NMOS tube M17 is connected with the drain electrode of the eighteenth PMOS tube M18 and the grid electrode of the third NMOS tube M3, and the drain electrode is connected with the source electrode of the eighteenth PMOS tube M18 and the grid electrode of the fourth NMOS tube M4; the grid is connected with a clock control signal CLKSB; the drain electrode of the eighteenth PMOS tube M18 is connected with the source electrode of the seventeenth NMOS tube M17 and the grid electrode of the third NMOS tube M3, the source electrode is connected with the drain electrode of the seventeenth NMOS tube M17 and the grid electrode of the fourth NMOS tube M4, the grid electrode is connected with a clock control signal CLKS, the upper electrode of the first energy storage capacitor C1 is connected with the source electrode of the second NMOS tube M2, the lower electrode is connected with CLKSB, the upper electrode of the second energy storage capacitor C2 is connected with the source electrode of the third NMOS tube M3, and the lower electrode is connected with CLKS. The M13 tube is conducted, and a charge pump loop formed by the M2, the M3, the M17, the M18, the C1 and the C2 enables voltage to be multiplied, the M4 grid voltage of the grid voltage bootstrap module is raised to 2VDD, deep conduction is achieved, and the charging function is completed. In the sampling stage, the M13 tube is switched off, an input signal is connected to the lower electrode of the bootstrap capacitor through the sampling switch module, the upper electrode of the bootstrap capacitor is lifted by a voltage value of VIN again according to the charge conservation principle, and sampling is carried out through the sampling switch.
The gate voltage bootstrap module 30 is composed of a fourth NMOS transistor M4, a thirteenth NMOS transistor M13, a bootstrap capacitor Ch, a fifth PMOS transistor M5, a sixth NMOS transistor M6, a seventh PMOS transistor M7, and a transmission gate composed of an eleventh PMOS transistor M11 and a twelfth NMOS transistor M12; the grid electrode of the fourth NMOS tube M4 is in short circuit with the drain electrode, the grid electrode is connected with the drain electrode of the seventeenth NMOS tube M17 and the source electrode of the eighteenth PMOS tube M18, the drain electrode is connected with the drain electrode of the seventeenth NMOS tube M17 and the source electrode of the eighteenth PMOS tube M18, and the source electrode is connected with the source electrode of the seventh PMOS tube M7 and the upper electrode of the bootstrap capacitor; the gate of the thirteenth NMOS transistor M13 is connected to the clock control signal CLKSB, the source terminal, and the drain is connected to the lower electrode of the bootstrap capacitor, the drain of the eleventh PMOS transistor M11, and the source of the twelfth NMOS transistor M12; the grid electrodes of the fifth PMOS tube M5 and the sixth NMOS tube M6 are connected with a clock control signal CLKS in common, the source electrode of the fifth PMOS tube M5 is connected with a power voltage end, the drain electrode is connected with the drain electrode of the sixth NMOS tube M6, the grid electrode of the seventh PMOS tube M7 and the source electrode grounding end of the sixth NMOS tube M6; the source electrode of the seventh PMOS tube M7 is connected with the source electrode of the fourth NMOS tube M4 and the upper electrode of the bootstrap capacitor Ch, the grid electrode is connected with the drain electrodes of the fifth PMOS tube M5 and the sixth NMOS tube M6, the source electrode of the eleventh PMOS tube M11 and the drain electrode of the twelfth NMOS tube M12, and the drain electrode is connected with the source electrode of the eighth NMOS tube M8; the grid electrode of the eleventh PMOS tube M11 is connected with a clock control signal CLKSB, the drain electrode of the eleventh PMOS tube M11 is connected with the source electrode of the twelfth NMOS tube M12, and the source electrode of the eleventh PMOS tube M11 is connected with the drain electrode of the twelfth NMOS tube M12; the source electrode of the twelfth NMOS tube M12 is connected with the drain electrode of the eleventh NMOS tube M11, and the grid electrode is connected with the grid electrode of the first NMOS tube M1, the grid electrode of the sampling switch tube Ms and the source electrode of the eighth NMOS tube M8.
The gate and the drain of the fourth NMOS transistor M4 are short-circuited, so that the voltage of the upper electrode of the bootstrap capacitor can be raised to 2vdd + vin in the sampling stage, and the source of the sixth NMOS transistor M6 is grounded and is not directly connected with the first NMOS transistor M1, thereby further reducing the parasitic capacitance influence caused by the sixth NMOS transistor M6. The complementary switch, consisting of M11 and M12, may be reduced to some extent as the frequency of the input signal increases.
The sampling switch module 40 includes: the circuit comprises a first NMOS tube M1, a fourteenth NMOS tube M14, a fifteenth NMOS tube M15 and a complementary switch consisting of a sampling tube Ms and a sixteenth PMOS tube M16; the grid electrode of the first NMOS tube M1 is connected with the grid electrode of the twelfth NMOS tube M12, the grid electrode of the sampling switch tube Ms and the source electrode of the eighth NMOS tube M8, the source electrode is connected with the drain electrode of the eleventh PMOS tube M11 and the source electrode of the twelfth NMOS tube M12, and the drain electrode is connected with the source electrode of the sampling switch tube Ms and the drain electrode of the sixteenth PMOS tube M16; the grid electrode of the fourteenth NMOS tube M14 is connected with a power voltage end, the source electrode is connected with the drain electrode of the fifteenth NMOS tube, and the drain electrode is connected with the substrate of the first NMOS tube and the sampling switch tube; the gate of the fifteenth NMOS transistor M15 is connected to the clock control signal CLKSB, and the source is connected to the ground.
The complementary switch module 401 is composed of a sampling switch tube Ms and a sixteenth PMOS tube M16, the gate of the sampling switch tube is connected with the gate of the first NMOS tube M1 and the gate of the twelfth NMOS tube M12, the source is connected with the drain of the first NMOS tube M1 and the drain of the sixteenth PMOS tube M16, respectively, and the drain is connected with the positive phase end of the voltage follower; the gate of the sixteenth PMOS transistor M16 is connected to the clock control signal CLKSB, and the drain is connected to the source of the sampling switch transistor Ms and the drain of the first NMOS transistor M1.
The M14 transistor and the M15 transistor are used for eliminating the body effect of the M1 transistor and the Ms transistor, when the CLKSB is at a high level, the sampling switch circuit holds, the grid electrode of the M15 transistor is led in the high level, and the substrates of the M1 transistor and the Ms transistor are pulled to the ground. When the CLKSB is at a low level, the sampling switch circuit starts sampling, the M15 transistor is turned off, the M1 transistor and the Ms transistor are turned on, and the substrates of the M1 transistor and the Ms transistor are both the input signal VIN. The complementary switch composed of the Ms tube and the M16 tube can be reduced to a certain extent when the frequency of the input signal is increased, and the on-resistance expression of the complementary switch is as follows:
in the formula,. Mu. n For the carrier mobility of Ms tubes, μ p Carrier mobility for M16 tubes, C ox Is a capacitance of a gate oxide layer,
is the width-length ratio of the Ms tube, is greater than or equal to>
The width-to-length ratio of M16 transistor, VDD, VIN, VTHN, VTHP, and VTHP
When the input signal is increased, compared with the traditional structure, the on-resistance is reduced to a certain extent, and the linearity of the sampling circuit is improved.
The sampling isolation module 50 is composed of a voltage follower and a load capacitor CL, wherein the positive phase end of the voltage follower is connected with the drain electrode of the sampling switch tube Ms and the source electrode of the sixteenth PMOS tube M16, the reverse phase end of the voltage follower is connected with the output end of the voltage follower and the upper electrode of the load capacitor CL, and the output end of the voltage follower is connected with the input end of the voltage follower and the upper electrode of the load capacitor CL; the upper electrode of the load capacitor CL is connected with the output end of the voltage follower and the grounding end of the lower electrode; the voltage follower is mainly responsible for isolating the influence of the voltage changed by the polar plate on the sampling tube Ms when the DAC capacitor array is switched, and the linearity of the sampling circuit is further improved.
In the holding stage, CLKS is low level, CLKSB is high level, the M13 tube, the M17 tube and the M18 tube are complementary switches are switched on, the M7 tube, the M11 tube and the M12 tube are switched off, the charge pump module multiplies the grid voltage of the M4 tube to 2VDD, the M4 tube is deeply switched on, the M10 tube is switched on, and the grid voltages of the M1 tube and the Ms tube are pulled to the ground to be switched off, so that the pre-charging is completed. In the sampling stage, CLKS is at a high level, CLKSB is at a low level, an M13 tube is turned off, a complementary switch consisting of an M17 tube and an M18 tube is turned off, a grid electrode of an M7 tube is input with a low level to enable the M7 tube to be conducted, a grid electrode of an M11 tube is input with a low level to enable the M11 tube to be conducted, an M8 tube and an M9 tube are conducted and pre-boost a point A to a power supply voltage, the influence of A electric parasitic capacitance is reduced, and the influence of M6 tube to the grounding is further reduced. The grid electrodes of the M1 tube and the Ms tube are high level at the moment, the sampling switch tube is conducted, the lower electrode of the bootstrap capacitor is VIN, the upper electrode is 2VDD + VIN according to charge conservation, the M14 tube and the M15 tube are added on the substrate of the sampling tube and the M1 tube for substrate offset elimination, and a voltage follower is added for isolating the influence of the change of the polar plate voltage on the sampling switch tube when the DAC capacitor array is switched, so that the linearity of the whole sampling switch circuit can be effectively improved. The complementary switch formed by the sampling tube and the M16 tube can reduce the on-resistance when the frequency of an input signal is increased, so that the linearity is improved.
The above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above embodiment, but equivalent modifications or changes made by those skilled in the art according to the present disclosure should be included in the scope of the present invention as set forth in the appended claims.
Claims (10)
1. A high linearity sampling switch circuit, characterized in that: the device comprises a charge discharging module, a charge pump module, a grid voltage bootstrap module, a sampling switch module, a complementary switch module and a sampling isolation module;
the grid voltage bootstrap module is respectively connected with the charge discharge module, the charge pump module and the sampling switch module, the complementary switch module is arranged in the sampling switch module, and the sampling switch module is connected with the sampling isolation module;
the sampling isolation module is used for isolating influence of voltage change of a DAC capacitor array plate on the sampling switch module, the charge pump module is deeply conducted on the grid voltage bootstrap module, and grid voltage of the sampling tube is increased to 2 times of sum of power voltage and an input signal, namely 2VDD + VIN in a sampling stage; the charge discharging module resets the sampling circuit, and the grid voltage bootstrap module enables the grid-source voltage of the sampling switch tube to be constant; the complementary switch module enables the on-resistance to be reduced when the frequency of the input signal is increased;
the sampling switch circuit is composed of a first NMOS tube M1, a second NMOS tube M2, a third NMOS tube M3, a fourth NMOS tube M4, a fifth PMOS tube M5, a sixth NMOS tube M6, a seventh PMOS tube M7, an eighth NMOS tube M8, a ninth PMOS tube M9, a tenth NMOS tube M10, an eleventh PMOS tube M11, a twelfth NMOS tube M12, a thirteenth NMOS tube M13, a fourteenth NMOS tube M14, a fifteenth NMOS tube M15, a sixteenth PMOS tube M16, a seventeenth NMOS tube M17, an eighteenth PMOS tube M18, a first energy storage capacitor C1, a second energy storage capacitor C2, a bootstrap capacitor Ch, a load capacitor CL, a sampling switch Ms and a voltage follower.
2. The high linearity sampling switch circuit of claim 1, wherein: in the sampling switch module, the source electrode of the first NMOS tube M1 is respectively connected with a twelfth NMOS tube M12 and an eleventh PMOS tube M11, the drain electrode of the first NMOS tube M1 is connected with the source electrode of the Ms switch tube, and the grid electrode of the first NMOS tube M1 is connected with the grid electrode of the twelfth NMOS tube M12, the source electrode of the eighth NMOS tube M8 and the grid electrode of the Ms switch tube; the source electrode of the Ms switch tube is connected with the drain electrode of the first NMOS tube M1 and the drain electrode of the sixteenth PMOS tube M16, the grid electrode of the Ms switch tube is respectively connected with the grid electrode of the first NMOS tube M1, the grid electrode of the twelfth NMOS tube M12 and the source electrode of the eighth NMOS tube M8, and the drain electrode of the Ms switch tube is connected with the positive phase end of the voltage follower and the source electrode of the sixteenth PMOS tube M16.
3. The high linearity sampling switch circuit of claim 2, wherein: in the sampling switch module, a source electrode of the fourteenth NMOS tube M14 is connected with a drain electrode of the fifteenth NMOS tube, the drain electrode of the fourteenth NMOS tube M14 is respectively connected with the substrates of M1 and Ms, and a grid electrode of the fourteenth NMOS tube M14 is connected with a voltage end;
the source electrode of the fifteenth NMOS tube M15 is grounded, the drain electrode of the fifteenth NMOS tube M15 is connected with the source electrode of the fourteenth NMOS tube M14, and the grid electrode of the fifteenth NMOS tube is connected with the clock control signal CLKSB; wherein, CLKSB and CLKS are inverted non-overlapping clocks.
4. A high linearity sampling switch circuit as claimed in claim 1, wherein: the charge discharge module comprises an eighth NMOS tube M8, a ninth PMOS tube M9 and a tenth NMOS tube M10, wherein the source electrode of the eighth NMOS tube M8 is connected with the drain electrode of the seventh PMOS tube and the grid electrodes of the twelfth NMOS tube M12, the first NMOS tube M1 and the Ms switch tube, the drain electrode of the eighth NMOS tube M8 is connected with the drain electrode of the ninth PMOS tube M9 and the source electrode of the tenth NMOS tube M10, and the grid electrode of the eighth NMOS tube M8 and the source electrode of the ninth PMOS tube are connected with a power supply voltage end.
5. The high linearity sampling switch circuit of claim 4, wherein: in the charge discharge module, the gates of the ninth PMOS transistor M9 and the tenth NMOS transistor M10 are connected to a clock control signal CLKSB, the drain of the ninth PMOS transistor is connected to the drain of the eighth NMOS transistor M8 and the source of the tenth NMOS transistor M10, and the source of the ninth PMOS transistor M9 and the gate of the eighth NMOS transistor M8 are connected to a power supply voltage terminal; the tenth NMOS transistor M10 has a drain grounded end, a gate connected to the clock control signal CLKSB, and a source connected to the drain of the eighth NMOS transistor M8 and the drain of the ninth PMOS transistor M9, respectively.
6. The high linearity sampling switch circuit of claim 1, wherein: the charge pump module comprises a second NMOS tube M2, a third NMOS tube M3, a seventeenth NMOS tube M17, an eighteenth PMOS tube M18, a first energy storage capacitor C1 and a second energy storage capacitor C2; the drain electrode of the second NMOS tube M2 is connected with a power supply voltage end, the grid electrode of the second NMOS tube M2 is respectively connected with the upper electrode of the second energy storage capacitor C2 and the source electrode of the third NMOS tube M3, and the source electrode of the second NMOS tube M2 is connected with the upper electrode of the first energy storage capacitor C1 and the grid electrode of the third NMOS tube; the drain electrode of the third NMOS tube M3 is connected with a power supply voltage end, the source electrode is connected with the upper electrode of the second energy storage capacitor C2 and the grid electrode of the second NMOS tube M2, and the grid electrode is connected with the upper electrode of the first energy storage capacitor C1, the source electrode of the second NMOS tube M2, the source electrode of the seventeenth NMOS tube M17 and the drain electrode of the eighteenth PMOS tube M18; the source electrode of the seventeenth NMOS tube M17 is connected with the grid electrode of the third NMOS tube M3 and the drain electrode of the eighteenth PMOS tube M8, and the drain electrode is connected with the source electrode of the eighteenth PMOS tube M18 and the grid electrode of the fourth NMOS tube M4; the grid is connected with a clock control signal CLKSB; the drain electrode of the eighteenth PMOS tube M18 is connected with the grid electrode of the third NMOS tube M3 and the source electrode of the seventeenth NMOS tube M17; the source electrode is connected with the drain electrode of the seventeenth NMOS tube M17 and the grid electrode of the fourth NMOS tube M4; the grid is connected with a clock control signal CLKS; the lower electrode of the first energy storage capacitor C1 and the grid electrode of the thirteenth NMOS tube are connected to a clock control signal CLKSB, and the lower electrode of the second energy storage capacitor C2 is connected to a clock control signal CLKS; in the holding stage, the gate voltage of the fourth NMOS transistor M4 is raised to 2VDD by the charge pump module, so that the fourth NMOS transistor M4 is deeply turned on.
7. The high linearity sampling switch circuit of claim 6, wherein: the grid voltage bootstrap module comprises a fourth NMOS tube M4, a thirteenth NMOS tube M13, a fifth PMOS tube M5, a sixth NMOS tube M6, a seventh PMOS tube M7, a complementary switch formed by an M11 tube and an M12 tube, and a bootstrap capacitor Ch; the grid electrode of the fourth NMOS tube M4 is in short circuit with the drain electrode, and the grid electrode is connected with the drain electrode of the seventeenth NMOS tube M17 and the source electrode of the eighteenth PMOS tube M18; the drain electrode is connected with the drain electrode of the seventeenth NMOS tube M17 and the source electrode of the eighteenth PMOS tube M18; the gate of the thirteenth NMOS transistor M13 is connected to the clock control signal CLKSB, the source is grounded, and the drain is connected to the lower electrode of the bootstrap capacitor, the drain of the eleventh PMOS transistor M11, the source of the twelfth NMOS transistor M2, and the first NMOS transistor M1, respectively; the source electrode of the fifth PMOS tube M5 is connected with the power supply voltage end, the drain electrode of the fifth PMOS tube M5 is respectively connected with the drain electrode of the sixth NMOS tube M6 and the grid electrode of the seventh PMOS tube M7, and the grid electrodes of the grid electrode and the M6 are connected with the clock control signal CLKS; a source electrode of the sixth NMOS tube is grounded, and a drain electrode of the sixth NMOS tube is respectively connected with a drain electrode of the fifth PMOS tube M5 and a gate electrode of the seventh PMOS tube M7; the grid electrode of the seventh PMOS transistor M7 is connected with the drain electrode of the fifth PMOS transistor M5, the drain electrode of the sixth NMOS transistor M6, the source electrode of the eleventh PMOS transistor M11, and the drain electrode of the twelfth NMOS transistor M12, the source electrode is connected with the upper electrode of the bootstrap capacitor and the source electrode of the fourth NMOS transistor M4, and the drain electrode is connected with the source electrode of the eighth NMOS transistor M8.
8. A high linearity sampling switch circuit as claimed in claim 7, wherein: in the gate voltage bootstrap module, a gate of the eleventh PMOS transistor M11 is connected to the clock control signal CLKSB, a source is connected to a drain of the twelfth NMOS transistor M12 and a gate of the seventh PMOS transistor M7, and a drain is connected to a source of the twelfth NMOS transistor M12, a source of the first NMOS transistor M1 and a drain of the thirteenth NMOS transistor M13; the drain electrode of the twelfth NMOS tube is connected with the drain electrode of the sixth NMOS tube M6 and the grid electrode of the seventh PMOS tube, the grid electrode of the twelfth NMOS tube is connected with the source electrode of the eighth NMOS tube M8, the grid electrode of the first NMOS tube M1 and the grid electrode of the Ms switch tube, and the source electrode of the twelfth NMOS tube is connected with the drain electrode of the thirteenth NMOS tube M13 and the source electrode of the first NMOS tube M1.
9. A high linearity sampling switch circuit as claimed in claim 1, wherein: the complementary switch module comprises a sampling switch tube Ms and a sixteenth PMOS tube M16; the source electrode of the Ms switch tube is connected with the drain electrode of the first NMOS tube M1 and the drain electrode of the sixteenth PMOS tube M16, the grid electrode of the Ms switch tube is respectively connected with the grid electrode of the first NMOS tube M1, the grid electrode of the twelfth NMOS tube M12 and the source electrode of the eighth NMOS tube M8, the drain electrode of the Ms switch tube is connected with the positive phase end of the voltage follower and the source electrode of the sixteenth PMOS tube M16, the grid electrode of the sixteenth PMOS tube M16 is connected with the clock control signal CLKSB, the drain electrode is connected with the source electrode of the sampling switch tube Ms and the drain electrode of the first NMOS tube M1, and the source electrode is connected with the positive phase end of the voltage follower and the drain electrode of the Ms switch tube.
10. The high linearity sampling switch circuit of claim 1, wherein: the sampling isolation module comprises a voltage follower and a load capacitor CL; the positive phase end of the voltage follower is connected with the drain electrode of the Ms switch tube and the source electrode of the sixteenth PMOS tube M16, and the negative phase end of the voltage follower is connected with the output end of the voltage follower and the upper electrode of the load capacitor;
the lower electrode of the load capacitor is connected with the ground, and the upper electrode is connected with the output end of the voltage follower and the inverting end of the voltage follower.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116896363A (en) * | 2023-09-08 | 2023-10-17 | 成都利普芯微电子有限公司 | NMOS control circuit and battery protection chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116896363A (en) * | 2023-09-08 | 2023-10-17 | 成都利普芯微电子有限公司 | NMOS control circuit and battery protection chip |
| CN116896363B (en) * | 2023-09-08 | 2023-12-05 | 成都利普芯微电子有限公司 | NMOS control circuit and battery protection chip |
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