CN112599436A - Transistor and STI abnormal hole detection method - Google Patents
Transistor and STI abnormal hole detection method Download PDFInfo
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Abstract
The invention provides a transistor and a method for detecting STI abnormal holes, wherein a grid electrode and a source electrode are floated on the basis of a transistor with an STI region positioned between a first N-type doped region and a second N-type doped region on a P-type substrate, and a drain electrode is connected with a preset voltage to obtain a first change condition of leakage current; floating the grid electrode, grounding the source electrode, and accessing the drain electrode to the preset voltage to obtain a second change condition of the leakage current; and judging whether the STI region has an abnormal hole or not according to the first change condition and the second change condition. According to the detection method, the change conditions of the leakage current are respectively obtained under two power-on conditions, when the STI region has the abnormal hole, the additional leakage current is generated, so that the second change condition of the leakage current inevitably has obvious change, and whether the STI region has the abnormal hole or not can be obviously judged through the two change conditions of the leakage current.
Description
Technical Field
The present invention relates to the field of integrated circuit manufacturing technologies, and more particularly, to a transistor and a method for detecting STI abnormal holes.
Background
With the continuous development of science and technology, various electronic devices are widely applied to the life and work of people, and great convenience is brought to the daily life of people.
Based on various electronic devices, it is obvious that an integrated circuit chip cannot be separated, and the size of the integrated circuit chip is getting smaller and smaller at present, so that the aspect ratio of STI (Shallow Trench Isolation) is getting larger and larger, and the conventional CVD (Chemical vapor Deposition) method cannot fill STI well, so that the STI is filled by using the method of Flowable CVD (FCVD for short) at present.
Although FCVD has a good hole filling capability, the FCVD is prone to have a local hole problem during the hole filling process, which results in poor insulation of the transistor and increased leakage current.
Currently, PFA/TEM is generally used in the art to verify whether STI has abnormal holes, but since the abnormal holes only occur occasionally and do not necessarily occur, the PFA/TEM is not necessarily able to detect the abnormal holes and the testing time is long.
Therefore, it is an urgent technical problem to be solved by those skilled in the art to provide an effective method for detecting STI abnormal holes.
Disclosure of Invention
In view of the above, to solve the above problems, the present invention provides a transistor and a method for detecting STI abnormal holes, and the technical solution is as follows:
a method for detecting STI abnormal holes is based on a transistor, and the transistor comprises: a P-type substrate; the P-type substrate is provided with a first N-type doped region, a second N-type doped region and an STI region arranged between the first N-type doped region and the second N-type doped region; a gate completely covering the STI region and partially covering the first N-type doped region and the second N-type doped region; the first N-type doped region is used as a source electrode, and the second N-type doped region is used as a drain electrode;
the detection method comprises the following steps:
floating the grid electrode and the source electrode, and accessing a preset voltage to the drain electrode to obtain a first change condition of leakage current;
floating the grid electrode, grounding the source electrode, and accessing the drain electrode to the preset voltage to obtain a second change condition of the leakage current;
and judging whether the STI region has an abnormal hole or not according to the first change condition and the second change condition.
Optionally, in the above detection method, when detecting an STI region of one transistor, the determining whether the STI region has an abnormal hole according to the first variation and the second variation includes:
and when the leakage current variation trends of the second variation situation and the first variation situation are close, indicating that no abnormal hole exists in the STI region.
Optionally, in the above detection method, when detecting an STI region of one transistor, the determining whether the STI region has an abnormal hole according to the first variation and the second variation includes:
when the leakage current variation trends of the second variation and the first variation have obvious difference, the STI region has abnormal holes.
Optionally, in the above detection method, when detecting STI regions of a plurality of transistors connected in series, the determining whether the STI regions have abnormal holes according to the first variation and the second variation includes:
and when the leakage current variation trends of the second variation situation and the first variation situation accord with a preset multiple, indicating that no abnormal hole exists in the STI region.
Optionally, in the above detection method, when detecting STI regions of a plurality of transistors connected in series, the determining whether the STI regions have abnormal holes according to the first variation and the second variation includes:
and when the leakage current variation trends of the second variation situation and the first variation situation exceed a preset multiple, indicating that the STI region has an abnormal hole.
A transistor, the transistor comprising:
a P-type substrate; the P-type substrate is provided with a first N-type doped region, a second N-type doped region and an STI region arranged between the first N-type doped region and the second N-type doped region;
the grid electrode is arranged on one side of the P-type substrate, completely covers the STI region, and partially covers the first N-type doped region and the second N-type doped region;
the first N-type doped region serves as a source electrode, and the second N-type doped region serves as a drain electrode.
Optionally, in the transistor, a bottom width of the STI region is 70 nm.
Optionally, in the transistor, a width of the gate is 72 nm.
Optionally, in the transistor, a width of the gate electrode covering the first N-type doped region is 10 nm.
Optionally, in the transistor, a width of the gate electrode covering the second N-type doped region is 10 nm.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a method for detecting an STI abnormal hole, which is characterized in that a grid electrode and a source electrode are floated on the basis of a transistor with an STI region positioned between a first N-type doped region and a second N-type doped region on a P-type substrate, and a drain electrode is connected with a preset voltage to obtain a first change condition of leakage current; floating the grid electrode, grounding the source electrode, and accessing the drain electrode to the preset voltage to obtain a second change condition of the leakage current; and judging whether the STI region has an abnormal hole or not according to the first change condition and the second change condition. According to the detection method, the change conditions of the leakage current are respectively obtained under two power-on conditions, when the STI region has the abnormal hole, the additional leakage current is generated, so that the second change condition of the leakage current inevitably has obvious change, and whether the STI region has the abnormal hole or not can be obviously judged through the two change conditions of the leakage current.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a transistor according to an embodiment of the present invention;
fig. 2 is a schematic diagram illustrating a dimensional structure of a transistor according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a dimensional structure of another transistor according to an embodiment of the present invention;
fig. 4 is a schematic diagram illustrating a dimensional structure of another transistor according to an embodiment of the present invention;
fig. 5 is a schematic flow chart illustrating a method for detecting an STI abnormal hole according to an embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating a situation of detecting a leakage current variation of an STI region having an abnormal hole according to an embodiment of the present invention;
FIG. 7 is a schematic diagram illustrating another embodiment of detecting a leakage current variation of an STI region with abnormal holes;
FIG. 8 is a schematic diagram illustrating another variation of leakage current for detecting abnormal holes in an STI region according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a transistor according to an embodiment of the present invention.
The transistor includes:
a P-type substrate 11; the P-type substrate 11 is provided with a first N-type doped region 12, a second N-type doped region 13 and an STI region 14 arranged between the first N-type doped region 12 and the second N-type doped region 13;
a gate 15 disposed on one side of the P-type substrate 11, wherein the gate 15 completely covers the STI region 14 and partially covers the first N-type doped region 12 and the second N-type doped region 13;
the first N-type doped region 12 serves as a source 16, and the second N-type doped region 13 serves as a drain 17.
In this embodiment, in the transistor provided by the present invention, the STI region 14 is disposed between the first N-type doped region 12 and the second N-type doped region 13, and is used for isolating the first N-type doped region 12 from the second N-type doped region 13.
Further, based on the above embodiments of the present invention, referring to fig. 2, fig. 2 is a schematic diagram of a size structure of a transistor according to an embodiment of the present invention.
The bottom width of the STI region 14 is 70 nm.
In this embodiment, the minimum width of the bottom of the STI region 14 is about 70nm, and only 70nm is taken as an example in the embodiment of the present invention.
Further, based on the above embodiments of the present invention, referring to fig. 3, fig. 3 is a schematic diagram of a dimensional structure of another transistor according to the embodiments of the present invention.
The width of the gate 15 is 72 nm.
In this embodiment, the width of the gate 15 is larger than the width of the top opening of the STI region 14, and 72nm is taken as an example in the embodiment of the present invention.
Further, based on the above embodiments of the present invention, referring to fig. 4, fig. 4 is a schematic diagram of a dimensional structure of another transistor according to an embodiment of the present invention.
The width of the gate 15 covering the first N-type doped region 12 is 10 nm.
The width of the gate 15 covering the second N-type doped region 13 is 10 nm.
In this embodiment, the width of the gate 15 covering the first N-type doped region 12 and the second N-type doped region 13 is the same, and 10nm is taken as an example here for explanation, and the size is not limited.
Further, based on all the above embodiments of the present invention, another embodiment of the present invention further provides a method for detecting an STI abnormal hole, and referring to fig. 5, fig. 5 is a schematic flow chart of the method for detecting an STI abnormal hole according to the embodiment of the present invention.
The detection method is based on the transistor provided by the above embodiment of the present invention, as shown in fig. 1, the transistor includes: a P-type substrate; the P-type substrate is provided with a first N-type doped region, a second N-type doped region and an STI region arranged between the first N-type doped region and the second N-type doped region; a gate completely covering the STI region and partially covering the first N-type doped region and the second N-type doped region; the first N-type doped region serves as a source electrode, and the second N-type doped region serves as a drain electrode.
As shown in fig. 5, the detection method includes:
s101: and floating the grid electrode and the source electrode, and accessing a preset voltage to the drain electrode to obtain a first change condition of the leakage current.
S102: and floating the grid electrode, grounding the source electrode, and accessing the drain electrode to the preset voltage to obtain a second change condition of the leakage current.
S103: and judging whether the STI region has an abnormal hole or not according to the first change condition and the second change condition.
In this embodiment, the detection method obtains the variation of the leakage current under two power-on conditions, respectively, and when the STI region has an abnormal hole, the leakage current will be generated, so that the second variation of the leakage current will inevitably have an obvious variation, and it is obvious that whether the STI region has the abnormal hole can be determined through the two variation of the leakage current.
Further, based on the above embodiment of the present invention, when detecting an STI region of one of the transistors, the determining whether the STI region has an abnormal hole according to the first variation and the second variation includes:
and when the leakage current variation trends of the second variation situation and the first variation situation are close, indicating that no abnormal hole exists in the STI region.
In this embodiment, the first variation of the leakage current is: the grid electrode and the source electrode are floating, the drain electrode is connected with a preset voltage, the drain current of the source electrode is measured, and the drain current is increased along with the rise of the preset voltage of the drain electrode.
The second variation of the leakage current is: and floating the gate, grounding the source, accessing the drain to the preset voltage, measuring the drain current of the source, and when the STI region has no abnormal hole, indicating that no other extra drain current exists, increasing the drain current along with the rise of the preset voltage of the drain, wherein the change trend is basically the same as that of the first change condition of the drain current.
Further, based on the above embodiments of the present invention, referring to fig. 6, fig. 6 is a schematic diagram illustrating a situation of detecting a leakage current variation of an abnormal hole in an STI region according to an embodiment of the present invention.
When detecting the STI region of one transistor, the determining whether the STI region has an abnormal hole according to the first variation and the second variation includes:
when the leakage current variation trends of the second variation and the first variation have obvious difference, the STI region has abnormal holes.
In this embodiment, as shown in fig. 6, the first variation of the leakage current is: the grid electrode and the source electrode are floating, the drain electrode is connected with a preset voltage, the drain current of the source electrode is measured, and the drain current is increased along with the rise of the preset voltage of the drain electrode.
The second variation of the leakage current is: and when the STI region has abnormal holes, the leakage current jumping from the abnormal holes is generated, and the measured leakage current is obviously increased compared with the first change condition.
Therefore, by respectively acquiring the change conditions of the leakage current under two power-on conditions, when the STI region has abnormal holes, additional leakage current is generated, so that the second change condition of the leakage current inevitably has obvious change, and obviously, whether the STI region has the abnormal holes or not can be judged through the two change conditions of the leakage current.
Further, based on the above-mentioned embodiments of the present invention, referring to fig. 7, fig. 7 is a schematic view illustrating another leakage current variation condition for detecting an abnormal hole in an STI region according to an embodiment of the present invention.
When detecting the STI regions of the transistors connected in series, the determining whether the STI regions have abnormal holes according to the first variation and the second variation includes:
and when the leakage current variation trends of the second variation situation and the first variation situation accord with a preset multiple, indicating that no abnormal hole exists in the STI region.
In this embodiment, the first variation of the leakage current is: the grid and the source are floating, the drain is connected with a preset voltage, and the drain current to the source in one transistor is measured and is increased along with the rise of the preset voltage of the drain.
The second variation of the leakage current is: the grid electrode is floated, the source electrode is grounded, the drain electrode is connected to the preset voltage, and the drain current to the source electrode in the plurality of series-connected transistors is measured.
Further, based on the above-mentioned embodiment of the present invention, referring to fig. 8, fig. 8 is a schematic view illustrating a leakage current variation condition for detecting an abnormal hole in an STI region according to another embodiment of the present invention.
When detecting the STI regions of the transistors connected in series, the determining whether the STI regions have abnormal holes according to the first variation and the second variation includes:
and when the leakage current variation trends of the second variation situation and the first variation situation exceed a preset multiple, indicating that the STI region has an abnormal hole.
In this embodiment, the first variation of the leakage current is: the grid and the source are floating, the drain is connected with a preset voltage, and the drain current to the source in one transistor is measured and is increased along with the rise of the preset voltage of the drain.
The second variation of the leakage current is: the gate is floated, the source electrode is grounded, the drain electrode is connected to the preset voltage, leakage current from the source electrode to the plurality of serially connected transistors is measured, obviously, the test area of the plurality of serially connected transistors is increased, when an abnormal hole exists in the STI region, leakage current jumping from the abnormal hole is generated under the condition that the measured leakage current is multiplied along with the area, and the measured leakage current is obviously increased compared with the first change condition.
Therefore, the invention can test the STI abnormal holes of a plurality of transistors after being connected in series, thereby improving the test efficiency.
The transistor and the STI abnormal hole detection method provided by the present invention are described in detail above, and the principle and the implementation of the present invention are explained in the present document by applying specific examples, and the description of the above embodiments is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include or include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A method for detecting STI abnormal holes is characterized in that the method is based on a transistor, and the transistor comprises: a P-type substrate; the P-type substrate is provided with a first N-type doped region, a second N-type doped region and an STI region arranged between the first N-type doped region and the second N-type doped region; a gate completely covering the STI region and partially covering the first N-type doped region and the second N-type doped region; the first N-type doped region is used as a source electrode, and the second N-type doped region is used as a drain electrode;
the detection method comprises the following steps:
floating the grid electrode and the source electrode, and accessing a preset voltage to the drain electrode to obtain a first change condition of leakage current;
floating the grid electrode, grounding the source electrode, and accessing the drain electrode to the preset voltage to obtain a second change condition of the leakage current;
and judging whether the STI region has an abnormal hole or not according to the first change condition and the second change condition.
2. The method as claimed in claim 1, wherein when detecting an STI region of one of the transistors, said determining whether the STI region has an abnormal hole according to the first variation and the second variation comprises:
and when the leakage current variation trends of the second variation situation and the first variation situation are close, indicating that no abnormal hole exists in the STI region.
3. The method as claimed in claim 1, wherein when detecting an STI region of one of the transistors, said determining whether the STI region has an abnormal hole according to the first variation and the second variation comprises:
when the leakage current variation trends of the second variation and the first variation have obvious difference, the STI region has abnormal holes.
4. The method as claimed in claim 1, wherein when detecting STI regions of a plurality of transistors connected in series, said determining whether the STI regions have abnormal holes according to the first variation and the second variation comprises:
and when the leakage current variation trends of the second variation situation and the first variation situation accord with a preset multiple, indicating that no abnormal hole exists in the STI region.
5. The method as claimed in claim 1, wherein when detecting STI regions of a plurality of transistors connected in series, said determining whether the STI regions have abnormal holes according to the first variation and the second variation comprises:
and when the leakage current variation trends of the second variation situation and the first variation situation exceed a preset multiple, indicating that the STI region has an abnormal hole.
6. A transistor, comprising:
a P-type substrate; the P-type substrate is provided with a first N-type doped region, a second N-type doped region and an STI region arranged between the first N-type doped region and the second N-type doped region;
the grid electrode is arranged on one side of the P-type substrate, completely covers the STI region, and partially covers the first N-type doped region and the second N-type doped region;
the first N-type doped region serves as a source electrode, and the second N-type doped region serves as a drain electrode.
7. The transistor of claim 6, wherein the bottom width of the STI region is 70 nm.
8. The transistor of claim 6, wherein the gate has a width of 72 nm.
9. The transistor of claim 6, wherein the gate covers the first N-type doped region by a width of 10 nm.
10. The transistor of claim 6, wherein the gate covers the second N-type doped region by a width of 10 nm.
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