CN210640254U - Semiconductor structure - Google Patents
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- CN210640254U CN210640254U CN201922132369.9U CN201922132369U CN210640254U CN 210640254 U CN210640254 U CN 210640254U CN 201922132369 U CN201922132369 U CN 201922132369U CN 210640254 U CN210640254 U CN 210640254U
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Abstract
The utility model relates to the field of semiconductor technology, a semiconductor structure is proposed, this semiconductor structure includes: the deep doping well and the semiconductor substrate have different doping types and are wrapped in the semiconductor substrate, so that PN junctions are respectively formed between two opposite side surfaces of the deep doping well and the semiconductor substrate in the stacking direction; an annular doped portion formed in the semiconductor substrate; a gate insulating layer disposed on the semiconductor substrate; the grid is arranged on one side of the grid insulating layer, which is far away from the semiconductor substrate, and the orthographic projection of the grid on the semiconductor substrate is positioned outside the deep doped well; a dielectric layer disposed on the semiconductor substrate; the first probe pad is arranged on one side of the dielectric layer, which is far away from the semiconductor substrate, and the orthographic projection of the first probe pad on the semiconductor substrate is positioned in the deep doping well; the wire is connected between the first probe pad and the grid electrode. The semiconductor structure can accurately and conveniently measure the capacitance between the grid and the semiconductor substrate.
Description
Technical Field
The utility model relates to the field of semiconductor technology, especially, relate to a semiconductor structure.
Background
The capacitor structure generally includes a Metal-Oxide-Semiconductor (MOS) capacitor, a Metal-Oxide-Metal (MOM) capacitor, a Metal-Insulator-Metal (MIM) capacitor, and a Poly-Insulator-Poly (PIP) capacitor. The capacitor structure needs to check its capacitance parameters. Taking a MOS capacitor as an example, the MOS capacitor generally includes a semiconductor substrate, a gate insulating layer formed on the semiconductor substrate, and a gate formed on the gate insulating layer. A capacitance structure is formed between the grid and the semiconductor substrate, and the capacitance structure formed between the grid and the semiconductor substrate cannot be directly measured due to the small area of the grid.
In the related art, a probe pad is generally formed on a semiconductor substrate and connected to a gate electrode through a wire. The capacitance detection device can be directly used for measuring the capacitance structure between the grid electrode and the semiconductor substrate through the probe pad due to the large area of the probe pad.
However, a capacitor structure is also formed between the probe pad and the semiconductor substrate, and the capacitor structure forms a parallel structure with a capacitor structure formed between the gate and the semiconductor substrate. Therefore, the capacitance measured by the probe pad includes the capacitance between the probe pad and the semiconductor substrate and the capacitance formed between the gate and the semiconductor substrate, which results in inaccurate test results.
It should be noted that the information of the present invention in the above background section is only for enhancing the understanding of the background of the present invention, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a semiconductor structure, this semiconductor structure can solve in the correlation technique, to the unsafe technical problem of capacitance measurement between its grid, the semiconductor substrate.
Other features and advantages of the invention will be apparent from the following detailed description, or may be learned by practice of the invention in part.
According to an aspect of the present invention, there is provided a semiconductor structure, comprising: the semiconductor device comprises a semiconductor substrate, a deep doping well, an annular doping part, a grid insulation layer, a grid, a dielectric layer, a first probe pad and a lead, wherein the deep doping well and the semiconductor substrate have different doping types and are wrapped in the semiconductor substrate, so that two opposite side surfaces of the deep doping well in the stacking direction respectively form PN junctions with the semiconductor substrate; the annular doping part and the deep doping well have the same doping type and are formed in the semiconductor substrate, wherein a first annular opening of the annular doping part is connected with the deep doping well, and a second annular opening of the annular doping part is located on the surface of the semiconductor substrate; the semiconductor substrate is located at the position surrounded by the annular doping part and is in a floating state; the gate insulating layer is arranged on the semiconductor substrate; the grid is arranged on one side of the grid insulating layer, which is far away from the semiconductor substrate, and the orthographic projection of the grid on the semiconductor substrate is positioned outside the deep doped well; the dielectric layer is arranged on the semiconductor substrate; the first probe pad is arranged on one side of the dielectric layer, which is far away from the semiconductor substrate, and the orthographic projection of the first probe pad on the semiconductor substrate is positioned in the deep doping well; the wire is connected between the first probe pad and the grid.
In an exemplary embodiment of the present invention, the semiconductor structure further includes: two heterodoping portions, source/drain layers. The two opposite doping parts are arranged in the semiconductor substrate and are opposite to the doping type of the semiconductor substrate, and the orthographic projections of the two opposite doping parts on the semiconductor substrate are positioned on the two opposite sides of the orthographic projection of the grid electrode on the semiconductor substrate; the source/drain layer comprises a first source/drain part and a second source/drain part, the first source/drain part and the second source/drain part are arranged on one side of the dielectric layer, which is far away from the semiconductor substrate, the first source/drain part is connected with one heterodoping part through a via hole in the dielectric layer, and the second source/drain part is connected with the other heterodoping part through another via hole in the dielectric layer.
In an exemplary embodiment of the present invention, the semiconductor structure further includes an annular doped portion, the annular doped portion has the same doping type as the deep doped well, and is formed in the semiconductor substrate, wherein the first annular opening of the annular doped portion is connected to the deep doped well, and the second annular opening of the annular doped portion is located on the surface of the semiconductor substrate.
In an exemplary embodiment of the present invention, the semiconductor structure further includes a second probe pad disposed on one side of the semiconductor substrate away from the dielectric layer, the second probe pad passing through the via hole on the dielectric layer and connected to the semiconductor substrate.
In an exemplary embodiment of the present invention, an area of the deep doping well is equal to or larger than an area of the first probe pad.
In an exemplary embodiment of the present invention, the semiconductor substrate is an N-type semiconductor, and the deep doped well is a P-type well.
In an exemplary embodiment of the present invention, the semiconductor substrate is a P-type semiconductor, and the deep doped well is an N-type well.
In an exemplary embodiment of the present invention, the first probe pad is a metal first probe pad.
According to an aspect of the present invention, there is provided a method for fabricating a semiconductor structure, the method comprising:
providing a semiconductor substrate;
forming a deep doped well in the semiconductor substrate, wherein the deep doped well is wrapped in the semiconductor substrate, so that two opposite side surfaces of the deep doped well in the stacking direction respectively form PN junctions with the semiconductor substrate, and the semiconductor substrate has different doping types;
forming an annular doping part in the semiconductor substrate, wherein the annular doping part and the deep doping well have the same doping type, a first annular opening of the annular doping part is connected with the deep doping well, and a second annular opening of the annular doping part is located on the surface of the semiconductor substrate;
the semiconductor substrate is located at the position surrounded by the annular doping part and is in a floating state;
forming a gate insulating layer on the semiconductor substrate;
forming a gate on one side of the gate insulating layer, which faces away from the semiconductor substrate, wherein the orthographic projection of the gate on the semiconductor substrate is positioned outside the deep doped well;
forming a dielectric layer on the semiconductor substrate;
forming a first probe pad on one side of the dielectric layer, which faces away from the semiconductor substrate, wherein the orthographic projection of the first probe pad on the semiconductor substrate is positioned in the deep doping well;
forming a wire to connect the first probe pad and the gate.
In an exemplary embodiment of the present invention, a deep doped well is formed in the semiconductor substrate, including:
providing a mask plate, wherein the mask plate is provided with an annular hollow area;
and carrying out ion implantation on the semiconductor substrate by using the mask plate to form a deep doped well.
In an exemplary embodiment of the present invention, the mask is utilized to perform ion implantation on the semiconductor substrate, and the annular doped portion is further formed, the first annular opening of the annular doped portion is connected to the deep doped well, and the second annular opening of the annular doped portion is located on the surface of the semiconductor substrate.
According to an aspect of the present invention, there is provided a method for detecting capacitance of a semiconductor structure, the method comprising:
inputting constant current to the first probe pad by using a constant current source;
detecting the change state of the voltage on the first probe pad along with time in real time;
and acquiring the capacitance of the capacitance structure according to the change state of the voltage on the first probe pad along with time.
In an exemplary embodiment of the present invention, the capacitance of the capacitance structure is obtained according to a state of change of the voltage on the first probe pad with time, including:
the capacitance is calculated according to the formula C ═ It/V, where I is the output current value of the constant current source, t is time, and V is a voltage value corresponding to time.
The present disclosure provides a semiconductor structure, which includes: the semiconductor device comprises a semiconductor substrate, a deep doping well, an annular doping part, a grid insulation layer, a grid, a dielectric layer, a first probe pad and a lead, wherein the deep doping well and the semiconductor substrate have different doping types and are wrapped in the semiconductor substrate, so that two opposite side surfaces of the deep doping well in the stacking direction respectively form PN junctions with the semiconductor substrate; the annular doping part and the deep doping well have the same doping type and are formed in the semiconductor substrate, wherein a first annular opening of the annular doping part is connected with the deep doping well, and a second annular opening of the annular doping part is located on the surface of the semiconductor substrate; the semiconductor substrate is located at the position surrounded by the annular doping part and is in a floating state; the gate insulating layer is arranged on the semiconductor substrate; the grid is arranged on one side of the grid insulating layer, which is far away from the semiconductor substrate, and the orthographic projection of the grid on the semiconductor substrate is positioned outside the deep doped well; the dielectric layer is arranged on the semiconductor substrate; the first probe pad is arranged on one side of the dielectric layer, which is far away from the semiconductor substrate, and the orthographic projection of the first probe pad on the semiconductor substrate is positioned in the deep doping well; the wire is connected between the first probe pad and the grid. The semiconductor structure provided by the disclosure can accurately and conveniently measure the capacitance between the grid and the semiconductor substrate.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
FIG. 1 is a cross-sectional view of a semiconductor structure in accordance with the related art;
FIG. 2 is an equivalent circuit diagram of a capacitance sensing structure in the semiconductor structure of FIG. 1;
FIG. 3 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor structure according to the present disclosure;
FIG. 4 is an equivalent circuit diagram of the capacitance sensing structure in the semiconductor structure of FIG. 3;
FIG. 5 is a top view of an exemplary embodiment of a semiconductor structure of the present disclosure;
FIG. 6 is a flow chart of one exemplary embodiment of a method of fabricating a semiconductor structure according to the present disclosure;
FIG. 7 is a flow chart of one exemplary embodiment of a method for capacitive sensing of a semiconductor structure according to the present disclosure;
FIG. 8 is a diagram illustrating the variation of the voltage on the first probe pad over time according to an exemplary embodiment of the method for capacitive sensing of a semiconductor structure of the present disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.
Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". Other relative terms, such as "high," "low," "top," "bottom," "left," "right," and the like are also intended to have similar meanings. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
The terms "a," "an," "the," and the like are used to denote the presence of one or more elements/components/parts; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.
Fig. 1 is a schematic cross-sectional view of a semiconductor structure in the related art. The semiconductor structure comprises a semiconductor substrate 01, a gate insulating layer 02, a gate 03, a dielectric layer 06 and a probe pad 04. The gate 03, the gate insulating layer 02 and the semiconductor substrate 01 form a MOS capacitor, and the gate 03 and the probe pad 04 are connected by a wire. As shown in fig. 1, a via hole may be further formed on the dielectric layer so that a source/drain layer 05 connected to the semiconductor substrate may be formed through the via hole. It should be noted that other dielectric layers may be disposed on the dielectric layer 06, and the probe pad 04 should include a probe portion on the uppermost dielectric layer, and at this time, a probe portion may be disposed on each dielectric layer, and each probe portion is electrically connected through a via hole on the dielectric layer. Fig. 2 is an equivalent circuit diagram of the capacitance detection structure in the semiconductor structure of fig. 1. N1 represents the isoelectric point of probe pad 04, and N2 represents the isoelectric point of semiconductor substrate 01. A capacitor C1 to be tested is formed between the grid 03 and the semiconductor substrate 01, a parasitic capacitor C2 is formed between the probe pad 04 and the semiconductor substrate 01, and a capacitor C1 to be tested and the parasitic capacitor C2 form a parallel capacitor structure. When the capacitance of the capacitor structure to be measured formed between the gate 03 and the semiconductor substrate 01 is detected through the probe pad 04, the actually measured capacitance is C1+ C2. The detection value is larger than an actual capacitance value formed between the gate electrode 03 and the semiconductor substrate 01.
Based on this, the present exemplary embodiment provides a semiconductor structure, as shown in fig. 3, 4 and 5, fig. 3 is a schematic cross-sectional view of a structure of an exemplary embodiment of the semiconductor structure of the present disclosure, fig. 4 is an equivalent circuit diagram of a capacitance detection structure in the semiconductor structure of fig. 3, and fig. 5 is a top view of an exemplary embodiment of the semiconductor structure of the present disclosure.
As shown in fig. 3 and 5, the semiconductor structure comprises: the semiconductor device comprises a semiconductor substrate 1, a deep doping well 2, an annular doping part 6, a grid insulation layer 3, a grid 4, a dielectric layer 12, a first probe pad 5 and a lead 13 connecting the grid 4 and the first probe pad 5, wherein the deep doping well 2 and the semiconductor substrate 1 have different doping types and are wrapped in the semiconductor substrate, so that two opposite side surfaces of the deep doping well in the stacking direction respectively form PN junctions with the semiconductor substrate; an annular doping part 6 and the deep doping well have the same doping type and are formed in the semiconductor substrate 1, wherein a first annular opening of the annular doping part 6 is connected with the deep doping well 2, and a second annular opening of the annular doping part is located on the surface of the semiconductor substrate 1; wherein, the semiconductor substrate 1 is located at the semiconductor substrate part 11 surrounded by the annular doping part and is in a floating state; the gate insulating layer 3 is disposed on the semiconductor substrate 1; the gate 4 is arranged on one side of the gate insulating layer 3, which is far away from the semiconductor substrate 1, and the orthographic projection of the gate 4 on the semiconductor substrate 1 is positioned outside the deep doped well 2; a dielectric layer 12 is disposed on the semiconductor substrate 1, the dielectric layer 12 may cover the gate 4; the first probe pad 5 is arranged on one side of the dielectric layer 12, which is far away from the semiconductor substrate 1, and the orthographic projection of the first probe pad 5 on the semiconductor substrate 1 is positioned in the deep doping well 2; the wires 13 are connected between the first probe pads 5 and the gate 4. Wherein, the stacking direction may refer to a direction perpendicular to the functional layer direction of the semiconductor structure; the floating state means that the semiconductor substrate portion 11 is isolated from other positions of the semiconductor substrate, and the potential of the semiconductor substrate portion 11 is not affected by the potential of the semiconductor substrate.
As shown in fig. 4, N1 represents the isoelectric point of the first probe pad 5, and N2 represents the isoelectric point of the semiconductor substrate 1. A capacitor C1 is formed between the gate 4 and the semiconductor substrate 1, a capacitor C2 is formed between the first probe pad 5 and the semiconductor substrate 1, a parasitic PN junction exists between the doped well 2 and the semiconductor substrate 11 on the upper portion of the doped well and has a parasitic junction capacitor C3, and a parasitic PN junction exists between the doped well 2 and the semiconductor substrate on the lower portion of the doped well and has a parasitic junction capacitor C4. The capacitor C2, the junction capacitor C3 and the junction capacitor C4 form a series capacitor structure, and the series capacitor structure and the capacitor C1 form a parallel capacitor structure. According to the formula of the series capacitance calculation, the capacitance of the series capacitance structure is equal to C2C 3C 4/(C2C 3+ C2C 4+ C3C 4), and the total capacitance between N1 and N2 is equal to C1+ C2C 3C 4/(C2C 3+ C2C 4+ C3C 4). Since C2 × C3 × C4/(C2 × C3+ C2 × C4+ C3 × C4) is much smaller than C2, the semiconductor structure can detect a more accurate value of C1 through the first probe pad 5. It should be noted that the substrate 1 is generally grounded, and the semiconductor substrate 11 surrounded by the doped well 2 and the ring-shaped doped portion 6 is not grounded, i.e., the substrate 11 is in a floating state.
In the exemplary embodiment, other dielectric layers may be disposed on the dielectric layer 12, and the probe pad 04 should include a probe portion on the uppermost dielectric layer, in which case, a probe portion may be disposed on each dielectric layer and electrically connected through a via on the dielectric layer, and the probe portion may be a metal layer.
In the present exemplary embodiment, one method for forming the doped well 2 may be to provide a mask having an annular hollow area, and perform ion implantation on the semiconductor substrate using the mask to form the deep doped well. As shown in fig. 3, when the ion implantation is performed, a ring-shaped doped portion 6 is formed on the semiconductor substrate 1, and the ring-shaped doped portion 6 has the same doping type as that of the deep doped well 2. The first annular opening of the annular doped part 6 is connected with the deep doped well 2, and the second annular opening of the annular doped part 6 is located on the surface of the semiconductor substrate 1, so that the semiconductor substrate part 11 is isolated from other parts of the semiconductor substrate 1 through the doped well 2 and the annular doped part 6. When the semiconductor substrate 1 is connected to the ground terminal, the semiconductor substrate portion 11 is in a floating state.
In the present exemplary embodiment, as shown in fig. 3, the area of the doping well 2 may be equal to or greater than the area of the first probe pad 5. This arrangement can reduce the capacitance formed between the first probe pad 5 and the semiconductor substrate 1 in parallel with the capacitance C1.
In this exemplary embodiment, as shown in fig. 3 and 5, the semiconductor structure may further include a second probe pad 7, the second probe pad 7 is disposed on a side of the dielectric layer 12 facing away from the semiconductor substrate 1, and the second probe pad 7 may be connected to the semiconductor substrate 1 through a via hole on the dielectric layer 12. Wherein the second probe pad 7 can be connected to the semiconductor substrate 1 except the semiconductor substrate portion 11 to serve as an isoelectric point of the semiconductor substrate. When testing the MOS capacitor C1 from the gate 4 to the substrate 1, the second probe pad 7 is grounded and the first probe pad 5 is a test point.
In the present exemplary embodiment, as shown in fig. 3 and 5, the semiconductor structure further includes: two anisotropically doped portions 91, 92, source/drain layers. Two opposite doped parts 91 and 92 are arranged in the semiconductor substrate 1, and orthographic projections of the two opposite doped parts 91 and 92 on the semiconductor substrate are positioned on two opposite sides of the orthographic projection of the gate 4 on the semiconductor substrate; the source/drain layer comprises a first source/drain portion 81 and a second source/drain portion 82, which are disposed on a side of the dielectric layer 12 away from the semiconductor substrate, and the first source/drain portion 81 is connected to one of the heterodoping portions 91 through a via hole in the dielectric layer, and the second source/drain portion 82 is connected to the other of the heterodoping portions 92 through another via hole in the dielectric layer. The heterodoping 91, 92 is of opposite doping type to the semiconductor substrate 1.
In the present exemplary embodiment, the semiconductor substrate 1 may be an N-type semiconductor, and accordingly, the deep doped well 2 and the ring-shaped doped portion 6 are P-type wells. Furthermore, the semiconductor substrate 1 may be a P-type semiconductor, and accordingly, the deep doped well 2 and the ring-shaped doped portion 6 are N-type wells.
In the present exemplary embodiment, the first probe pad 5 and the second probe pad 7 may be metal probe pads, and the first probe pad 5, the second probe pad 7 and the gate 4 may be formed by a one-step patterning process.
The present exemplary embodiment further provides a method for fabricating a semiconductor structure, as shown in fig. 6, which is a flowchart of an exemplary embodiment of the method for fabricating a semiconductor structure according to the present disclosure. The method comprises the following steps:
step S61: providing a semiconductor substrate;
step S62: forming a deep doped well in the semiconductor substrate, wherein the deep doped well is wrapped in the semiconductor substrate, so that two opposite side surfaces of the deep doped well in the stacking direction respectively form PN junctions with the semiconductor substrate, and the semiconductor substrate has different doping types;
step S63: forming an annular doping part in the semiconductor substrate, wherein the annular doping part and the deep doping well have the same doping type, a first annular opening of the annular doping part is connected with the deep doping well, and a second annular opening of the annular doping part is located on the surface of the semiconductor substrate;
the semiconductor substrate is located at the position surrounded by the annular doping part and is in a floating state;
step S64: forming a gate insulating layer on the semiconductor substrate;
step S65: forming a gate on one side of the gate insulating layer, which faces away from the semiconductor substrate, wherein the orthographic projection of the gate on the semiconductor substrate is positioned outside the deep doped well;
step S66: forming a dielectric layer on the semiconductor substrate;
step S67: forming a first probe pad on one side of the dielectric layer, which faces away from the semiconductor substrate, wherein the orthographic projection of the first probe pad on the semiconductor substrate is positioned in the deep doping well;
step S68: forming a wire to connect the first probe pad and the gate.
The above steps are explained in detail below:
referring to fig. 3, step S61 may include: a semiconductor substrate 1 is provided, wherein the semiconductor substrate 1 may be an N-type semiconductor substrate or a P-type semiconductor substrate. Step S62 may include forming a deep doped well 2 in the semiconductor substrate 1, where the deep doped well 2 is wrapped in the semiconductor substrate 1, so that two opposite sides of the deep doped well 2 in the stacking direction respectively form PN junctions with the semiconductor substrate 1. Step S63 may include forming a ring-shaped doped portion 6 in the semiconductor substrate 1, the ring-shaped doped portion 6 and the deep doped well 2 having the same doping type, wherein a first ring-shaped opening of the ring-shaped doped portion 6 is connected to the deep doped well 2, and a second ring-shaped opening of the ring-shaped doped portion 6 is located on the surface of the semiconductor substrate 1. Step S64 may include forming a gate insulating layer 3 on the semiconductor substrate 1, wherein the gate insulating layer 3 may be formed by a patterning process, for example, a gate insulating material layer may be formed on the semiconductor substrate 1, a photoresist layer may be formed on the gate insulating material layer, and the gate insulating material layer may be formed into the gate insulating layer by an exposure, development, and etching process. Step S65 may include: a gate 4 is formed on the side of the gate insulating layer 3 facing away from the semiconductor substrate 1, wherein the gate 4 can likewise be formed by a patterning process. Step S56 may include forming a dielectric layer 12 on the semiconductor substrate 1, where the dielectric layer 12 may be formed on the semiconductor substrate through a coating process, and the dielectric layer 12 may cover the gate 4. Step S67 may include forming first probe pads 5 on a side of the dielectric layer 12 facing away from the semiconductor substrate 1. Step S68 may include forming conductive lines 13 to connect the first probe pads 5 and the gates 4.
In the present exemplary embodiment, one method for forming the doped well 2 may be to provide a mask having an annular hollow area, and perform ion implantation on the semiconductor substrate 1 by using the mask to form the deep doped well 2. As shown in fig. 3, when the ion implantation is performed, a ring-shaped doped portion 6 is formed on the semiconductor substrate 1, and the ring-shaped doped portion 6 has the same doping type as that of the deep doped well 2. The first annular opening of the annular doped part 6 is connected with the deep doped well 2, and the second annular opening of the annular doped part 6 is located on the surface of the semiconductor substrate 1, so that the semiconductor substrate part 11 is isolated from other parts of the semiconductor substrate 1 through the doped well 2 and the annular doped part 6. When the semiconductor substrate 1 is connected to the ground terminal, the semiconductor substrate portion 11 is in a floating state.
The present exemplary embodiment further provides a method for detecting capacitance of a semiconductor structure, which is used for detecting the above-mentioned semiconductor structure, and as shown in fig. 7, is a flowchart of an exemplary embodiment of the method for detecting capacitance of a semiconductor structure according to the present disclosure. The method comprises the following steps:
step S71: inputting constant current to the first probe pad by using a constant current source;
step S72: detecting the change state of the voltage on the first probe pad along with time in real time;
step S73: and acquiring the capacitance of the capacitance structure according to the change state of the voltage on the first probe pad along with time.
In the present exemplary embodiment, acquiring the capacitance of the capacitive structure according to a variation state of the voltage on the first probe pad with time may include:
the capacitance is calculated according to the formula C ═ It/V, where I is the output current value of the constant current source, t is time, and V is a voltage value corresponding to time.
For example, the constant current source may be used to input a constant current I to the first probe pad 5 in fig. 3, so as to monitor the voltage on the first probe pad 5 in real time, as shown in fig. 8, which is a state diagram of the voltage on the first probe pad with time in an exemplary embodiment of the method for detecting the capacitance of the semiconductor structure according to the present disclosure. Wherein the abscissa is time in seconds and the ordinate is voltage in volts. From fig. 7, the voltage V1 at time t1 can be derived, so that the capacitance can be calculated from C ═ It1/V1, where I is the output current value of the constant current source.
In addition, the exemplary embodiment can also directly detect the capacitance between the first probe pad and the second probe pad through the capacitance detection device, thereby obtaining the MOS capacitance between the gate and the semiconductor substrate.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is to be limited only by the terms of the appended claims.
Claims (5)
1. A semiconductor structure, comprising:
a semiconductor substrate;
the deep doping well has a doping type different from that of the semiconductor substrate and is wrapped in the semiconductor substrate so that two opposite side surfaces of the deep doping well in the stacking direction respectively form PN junctions with the semiconductor substrate;
the annular doping part and the deep doping well have the same doping type and are formed in the semiconductor substrate, wherein a first annular opening of the annular doping part is connected with the deep doping well, and a second annular opening of the annular doping part is located on the surface of the semiconductor substrate;
the semiconductor substrate is located at the position surrounded by the annular doping part and is in a floating state;
a gate insulating layer disposed on the semiconductor substrate;
the grid electrode is arranged on one side, away from the semiconductor substrate, of the grid electrode insulating layer, and the orthographic projection of the grid electrode on the semiconductor substrate is located outside the deep doping well;
a dielectric layer disposed on the semiconductor substrate;
the first probe pad is arranged on one side, away from the semiconductor substrate, of the dielectric layer, and the orthographic projection of the first probe pad on the semiconductor substrate is located in the deep doping well;
and the lead is connected between the first probe pad and the grid electrode.
2. The semiconductor structure of claim 1, further comprising:
the two opposite doping parts are arranged in the semiconductor substrate and have opposite doping types to the semiconductor substrate, and orthographic projections of the two opposite doping parts on the semiconductor substrate are positioned on two opposite sides of the orthographic projection of the grid electrode on the semiconductor substrate;
and the source/drain layer comprises a first source/drain part and a second source/drain part, the first source/drain part and the second source/drain part are arranged on one side of the dielectric layer, which is far away from the semiconductor substrate, the first source/drain part is connected with one heterodoping part through a via hole on the dielectric layer, and the second source/drain part is connected with the other heterodoping part through another via hole on the dielectric layer.
3. The semiconductor structure of claim 1, further comprising:
and the second probe pad is arranged on one side of the dielectric layer, which is far away from the semiconductor substrate, and the second probe pad is connected with the semiconductor substrate through a through hole on the dielectric layer.
4. The semiconductor structure of claim 1, wherein an area of the deep doped well is equal to or greater than an area of the first probe pad.
5. The semiconductor structure of claim 1, wherein the doping type of the semiconductor substrate is P-type and the deep doped well is N-type.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112993004A (en) * | 2019-11-29 | 2021-06-18 | 长鑫存储技术有限公司 | Semiconductor structure, manufacturing method thereof and capacitance detection method |
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| CN112993004A (en) * | 2019-11-29 | 2021-06-18 | 长鑫存储技术有限公司 | Semiconductor structure, manufacturing method thereof and capacitance detection method |
| CN112993004B (en) * | 2019-11-29 | 2024-06-07 | 长鑫存储技术有限公司 | Semiconductor structure, manufacturing method thereof and capacitance detection method |
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