US6693834B1 - Device and method for detecting alignment of bit lines and bit line contacts in DRAM devices - Google Patents
Device and method for detecting alignment of bit lines and bit line contacts in DRAM devices Download PDFInfo
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- US6693834B1 US6693834B1 US10/448,727 US44872703A US6693834B1 US 6693834 B1 US6693834 B1 US 6693834B1 US 44872703 A US44872703 A US 44872703A US 6693834 B1 US6693834 B1 US 6693834B1
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- 238000000034 method Methods 0.000 title claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 230000002159 abnormal effect Effects 0.000 claims 2
- 238000001514 detection method Methods 0.000 claims 2
- 239000003990 capacitor Substances 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70616—Monitoring the printed patterns
- G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70653—Metrology techniques
- G03F7/70658—Electrical testing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
Definitions
- the present invention relates to a test device, and in particular to a test device for detecting alignment of bit lines and bit line contacts in DRAM devices, as well as a test method thereof.
- FIG. 1 a is a layout of conventional deep trench capacitors in a memory device. Deep trench capacitors 10 are disposed under the passing word lines. Transistors 14 are electrically coupled to the storage nodes 16 of the capacitors 10 through the diffusion regions 18 . The diffusion regions 20 are connected to plugs 22 coupled to bit lines (not shown). The transistors 14 are driven by word lines 12 , and the channels under the word lines 12 are conductive when appropriate voltages are applied to the word lines 12 . Consequently, the current produced between the diffusion regions 18 and 20 may flow into or out of the storage nodes 16 .
- FIG. 1 b is a cross-section of FIG. 1 a .
- trench isolations are formed in the substrate and deep trench capacitors 10 to define active areas.
- the word lines 12 are then formed on the substrate, the diffusion regions 18 and 20 are formed in the active areas by word lines 12 during the implant process, and the diffusion regions 18 and 20 are located on both sides of the word lines 12 .
- the plugs 22 are formed on the diffusions 20 .
- the adjacent memory cells may experience current leakage and cell failure, reducing process yield, if bit line masks and contacts are not aligned accurately.
- the process yield and reliability of the memory cells can be improved if alignment inaccuracy between the masks of active areas and the deep trench capacitors is controlled within an acceptable range.
- an object of the invention is to detect alignment of bit lines and bit line contacts in DRAM devices.
- the present invention provides a test device for detecting alignment of bit lines and bit line contacts in DRAM devices.
- an active area is disposed in the scribe line area.
- Parallel first and second bar-type bit line contacts are disposed in the active area.
- the first and second bar-type bit line contacts are shorter than the active area, and each bar-type line contact has an outside surface and two terminals.
- First and second bit lines are disposed in the active area, the first bar-type bit line contact is covered by the first bit line with a first outside surface aligned with the outside surface of the first bar-type contact.
- the second bar-type bit line contact is covered by the second bit line with a second outside surface aligned with the outside surface of the second bar-type contact.
- First and second plugs are disposed on the two terminals of the first bit line respectively.
- Third and fourth plugs are disposed on the two terminals of the second bit line respectively.
- the present invention also provides a method for detecting alignment of bit lines and bit line contacts in DRAM devices.
- a wafer with at least one scribe line region and at least one memory region is provided.
- a plurality of memory cells in the memory region and at least one test device in the scribe line region are formed simultaneously, wherein the memory region has bit line contacts and bit lines.
- a first resistance is detected by the first plug and the second plug, and the second resistance is detected by the third plug and the fourth plug, respectively.
- Alignment of the bar-type bit line contacts and the bit lines of the test device is determined according to the first resistance and the second resistance.
- alignment of the bit line contacts and the bit lines is determined according to alignment of the bar-type bit line contacts and bit lines of the test device.
- FIGS. 1 a and 1 b are layouts of a conventional memory device with deep trench capacitors
- FIG. 2 is a layout of the test device according to the present invention.
- FIG. 3 is a cross section of FIG. 2 according to the present invention.
- FIG. 4 is a layout of the test device with alignment shift according to the present invention.
- FIG. 5 is a cross section of FIG. 4 .
- FIG. 2 is a layout of the test device according to the present invention
- FIG. 3 is a cross section of FIG. 2 .
- the test device detects whether the alignment of bit lines and bit line contacts in DRAM devices, wherein at least one test device is disposed a scribe line region 160 of a wafer 100 .
- An active area 181 is defined in the scribe line region of the wafer by trench isolation, wherein the active area 181 has a width about 2 micrometers and a length of about 300 micrometers.
- First and second bar-type bit line contacts 22 1 and 22 2 are parallel to each other and disposed in the active area 181 .
- the first and second bar-type bit line contacts 22 1 and 22 2 are shorter than the active area 181 .
- length L of the first and second bar-type bit line contacts 22 1 and 22 2 is about 290 micrometers and the width of the first and second bar-type bit line contacts 22 1 and 22 2 is about 0.2 micrometers.
- the first bar-type line contact 22 1 and the second bar-type contact 22 2 have outside surfaces S 221 and S 222 , respectively, are made of, for example, polysilicon.
- First and second bit lines are disposed in the active area 181 , wherein the first bar-type bit line contact 22 1 is covered by the first bit line 13 1 .
- the first bit line 13 1 has a first outside surface S 131 aligned with the outside surface S 221 of the first bar-type contact 22 1 .
- the second bar-type bit line contact 22 2 is covered by the second bit line S 132 .
- the second bit line 13 2 has a second outside surface S 132 aligned with the outside surface S 222 of the second bar-type contact 222 .
- Bit lines 13 1 and 13 2 are longer than bar-type bit line contacts 22 1 and 22 2 and the active area.
- the bit lines 13 1 and 13 2 may have length of about 310 micrometers and width (W 1 and W 2 ) of about 0.5 micrometers, and the bit lines 13 1 and 13 2 are made of tungsten.
- first and second plugs CS 1 and CS 2 are disposed on the two terminals of the first bit line 13 1 respectively and third and fourth plugs CS 3 and CS 4 are disposed on the two terminals of the second bit line 13 2 respectively.
- a first resistance R 1 can be determined by the first and second plugs CS 1 and CS 2
- a second resistance R 2 can be determined by the third and fourth plugs CS 3 and CS 4
- the first resistance R 1 and the second resistance R 2 can be presented by equations 1 and 2 respectively.
- R 1 R MO ⁇ L W 1 ( 1 )
- R 2 R MO ⁇ L W 2 ( 2 )
- Equations 3 and 4 are obtained according to the equations 1 and 2 respectively.
- W 1 R MO ⁇ L R 1 ( 3 )
- W 2 R MO ⁇ L R 2 ( 4 )
- the alignment shift ⁇ W between first and second bar-type bit line contacts ( 22 1 and 22 2 ) and the first and second bit lines ( 13 1 and 13 2 ) can be obtained if the first resistance R 1 and the second resistance R 2 are detected. That is to say, the alignment shift ⁇ W between first and second bar-type bit line contacts ( 22 1 and 22 2 ) and the first and second bit lines ( 13 1 and 13 2 ) when the first resistance R 1 equals the second resistance R 2 .
- the bit lines 13 1 and 13 2 are shifted by a distance ⁇ W along the direction X 1 if the masks of the bit lines ( 13 1 and 13 2 ) and the bar-type bit line contacts ( 22 1 and 22 2 ) have an alignment shift in the direction X 1 . If this condition is met, the second outside surface S 132 of the second bit line 13 2 may not align with the outside surface S 222 of the second bar-type bit line contact 22 2 . The second bar-type bit line contact 22 2 is not covered by the second bit line 13 2 completely, and the portion with width ⁇ W is exposed.
- the first bar-type bit line contact 22 2 is covered by the first bit line 13 1 completely, even though the first bit line 13 1 has been shifted by a distance ⁇ W.
- the equivalent width of the second bit line 13 2 is increased to W 2 + ⁇ W, but that of the first bit line 13 1 is still W 1 .
- Resistance is inversely proportional to the cross section of the conductor, and the cross section of the conductor can be regarded as a product of width and length of the conductor.
- the lengths of the bit lines 13 1 and 13 2 are equal, and the lengths of the bar-type bit line contacts 22 1 and 22 2 are equal.
- resistance is inversely proportional to equivalent width of conductor.
- the first resistance R 1 detected by the first and second plugs (CS 1 and CS 2 ) is larger than the second resistance R 2 detected by the third and fourth plugs (CS 3 and CS 4 ), and further, the alignment shift can be obtained by the equation 5.
- bit lines 13 1 and 13 2 are shifted by a distance ⁇ W along the direction X 2 (not shown in FIG. 4 and FIG. 5) if the masks of the bit lines ( 13 1 and 13 2 ) and the bar-type bit line contacts ( 22 1 and 22 2 ) have an alignment shift in the direction X 2 . If this condition is met, the first outside surface S 131 of the first bit line 13 1 may not align with the outside surface S 221 of the first bar-type bit line contact 22 1 . The first bar-type bit line contact 22 1 is not covered by the first bit line 13 1 completely, and the portion with width ⁇ W is exposed.
- the second bar-type bit line contact 22 1 is covered by the second bit line 13 2 completely, even though the second bit line 13 2 has been shifted by a distance W.
- the equivalent width of the first bit line 13 1 is increased to W 1 + ⁇ W, but that of the second bit line 13 2 is still W 2 .
- resistance is inversely proportional to equivalent width of conductor.
- the first resistance R 1 detected by the first and second plugs (CS 1 and CS 2 ) is smaller than the second resistance R 2 detected by the third and fourth plugs (CS 3 and CS 4 ), and the alignment shift ⁇ W can be obtained by the equation 5.
- the present invention also provides a method for detecting alignment of bit lines and bit line contacts in DRAM device.
- a wafer with at least one scribe line area and at least one memory region is provided (not shown).
- a plurality of memory cells in the memory region and at least one test device in the scribe line area are formed simultaneously, wherein the memory regions have bit lines and bit line contacts as shown in FIGS. 1 a and 1 b .
- the structure of the test device is shown in FIG. 2 and FIG. 3 .
- the bit line contacts in the memory regions and the bar-type bit line contacts in the test device are formed by the same mask and the same process.
- the bit lines in the memory regions and first and second bit lines in the test device are formed by the same mask and the same process.
- the first resistance R 1 is detected by the first plug CS 1 and the second plug CS 2 in the test device
- the second resistance R 2 is detected by the third plug CS 3 and the fourth plug CS 4 in the test device.
- Alignment of the bit lines ( 13 1 and 13 2 ) and the bar-type bit line contacts ( 22 1 and 22 2 ) of the test device is determined according to whether the first resistance R 1 is equal to the second resistance R 2 .
- the memory regions and the test device may have the same alignment shift between the bit line contacts and bit lines due to use of the same masks and the same process.
- alignment of bit lines and bit line contacts in memory regions can be obtained according to alignment of bar-type bit line contacts ( 22 1 and 22 2 ) and bit lines ( 13 1 and 13 2 ) of the test device.
- the alignment shift between bit lines and the bit line contacts in the memory regions can also be obtained according to the equation 5.
- the test device is disposed in the scribe line region and is formed by the same masks and process as the bit lines and bit line contacts in the memory regions simultaneously. Therefore, the test device disposed in the scribe line region can detect the alignment shift between the bit lines and bit line contacts in the memory regions because the test device and the memory regions may have the same alignment shift when masks are aligned. Further, in the present invention the test device is disposed in the scribe line region to avoid occupying layout space in memory regions.
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Abstract
A method and device for detecting alignment of bit lines and bit line contacts in DRAM devices. In the present invention, the test device is disposed in the scribe line region and is formed by the same masks and process as the bit lines and bit line contacts in the memory regions simultaneously. The memory deices and test may have the same alignment shift between bit line contacts and bit line due to use of the same masks and process. Thus, alignment of bit lines and bit line contacts in the memory region is determined according to two resistances (R1 and R2) detected by the test device. Further, the alignment shift can be obtained by
wherein RMO is the resistance per surface area of the bit lines, and L is the length of the bar-type bit line contacts in the test device.
Description
1. Field of the Invention
The present invention relates to a test device, and in particular to a test device for detecting alignment of bit lines and bit line contacts in DRAM devices, as well as a test method thereof.
2. Description of the Related Art
FIG. 1a is a layout of conventional deep trench capacitors in a memory device. Deep trench capacitors 10 are disposed under the passing word lines. Transistors 14 are electrically coupled to the storage nodes 16 of the capacitors 10 through the diffusion regions 18. The diffusion regions 20 are connected to plugs 22 coupled to bit lines (not shown). The transistors 14 are driven by word lines 12, and the channels under the word lines 12 are conductive when appropriate voltages are applied to the word lines 12. Consequently, the current produced between the diffusion regions 18 and 20 may flow into or out of the storage nodes 16.
FIG. 1b is a cross-section of FIG. 1a. After the deep trench capacitors 10 are completely formed in the substrate, trench isolations are formed in the substrate and deep trench capacitors 10 to define active areas. The word lines 12 are then formed on the substrate, the diffusion regions 18 and 20 are formed in the active areas by word lines 12 during the implant process, and the diffusion regions 18 and 20 are located on both sides of the word lines 12. Finally, the plugs 22 are formed on the diffusions 20. The adjacent memory cells may experience current leakage and cell failure, reducing process yield, if bit line masks and contacts are not aligned accurately.
Therefore, the process yield and reliability of the memory cells can be improved if alignment inaccuracy between the masks of active areas and the deep trench capacitors is controlled within an acceptable range.
Accordingly, an object of the invention is to detect alignment of bit lines and bit line contacts in DRAM devices.
According to the above mentioned objects, the present invention provides a test device for detecting alignment of bit lines and bit line contacts in DRAM devices.
In the test device of the present invention, an active area is disposed in the scribe line area. Parallel first and second bar-type bit line contacts are disposed in the active area. The first and second bar-type bit line contacts are shorter than the active area, and each bar-type line contact has an outside surface and two terminals. First and second bit lines are disposed in the active area, the first bar-type bit line contact is covered by the first bit line with a first outside surface aligned with the outside surface of the first bar-type contact. The second bar-type bit line contact is covered by the second bit line with a second outside surface aligned with the outside surface of the second bar-type contact. First and second plugs are disposed on the two terminals of the first bit line respectively. Third and fourth plugs are disposed on the two terminals of the second bit line respectively.
According to the above mentioned objects, the present invention also provides a method for detecting alignment of bit lines and bit line contacts in DRAM devices.
In the method of the present invention, a wafer with at least one scribe line region and at least one memory region is provided. A plurality of memory cells in the memory region and at least one test device in the scribe line region are formed simultaneously, wherein the memory region has bit line contacts and bit lines. A first resistance is detected by the first plug and the second plug, and the second resistance is detected by the third plug and the fourth plug, respectively. Alignment of the bar-type bit line contacts and the bit lines of the test device is determined according to the first resistance and the second resistance. Finally, alignment of the bit line contacts and the bit lines is determined according to alignment of the bar-type bit line contacts and bit lines of the test device.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
FIGS. 1a and 1 b are layouts of a conventional memory device with deep trench capacitors;
FIG. 2 is a layout of the test device according to the present invention;
FIG. 3 is a cross section of FIG. 2 according to the present invention; and
FIG. 4 is a layout of the test device with alignment shift according to the present invention; and
FIG. 5 is a cross section of FIG. 4.
FIG. 2 is a layout of the test device according to the present invention, and FIG. 3 is a cross section of FIG. 2. The test device detects whether the alignment of bit lines and bit line contacts in DRAM devices, wherein at least one test device is disposed a scribe line region 160 of a wafer 100.
An active area 181 is defined in the scribe line region of the wafer by trench isolation, wherein the active area 181 has a width about 2 micrometers and a length of about 300 micrometers.
First and second bar-type bit line contacts 22 1 and 22 2 are parallel to each other and disposed in the active area 181. The first and second bar-type bit line contacts 22 1 and 22 2 are shorter than the active area 181. In this case, length L of the first and second bar-type bit line contacts 22 1 and 22 2 is about 290 micrometers and the width of the first and second bar-type bit line contacts 22 1 and 22 2 is about 0.2 micrometers. In addition, the first bar-type line contact 22 1 and the second bar-type contact 22 2 have outside surfaces S221 and S222, respectively, are made of, for example, polysilicon.
First and second bit lines are disposed in the active area 181, wherein the first bar-type bit line contact 22 1 is covered by the first bit line 13 1. The first bit line 13 1 has a first outside surface S131 aligned with the outside surface S221 of the first bar-type contact 22 1. The second bar-type bit line contact 22 2 is covered by the second bit line S132. The second bit line 13 2 has a second outside surface S132 aligned with the outside surface S222 of the second bar-type contact 222. Bit lines 13 1 and 13 2 are longer than bar-type bit line contacts 22 1 and 22 2 and the active area. For example, the bit lines 13 1 and 13 2 may have length of about 310 micrometers and width (W1 and W2) of about 0.5 micrometers, and the bit lines 13 1 and 13 2 are made of tungsten.
In addition, first and second plugs CS1 and CS2 are disposed on the two terminals of the first bit line 13 1 respectively and third and fourth plugs CS3 and CS4 are disposed on the two terminals of the second bit line 13 2 respectively.
Usually, a first resistance R1 can be determined by the first and second plugs CS1 and CS2, and a second resistance R2 can be determined by the third and fourth plugs CS3 and CS4. The first resistance R1 and the second resistance R2 can be presented by equations 1 and 2 respectively.
Because the first bit line 13 1 and second bit line 13 2 are formed in the same process with the same conditions and parameters, the resistances per surface area of the first and second bit lines 13 1 and 13 2 are both RMO. Also, the lengths of the first and second bar-type bit line contacts 22 1 and 22 2 are both L. Equation 5 is obtained by substituting equations 3 and 4.
Therefore, the alignment shift ΔW between first and second bar-type bit line contacts (22 1 and 22 2) and the first and second bit lines (13 1 and 13 2) can be obtained if the first resistance R1 and the second resistance R2 are detected. That is to say, the alignment shift ΔW between first and second bar-type bit line contacts (22 1 and 22 2) and the first and second bit lines (13 1 and 13 2) when the first resistance R1 equals the second resistance R2.
For example, with reference to FIG. 4 and FIG. 5, the bit lines 13 1 and 13 2 are shifted by a distance ΔW along the direction X1 if the masks of the bit lines (13 1 and 13 2) and the bar-type bit line contacts (22 1 and 22 2) have an alignment shift in the direction X1. If this condition is met, the second outside surface S132 of the second bit line 13 2 may not align with the outside surface S222 of the second bar-type bit line contact 22 2. The second bar-type bit line contact 22 2 is not covered by the second bit line 13 2 completely, and the portion with width ΔW is exposed. The first bar-type bit line contact 22 2 is covered by the first bit line 13 1 completely, even though the first bit line 13 1 has been shifted by a distance ΔW. Thus, the equivalent width of the second bit line 13 2 is increased to W2+ΔW, but that of the first bit line 13 1 is still W1. Resistance is inversely proportional to the cross section of the conductor, and the cross section of the conductor can be regarded as a product of width and length of the conductor. In the present invention, the lengths of the bit lines 13 1 and 13 2 are equal, and the lengths of the bar-type bit line contacts 22 1 and 22 2 are equal. Thus, in the present invention, resistance is inversely proportional to equivalent width of conductor. In this condition, the first resistance R1 detected by the first and second plugs (CS1 and CS2) is larger than the second resistance R2 detected by the third and fourth plugs (CS3 and CS4), and further, the alignment shift can be obtained by the equation 5.
On the contrary, the bit lines 13 1 and 13 2 are shifted by a distance ΔW along the direction X2 (not shown in FIG. 4 and FIG. 5) if the masks of the bit lines (13 1 and 13 2) and the bar-type bit line contacts (22 1 and 22 2) have an alignment shift in the direction X2. If this condition is met, the first outside surface S131 of the first bit line 13 1 may not align with the outside surface S221 of the first bar-type bit line contact 22 1. The first bar-type bit line contact 22 1 is not covered by the first bit line 13 1 completely, and the portion with width ΔW is exposed. The second bar-type bit line contact 22 1 is covered by the second bit line 13 2 completely, even though the second bit line 13 2 has been shifted by a distance W. Thus, the equivalent width of the first bit line 13 1 is increased to W1+ΔW, but that of the second bit line 13 2 is still W2. In the present invention, resistance is inversely proportional to equivalent width of conductor. Thus, in this condition, the first resistance R1 detected by the first and second plugs (CS1 and CS2) is smaller than the second resistance R2 detected by the third and fourth plugs (CS3 and CS4), and the alignment shift ΔW can be obtained by the equation 5.
The present invention also provides a method for detecting alignment of bit lines and bit line contacts in DRAM device. In the method of the present invention, a wafer with at least one scribe line area and at least one memory region is provided (not shown).
A plurality of memory cells in the memory region and at least one test device in the scribe line area are formed simultaneously, wherein the memory regions have bit lines and bit line contacts as shown in FIGS. 1a and 1 b. The structure of the test device is shown in FIG. 2 and FIG. 3. The bit line contacts in the memory regions and the bar-type bit line contacts in the test device are formed by the same mask and the same process. The bit lines in the memory regions and first and second bit lines in the test device are formed by the same mask and the same process.
After that, the first resistance R1 is detected by the first plug CS1 and the second plug CS2 in the test device, and the second resistance R2 is detected by the third plug CS3 and the fourth plug CS4 in the test device. Alignment of the bit lines (13 1 and 13 2) and the bar-type bit line contacts (22 1 and 22 2) of the test device is determined according to whether the first resistance R1 is equal to the second resistance R2.
The memory regions and the test device may have the same alignment shift between the bit line contacts and bit lines due to use of the same masks and the same process. Thus, alignment of bit lines and bit line contacts in memory regions can be obtained according to alignment of bar-type bit line contacts (22 1 and 22 2) and bit lines (13 1 and 13 2) of the test device. The alignment shift between bit lines and the bit line contacts in the memory regions can also be obtained according to the equation 5.
In the present invention, the test device is disposed in the scribe line region and is formed by the same masks and process as the bit lines and bit line contacts in the memory regions simultaneously. Therefore, the test device disposed in the scribe line region can detect the alignment shift between the bit lines and bit line contacts in the memory regions because the test device and the memory regions may have the same alignment shift when masks are aligned. Further, in the present invention the test device is disposed in the scribe line region to avoid occupying layout space in memory regions.
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Claims (15)
1. A test device for detecting alignment of bit lines and bit line contacts in DRAM devices, wherein the test device is disposed in a scribe line region of a wafer, comprising:
an active area disposed in the scribe line area;
parallel first and second bar-type bit line contacts, disposed in the active area, wherein the first and second bar-type bit line contacts are shorter than the active area, and each bar-type line contact has an outside surface and two terminals;
first and second bit lines disposed in the active area, wherein the first bar-type bit line contact is covered by the first bit line with a first outside surface aligned with the outside surface of the first bar-type contact, and the second bar-type bit line contact is covered by the second bit line with a second outside surface aligned with the outside surface of the second bar-type contact;
first and second plugs disposed on the two terminals of the first bit line respectively; and
third and fourth plugs disposed on the two terminals of the second bit line respectively.
2. The test device as claimed in claim 1 , wherein a first resistance is detected by the first and second plugs, and a second resistance is detected by the third and fourth plugs.
3. The test device as claimed in claim 1 , wherein the first bar-type bit line contact and second bar-type bit line contact have the same width.
4. The test device as claimed in claim 1 , wherein the first and second bit lines have the same width and are longer than the widths of the first and second bar-type bit line contacts.
5. The test device as claimed in claim 1 , wherein the first and second bit lines are longer than the first bar-type bit line contact and the active area.
6. The test device as claimed in claim 2 , wherein the alignment of the bit line contact and the bar-type active area is abnormal when the first resistance is not equal to the second resistance.
7. The test device as claimed in claim 1 , wherein the first and second bit lines are made of tungsten.
8. The test device as claimed in claim 1 , wherein the first and second bar-type bit line contacts are made of polysilicon.
9. A method for detecting alignment of bit lines and bit line contacts in DRAM devices, comprising:
providing a wafer with at least one scribe line and at least one memory region;
forming a plurality of memory cells in the memory region and at least one test device in the scribe line simultaneously, wherein the memory region has bit line contacts and bit lines, the test device including:
an active area disposed in the scribe line area;
parallel first and second bar-type bit line contacts, disposed in the active area, wherein the first and second bar-type bit line contacts are shorter than the active area, and each bar-type line contact has an outside surface and two terminals;
first and second bit lines disposed in the active area, wherein the first bar-type bit line contact is covered by the first bit line with a first outside surface aligned with the outside surface of the first bar-type contact, and the second bar-type bit line contact is covered by the second bit line with a second outside surface aligned with the outside surface of the second bar-type contact;
first and second plugs disposed on the two terminals of the first bit line respectively; and
third and fourth plugs disposed on the two terminals of the second bit line respectively;
detection of a first resistance by the first and second plugs;
detection of a second resistance by the third and fourth plugs;
determining alignment of the first and second bit lines and the first and second bar-type bit line contacts of the test device according to the first resistance and the second resistance; and
determining alignment of the bit line contacts and the bit lines in the memory regions according to alignment of the bar-type bit line contacts and bit lines of the test device.
10. The method as claimed in claim 9 , wherein the first bar-type bit line contact and second bar-type bit line contact have the same width.
11. The method as claimed in claim 9 , wherein the first and second bit lines have the same width and are longer than the width of the first and second bar-type bit line contacts.
12. The method as claimed in claim 9 , wherein the first and second bit lines are longer than the first bar-type bit line contact and the active area, and the first and second bit lines have the same resistance per surface area.
13. The method as claimed in claim 9 , wherein the alignment of the bit line contact and the bar-type active area is determined to be abnormal when the first resistance is not equal to the second resistance.
14. The method as claimed in claim 12 , further comprising a step of determining alignment shift of the bit line contacts and the bit lines according to the first resistance, the second resistance, the length of the first and second bar-type bit line contacts and the resistance per surface area of the first and second bit lines.
15. The method as claimed in claim 14 , wherein the alignment shift (ΔW) is determined by an equation:
wherein RMO is the resistance per surface area of the first and second bit lines, L is the length of the first and second bar-type bit line contacts, R1 is the first resistance, and R2 is the second resistance.
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TW091119511A TWI305648B (en) | 2002-08-28 | 2002-08-28 | Test key and test method for detecting whether the overlay of bit line and bit line contact of dram is normal |
TW91119511A | 2002-08-28 |
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US20040029301A1 (en) * | 2002-08-09 | 2004-02-12 | Nanya Technology Corporation | Method and device for detecting whether the alignment of bit line contacts and active areas in DRAM devices is normal |
US20040033634A1 (en) * | 2002-08-19 | 2004-02-19 | Nanya Technology Corporation | Device and method for detecting alignment of deep trench capacitors and active areas in DRAM devices |
US20040076056A1 (en) * | 2002-10-22 | 2004-04-22 | Nanya Technology Corporation | Device and method for detecting alignment of deep trench capacitors and word lines in DRAM devices |
US6905897B1 (en) * | 2003-12-10 | 2005-06-14 | Nanya Technology Corp. | Wafer acceptance testing method and structure of a test key used in the method |
CN113093482A (en) * | 2021-03-29 | 2021-07-09 | 长鑫存储技术有限公司 | Alignment error testing method, alignment error adjusting method, alignment error testing system and storage medium |
US20220310460A1 (en) * | 2021-03-29 | 2022-09-29 | Changxin Memory Technologies, Inc. | Test method, adjustment method, test system, and storage medium for alignment error |
US11521976B1 (en) * | 2021-09-03 | 2022-12-06 | Nanya Technology Corporation | Semiconductor device with bit line contact and method for fabricating the same |
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US20040029301A1 (en) * | 2002-08-09 | 2004-02-12 | Nanya Technology Corporation | Method and device for detecting whether the alignment of bit line contacts and active areas in DRAM devices is normal |
US6844207B2 (en) * | 2002-08-09 | 2005-01-18 | Nanya Technology Corporation | Method and device for detecting whether the alignment of bit line contacts and active areas in DRAM devices is normal |
US20040033634A1 (en) * | 2002-08-19 | 2004-02-19 | Nanya Technology Corporation | Device and method for detecting alignment of deep trench capacitors and active areas in DRAM devices |
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US6905897B1 (en) * | 2003-12-10 | 2005-06-14 | Nanya Technology Corp. | Wafer acceptance testing method and structure of a test key used in the method |
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CN113093482A (en) * | 2021-03-29 | 2021-07-09 | 长鑫存储技术有限公司 | Alignment error testing method, alignment error adjusting method, alignment error testing system and storage medium |
CN113093482B (en) * | 2021-03-29 | 2022-07-22 | 长鑫存储技术有限公司 | Alignment error testing method, alignment error adjusting method, alignment error testing system and storage medium |
US20220310460A1 (en) * | 2021-03-29 | 2022-09-29 | Changxin Memory Technologies, Inc. | Test method, adjustment method, test system, and storage medium for alignment error |
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