CN114783500A - Electrical test method and test structure of semiconductor device - Google Patents

Electrical test method and test structure of semiconductor device Download PDF

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Publication number
CN114783500A
CN114783500A CN202210398929.9A CN202210398929A CN114783500A CN 114783500 A CN114783500 A CN 114783500A CN 202210398929 A CN202210398929 A CN 202210398929A CN 114783500 A CN114783500 A CN 114783500A
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China
Prior art keywords
conductive structure
word line
conductive
contact hole
leakage current
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Chinese (zh)
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白新
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202210398929.9A priority Critical patent/CN114783500A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1202—Word line control

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Abstract

The disclosure relates to the technical field of semiconductors, and relates to an electrical test method and a test structure of a semiconductor device, wherein the test method comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises an array area and a body leading-out area, the array area comprises a plurality of word lines which are distributed at intervals, and conductive contact plugs and bit lines are respectively distributed on two sides of each word line; respectively forming a leading-out bit line, a conductive contact plug, a body leading-out area, any word line and a conductive structure of the word lines adjacent to the two sides of the word line; and applying voltage to each conductive structure to complete the electrical test. The testing method disclosed by the invention can reduce the deviation of the testing result and improve the testing accuracy.

Description

Electrical test method and test structure of semiconductor device
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to an electrical test method and a test structure for a semiconductor device.
Background
Dynamic Random Access Memory (DRAM) has the advantages of small size, high integration degree, high transmission speed, and the like, and is widely used in mobile devices such as mobile phones and tablet computers. The word line is used as a core component of the dynamic random access memory and is mainly used for transmitting a level signal to the transistor. The signal transmission effect of the transistor is directly affected by the quality of the electrical performance of the word line, so that it is very important to perform electrical performance test on the word line. However, the existing test method has large deviation of test results and low accuracy.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The present disclosure is directed to overcome the above-mentioned deficiencies in the prior art, and provides a method and a structure for testing electrical properties of a semiconductor device, which can reduce the deviation of the test result and improve the test accuracy.
According to an aspect of the present disclosure, there is provided an electrical test method of a semiconductor device, including:
providing a semiconductor structure, wherein the semiconductor structure comprises an array area and a body leading-out area, the array area comprises a plurality of word lines distributed at intervals, and conductive contact plugs and bit lines are distributed on two sides of each word line respectively;
respectively forming a conductive structure for leading out the bit line, the conductive contact plug, the body leading-out region, any word line and word lines adjacent to two sides of the word line;
and applying voltage to each conductive structure respectively to complete the electrical test.
In an exemplary embodiment of the present disclosure, any one of the word lines is defined as a target word line, and the word lines adjacent to both sides of the target word line are respectively defined as a first word line and a second word line; the conductive structure corresponding to the target word line is a first conductive structure, the conductive structure corresponding to the first word line is a second conductive structure, the conductive structure corresponding to the second word line is a third conductive structure, the conductive structure corresponding to the conductive contact plug is a fourth conductive structure, the conductive structure corresponding to the bit line is a fifth conductive structure, and the conductive structure corresponding to the body leading-out region is a sixth conductive structure;
the test method further comprises the following steps:
detecting a first leakage current between the target word line and the first word line;
detecting a second leakage current between the target word line and the second word line;
and when the magnitude of the first leakage current and the magnitude of the second leakage current are smaller than or equal to a first magnitude, applying voltages to the first conductive structure, the second conductive structure, the third conductive structure, the fourth conductive structure, the fifth conductive structure and the sixth conductive structure respectively to finish the electrical property test.
In an exemplary embodiment of the present disclosure, the detecting a first leakage current between the target word line and the first word line includes:
applying a first preset voltage to the first conductive structure and applying a second preset voltage to the second conductive structure;
a first leakage current is detected between the first conductive structure and the second conductive structure.
In an exemplary embodiment of the present disclosure, the detecting a second leakage current between the target word line and the second word line includes:
applying a first preset voltage to the first conductive structure and applying a third preset voltage to the third conductive structure;
detecting a second leakage current between the first conductive structure and the third conductive structure.
In an exemplary embodiment of the present disclosure, the first preset voltage ranges from-2V to 2V, and the second preset voltage and the third preset voltage are both 0V.
In an exemplary embodiment of the disclosure, the word lines are equally spaced, and the second conductive structure is spaced from the third conductive structure by a distance greater than a distance between two adjacent word lines.
In an exemplary embodiment of the present disclosure, the forming of the conductive structures for leading out the bit line, the conductive contact plug, the body leading-out region, any one of the word lines, and the word lines adjacent to both sides of the word line, respectively, includes:
forming a first contact hole exposing the target word line, a second contact hole exposing the first word line, a third contact hole exposing the second word line, a fourth contact hole exposing the conductive contact plug and a fifth contact hole exposing the bit line in the array area;
filling conductive materials in the first contact hole, the second contact hole, the third contact hole, the fourth contact hole and the fifth contact hole respectively so as to form a first conductive structure in the first contact hole, a second conductive structure in the second contact hole, a third conductive structure in the third contact hole, a fourth conductive structure in the fourth contact hole and a fifth conductive structure in the fifth contact hole;
forming a sixth contact hole exposing the conductive circuit of the body lead-out area in the body lead-out area;
and filling a conductive material in the sixth contact hole to form a sixth conductive structure.
In one exemplary embodiment of the present disclosure, the conductive material is tungsten.
In an exemplary embodiment of the present disclosure, the test method further includes:
detecting transfer currents of the first word line and the second word line, respectively;
detecting the corresponding saturation current when the conductive contact plug works in a saturation region;
controlling the voltage of the first word line and the voltage of the second word line to be 0V, and detecting the corresponding working current value on the conductive contact plug;
and when the magnitude of the transfer current and the magnitude of the saturation current are both larger than or equal to a second magnitude and the magnitude of the working current is smaller than or equal to a third magnitude, applying voltages to the first conductive structure, the second conductive structure, the third conductive structure, the fourth conductive structure, the fifth conductive structure and the sixth conductive structure respectively to finish an electrical test.
In an exemplary embodiment of the present disclosure, the test method further includes:
and when at least one of the first leakage current and the second leakage current is larger than the first order of magnitude, reselecting the target word line, the first word line and the second word line until the detected first leakage current and second leakage current are smaller than or equal to the first order of magnitude.
In an exemplary embodiment of the present disclosure, the first order of magnitude is 10-15A。
In an exemplary embodiment of the present disclosure, the second order of magnitude is 10-6A, the third order of magnitude being 10-15A。
According to an aspect of the present disclosure, there is provided an electrical test structure of a semiconductor device, including:
the semiconductor structure comprises an array area and a body leading-out area, wherein the array area comprises a plurality of word lines distributed at intervals, and conductive contact plugs and bit lines are distributed on two sides of each word line respectively;
the bit lines, the conductive contact plugs, the body leading-out regions, any word line and word lines adjacent to the two sides of the word lines are all connected with one conductive structure in a one-to-one correspondence mode.
In an exemplary embodiment of the present disclosure, any one of the word lines is defined as a target word line, and the word lines adjacent to both sides of the target word line are respectively defined as a first word line and a second word line; the conductive structure corresponding to the target word line is a first conductive structure, the conductive structure corresponding to the first word line is a second conductive structure, the conductive structure corresponding to the second word line is a third conductive structure, the conductive structure corresponding to the conductive contact plug is a fourth conductive structure, the conductive structure corresponding to the bit line is a fifth conductive structure, and the conductive structure corresponding to the body lead-out area is a sixth conductive structure; the first conductive structure, the second conductive structure, the third conductive structure, the fourth conductive structure, the fifth conductive structure and the sixth conductive structure are all made of tungsten.
In an exemplary embodiment of the disclosure, the word lines are equally spaced, and the second conductive structure is spaced from the third conductive structure by a distance greater than a distance between two adjacent word lines.
According to the electrical property test method and the test structure of the semiconductor device, the bit line, the body lead-out area, the conductive contact plug and each word line can be electrically led out through the conductive structure, and the electrical property test can be completed by applying voltage to each conductive structure. In the process, other word lines on two sides of the word line to be tested can be tested simultaneously, and further, the influence of other word lines around the word line to be tested is taken into consideration, so that the deviation of the test result can be reduced, and the test accuracy is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
FIG. 1 is a flow chart of a method for electrical testing of a semiconductor device according to one embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a semiconductor device in an embodiment of the present disclosure;
FIG. 3 is a micro-topography of a semiconductor device in an embodiment of the present disclosure;
fig. 4 is a flowchart of step S120 in the embodiment of the present disclosure;
FIG. 5 is a flow chart of a method for electrical testing of a semiconductor device in accordance with another embodiment of the present disclosure;
fig. 6 is a flowchart of an electrical testing method of a semiconductor device according to another embodiment of the present disclosure.
Description of reference numerals:
100. a substrate; 11. an array region; 12. a body exit region; 101. a source electrode; 102. a drain electrode; 200. a target word line; 210. a first word line; 220. a second word line; 300. a bit line; 400. a conductive contact plug; 510. a first conductive structure; 520. a second conductive structure; 530. a third conductive structure; 540. a fourth conductive structure; 550. a fifth conductive structure; 560. a sixth conductive structure; 600. a storage capacitor.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. The same reference numerals in the drawings denote the same or similar structures, and thus a detailed description thereof will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
Although relative terms, such as "upper" and "lower," may be used herein to describe one element of an icon relative to another, such terms are used herein for convenience only, e.g., with reference to the orientation of the example illustrated in the drawings. It will be understood that if the illustrated device is turned upside down, elements described as "upper" will be those that are "lower". When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements/components/parts/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first", "second", "third", "fourth", "fifth" and "sixth", etc. are used merely as labels, and are not limiting on the number of their objects.
The memory mainly comprises a substrate, a word line, a bit line, a storage capacitor and a transistor, wherein the word line is simultaneously used as a grid electrode of the transistor and used for controlling the transistor to be switched on or switched off, the bit line is connected with a source electrode of the transistor, and the storage capacitor is communicated with the source electrode of the transistor through a conductive contact plug. A plurality of transistors are usually included in a memory, that is, a plurality of word lines are included in the memory, and the word lines may be distributed side by side. At present, in the process of performing an electrical test on a word line, voltages are respectively applied to a word line to be detected, a bit line connected to the word line to be detected, a conductive contact plug connected to the word line to be detected, and a body lead-out area on a substrate through probes, so as to complete the electrical test; however, in the above test process, the influence of other word lines around the word line to be tested is ignored, so that the test data deviation is large, and the accuracy of the test result is low.
Accordingly, the present disclosure provides an electrical testing method for a semiconductor device, which may be a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), or the like. Fig. 1 shows a flowchart of an electrical testing method of a semiconductor device in an embodiment of the present disclosure, and referring to fig. 1, the testing method may include steps S110 to S130, where:
step S110, providing a semiconductor structure, wherein the semiconductor structure comprises an array area and a body leading-out area, the array area comprises a plurality of word lines distributed at intervals, and both sides of each word line are respectively distributed with a conductive contact plug and a bit line;
step S120, respectively forming conductive structures for leading out the bit line, the conductive contact plug, the body leading-out region, any word line and word lines adjacent to the two sides of the word line;
in step S130, a voltage is applied to each of the conductive structures to complete an electrical test.
According to the electrical test method of the semiconductor device, the bit line, the body lead-out region, the conductive contact plug and each word line can be electrically led out through the conductive structures, and the electrical test can be completed by applying voltage to each conductive structure. In the process, other word lines on two sides of the word line to be tested can be tested simultaneously, and further, the influence of other word lines around the word line to be tested is taken into consideration, so that the test result deviation can be reduced, and the test accuracy is improved.
The following provides a detailed description of the electrical testing method of the semiconductor device according to the embodiments of the present disclosure:
as shown in fig. 1, in step S110, a semiconductor structure is provided, where the semiconductor structure includes an array region and a body pull-out region, the array region includes a plurality of word lines distributed at intervals, and conductive contact plugs and bit lines are respectively distributed on two sides of each word line.
As shown in fig. 2, the semiconductor structure may include a substrate 100, and the substrate 100 may be a flat plate structure, which may be rectangular, circular, oval, polygonal or irregular, and may be made of silicon or other semiconductor materials, and the shape and material of the substrate 100 are not particularly limited.
Shallow trench isolation structures, well regions, etc. may also be formed on the substrate 100. The substrate 100 may be p-type and may include spaced apart source and drain regions. The source and drain regions may be doped to form a source 101 and a drain 102. For example, the source and drain regions may be n-doped. For example, the source and drain regions may be doped with an n-type dopant material such that the source and drain regions form an n-type semiconductor. The n-type doping material may be an element in group V of the periodic table, such as phosphorus, but may be other elements, which are not listed here. The substrate 100 may be n-type, and in this case, the source region and the drain region may be p-type doped.
In an embodiment, the source region and the drain region may be implanted with phosphorous ions by ion implantation, but the source region and/or the drain region may also be doped by other processes, which is not limited herein.
It should be noted that a channel region may be disposed between the source region and the drain region, a gate trench may be disposed in the channel region, and a buried word line structure may be formed in the gate trench, and the word line structure may serve as a gate of the transistor to control the transistor to be turned on or off.
As shown in fig. 3, the substrate 100 may include an array region 11 and a body pull-out region 12, wherein the array region 11 is used to form word lines, bit lines 300 and a plurality of storage capacitors 600 distributed in an array, the body pull-out region 12 is used to form metal wirings, and the array region 11 and the body pull-out region 12 may be disposed side by side and adjacently distributed. Each word line may be located in the array region 11, and the word lines may be distributed at equal intervals in the array region 11, and each word line has a source 101 and a drain 102 on both sides of a top end thereof. The bit line 300 may be connected to the source 101, and the storage capacitor 600 may be connected to the drain 102 through the conductive contact plug 400; namely: conductive contact plugs 400 and bit lines 300 are respectively distributed on two sides of each word line, and each word line and the corresponding conductive contact plug 400 and bit line 300 form a transistor; the word line serves as a gate of the transistor, the bit line 300 serves as a source of the transistor, and the conductive contact plug 400 serves as a drain of the transistor.
For the sake of convenience of distinction, any word line may be defined as the target word line 200, while adjacent word lines on both sides of the target word line 200 are defined as the first word line 210 and the second word line 220, respectively. For example, one word line may be randomly selected as the target word line 200, and two word lines adjacent to the target word line 200 on both sides of the target word line 200 are defined as a first word line 210 and a second word line 220, respectively. That is, the target word line 200 is located between the first word line 210 and the second word line 220.
As shown in fig. 1, in step S120, conductive structures for leading out the bit lines, the conductive contact plugs, the body leading-out regions, any one of the word lines, and word lines adjacent to both sides of the word line are respectively formed.
Contact holes respectively exposing partial areas of the bit line 300, the conductive contact plug 400, the body extraction region 12 and the word line can be formed, so that conductive structures are respectively formed in the contact holes, and the bit line 300, the conductive contact plug 400, the body extraction region 12, the target word line 200, the first word line 210 and the second word line 220 are respectively and electrically extracted through the conductive structures, so that the bit line 300, the conductive contact plug 400, the body extraction region 12, the target word line 200, the first word line 210 and the second word line 220 can be electrically tested through the conductive structures.
In an exemplary embodiment of the present disclosure, conductive structures leading out the bit line 300, the conductive contact plug 400, the body lead-out region 12, any one of the word lines, and word lines adjacent to both sides of the word line are respectively formed, that is: step S120 may include steps S1201 to S1204, as shown in fig. 4, in which:
step S1201 is to form a first contact hole exposing the target word line, a second contact hole exposing the first word line, a third contact hole exposing the second word line, a fourth contact hole exposing the conductive contact plug, and a fifth contact hole exposing the bit line in the array region.
The first contact hole may be formed in the array region 11 by an etching process, and the first contact hole may expose the target word line 200, or the surface of the region of the array region 11 where the target word line 200 is located may be polished, ground, or ground by a polishing, grinding, or grinding process, so as to form the first contact hole exposing the target word line 200, where a forming manner of the first contact hole is not particularly limited.
The first contact hole may be a circular hole, an elliptical hole, a rectangular hole, or a hole structure with other shapes, and the shape of the first contact hole is not particularly limited as long as the target word line 200 is exposed.
It should be noted that the aperture of the first contact hole may be slightly larger than the width of the target word line 200 in the direction perpendicular to the extension direction of the target word line 200, and the aperture of the first contact hole may be much smaller than the length of the target word line 200 in the direction parallel to the extension direction of the target word line 200. Taking the first contact hole as a circular hole as an example, the center of the first contact hole is located at the center of the target word line 200, the diameter of the first contact hole is slightly larger than the width of the target word line 200, and the radius of the first contact hole is smaller than the distance between two adjacent word lines.
In one embodiment, the second contact hole can be staggered from the first contact hole to prevent the first contact hole and the second contact hole from communicating, and thus prevent the first conductive structure 510 formed in the first contact hole from being shorted with the second conductive structure 520 formed in the second contact hole.
The second contact hole may be formed in the array region 11 by an etching process, and the second contact hole may expose the first word line 210, or the surface of the region of the array region 11 where the first word line 210 is located may be polished, ground, or ground by a polishing, grinding, or grinding process, so as to form the second contact hole exposing the first word line 210, where a forming manner of the second contact hole is not particularly limited.
The second contact hole may be a circular hole, an elliptical hole, a rectangular hole, or a hole structure with other shapes, and the shape of the second contact hole is not particularly limited as long as the first word line 210 is exposed.
It should be noted that the aperture of the second contact hole may be slightly larger than the width of the first word line 210 in the direction perpendicular to the extending direction of the first word line 210, and the aperture of the second contact hole may be much smaller than the length of the first word line 210 in the direction parallel to the extending direction of the first word line 210. Taking the second contact hole as a circular hole as an example, the center of the second contact hole is located at the center of the first word line 210, the diameter of the second contact hole is slightly larger than the width of the first word line 210, and the radius of the second contact hole is smaller than the distance between two adjacent word lines.
The third contact hole may be formed in the array region 11 by an etching process, and the third contact hole may expose the second word line 220, or the surface of the region where the second word line 220 is located in the array region 11 may be polished, ground, or ground by a polishing, grinding, or grinding process, so as to form the third contact hole exposing the second word line 220, where a forming manner of the third contact hole is not particularly limited.
The third contact hole may be a circular hole, an elliptical hole, a rectangular hole, or a hole structure with other shapes, and the shape of the third contact hole is not particularly limited as long as the second word line 220 is exposed.
It should be noted that, in the direction perpendicular to the extending direction of the second word line 220, the aperture of the third contact hole may be slightly larger than the width of the second word line 220, and in the direction parallel to the extending direction of the second word line 220, the aperture of the third contact hole may be much smaller than the length of the second word line 220. Taking the third contact hole as a circular hole as an example, the center of the third contact hole is located at the center of the second word line 220, the diameter of the third contact hole is slightly larger than the width of the second word line 220, and the radius of the third contact hole is smaller than the distance between two adjacent word lines.
It should be noted that the distance between the third contact hole and the second contact hole may be greater than the distance between two adjacent word lines, so that the distance between the third conductive structure 530 formed in the third contact hole and the second conductive structure 520 formed in the second contact hole is greater than the distance between two adjacent word lines, and the third conductive structure 530 and the second conductive structure 520 may be prevented from being shorted with the target word line 200.
The fourth contact hole may be formed in the array region 11 by an etching process, and the fourth contact hole may expose the conductive contact plug 400, or the surface of the region of the array region 11 where the conductive contact plug 400 is located may be polished, ground, or lapped by a polishing, grinding, or lapping process, so as to form the fourth contact hole exposing the conductive contact plug 400, and a forming manner of the fourth contact hole is not particularly limited.
The shape of the fourth contact hole may be the same as the shape of the conductive contact plug 400, or may be different from the shape of the conductive contact plug 400, and is not particularly limited. For example, the fourth contact hole may be a circular hole, an elliptical hole, a rectangular hole, or a hole structure with other shapes, and the shape of the fourth contact hole is not particularly limited as long as the conductive contact plug 400 is exposed.
It should be noted that the orthographic projection of the fourth contact hole on the substrate 100 may be within the orthographic projection of the conductive contact plug 400 on the substrate 100, that is: the orthographic projection of the fourth contact hole on the substrate 100 may coincide with the orthographic projection of the conductive contact plug 400 on the substrate 100, and may also be inside the orthographic projection of the conductive contact plug 400 on the substrate 100.
The fifth contact hole may be formed in the array region 11 by an etching process, and the fifth contact hole may expose the bit line 300, or the surface of the region of the array region 11 where the bit line 300 is located may be polished, ground, or ground by a polishing, grinding, or grinding process, so as to form the fifth contact hole exposing the bit line 300, where a forming manner of the fifth contact hole is not particularly limited.
The fifth contact hole may be a circular hole, an elliptical hole, a rectangular hole, or a hole structure with other shapes, and the shape of the fifth contact hole is not particularly limited as long as the bit line 300 is exposed.
Note that, in the extending direction perpendicular to the bit line 300, the aperture of the fifth contact hole may be slightly larger than the width of the bit line 300, and in the extending direction parallel to the bit line 300, the aperture of the fifth contact hole may be much smaller than the length of the bit line 300. Taking the fifth contact hole as a circular hole as an example, the center of the fifth contact hole is located at the center of the bit line 300, the diameter of the fifth contact hole is slightly larger than the width of the bit line 300, and the radius of the fifth contact hole is smaller than the distance between two adjacent bit lines 300.
Step S1202, conductive materials are respectively filled in the first contact hole, the second contact hole, the third contact hole, the fourth contact hole and the fifth contact hole, so as to form a first conductive structure in the first contact hole, a second conductive structure in the second contact hole, a third conductive structure in the third contact hole, a fourth conductive structure in the fourth contact hole and a fifth conductive structure in the fifth contact hole.
Conductive materials may be respectively filled in the first contact hole, the second contact hole, the third contact hole, the fourth contact hole and the fifth contact hole by Focusing Ion Beam (FIB), and of course, processes such as vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, thermal evaporation or atomic layer deposition may also be adopted to respectively fill conductive materials in the first contact hole, the second contact hole, the third contact hole, the fourth contact hole and the fifth contact hole, so as to form the first conductive structure 510 in the first contact hole, the second conductive structure 520 in the second contact hole, the third conductive structure 530 in the third contact hole, the fourth conductive structure 540 in the fourth contact hole, and the fifth conductive structure 550 in the fifth contact hole, so as to facilitate passing through the first conductive structure 510, the second conductive structure 520, the third conductive structure 530 and the fifth contact hole, The fourth conductive structure 540 and the fifth conductive structure 550 electrically lead out the target word line 200, the first word line 210, the second word line 220, the conductive contact plug 400 and the bit line 300, respectively.
It should be noted that, the second conductive structures 520 and the first conductive structures 510 are distributed in a staggered manner, so as to prevent the first conductive structures 510 and the second conductive structures 520 from being short-circuited; the distance between the third conductive structure 530 and the second conductive structure 520 is greater than the distance between two adjacent word lines, so as to prevent the third conductive structure 530 and the second conductive structure 520 from being shorted with the target word line 200.
In an exemplary embodiment of the present disclosure, the conductive material may be tungsten, but may also be other materials with better conductivity, which is not listed here.
In step S1203, a sixth contact hole exposing the conductive line of the body lead-out area is formed in the body lead-out area.
The conductive line may be a metal wiring structure located in the body extracting region 12, which may include a plurality of wiring circuits, may be connected to the array region 11 through the wiring circuits, and may electrically extract a word line, a bit line 300, a conductive contact plug 400, a storage capacitor 600, or the like in the array region 11 through the wiring circuits.
The sixth contact hole may be formed in the body lead-out region 12 by an etching process, and the sixth contact hole may expose the wiring circuit, or the surface of the region where the wiring circuit is located in the body lead-out region 12 may be polished, ground, or ground by a polishing, grinding, or grinding process, so as to form the sixth contact hole exposing the wiring circuit, and the formation manner of the sixth contact hole is not particularly limited.
The sixth contact hole may be a circular hole, an elliptical hole, a rectangular hole, or a hole structure having another shape, and the shape of the sixth contact hole is not particularly limited as long as the wiring circuit is exposed.
Note that the aperture diameter of the sixth contact hole may be slightly larger than the width of the wiring circuit in the direction perpendicular to the extending direction of the wiring circuit, and the aperture diameter of the sixth contact hole may be much smaller than the length of the wiring circuit in the direction parallel to the extending direction of the wiring circuit. Taking the sixth contact hole as a circular hole as an example, the circle center of the sixth contact hole is located at the center of the wiring circuit, the diameter of the circle center is slightly larger than the width of the wiring circuit, and the radius of the sixth contact hole is smaller than the distance between two adjacent wiring circuits.
Step S1204, filling a conductive material in the sixth contact hole to form a sixth conductive structure.
The sixth contact hole may be filled with a conductive material by a Focused Ion Beam (FIB) method, and of course, the sixth contact hole may also be filled with a conductive material by vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, thermal evaporation, atomic layer deposition, or other processes, so as to form a sixth conductive structure 560 in the sixth contact hole, so that the body extraction region 12 is electrically extracted through the sixth conductive structure 560.
As shown in fig. 1, in step S130, a voltage is applied to each of the conductive structures to complete an electrical test.
The electrical test can be completed by applying voltages to the first conductive structure 510, the second conductive structure 520, the third conductive structure 530, the fourth conductive structure 540, the fifth conductive structure 550, and the sixth conductive structure 560 through the nanoprobes, respectively.
For example, 6 nanoprobes can be respectively bundled on the first conductive structure 510, the second conductive structure 520, the third conductive structure 530, the fourth conductive structure 540, the fifth conductive structure 550, and the sixth conductive structure 560, and then the voltage applied by each nanoprobe is respectively transmitted to the target word line 200, the first word line 210, the second word line 220, the conductive contact plug 400, the bit line 300, and the body lead-out region 12 corresponding to each conductive structure through the first conductive structure 510, the second conductive structure 520, the third conductive structure 530, the fourth conductive structure 540, the fifth conductive structure 550, and the sixth conductive structure 560.
In an exemplary embodiment of the present disclosure, the scan voltage of the target word line 200 may be-0.5V-3V, the scan voltages of the first and second word lines 210 and 220 may be-0.2V-1V, the voltage of the conductive contact plug 400 may be 0.05V-1V, the voltage of the bit line 300 may be-0.05V-0V, and the voltage of the body extracting region 12 may be-0.7V-0V.
For example, two test conditions can be set by a nanoprobe machine according to a linear region and a saturation region, and in the linear region, a scan voltage of-0.5V to 3V can be applied to the target word line 200, a voltage of 0.05V can be applied to the conductive plug 400, a voltage of 0V can be applied to the bit line 300, a voltage of-0.7V can be applied to the body pull-out region 12, a voltage of-0.2V can be applied to both the first word line 210 and the second word line 220, and the I of the transistor can be testedd-VgCurve, further through Id-VgCurve-aware transistor operation in-lineCurrent, voltage parameters in the region. In the saturation region, a scan voltage of-0.5V to 3V may be applied to the target word line 200, a voltage of 1V may be applied to the conductive contact plug 400, a voltage of 0V may be applied to the bit line 300, a voltage of-0.7V may be applied to the bulk extraction region 12, a voltage of-0.2V may be applied to both the first word line 210 and the second word line 220, and I of the transistor may be testedd-VgCurve, further through Id-VgThe current and voltage parameters of the transistor working in the saturation region are obtained through the curve.
In an exemplary embodiment of the present disclosure, the testing method of the present disclosure may further include steps S210 to S230, as shown in fig. 5, wherein:
step S210 detects a first leakage current between the target word line and the first word line.
After the conductive structure is formed, the leakage current between the target word line 200 and the first word line 210 can be detected, and then whether the leakage current is introduced in the process of forming the first conductive structure 510 and the second conductive structure 520 is judged, so that the influence of the leakage current brought in the process of forming the first conductive structure 510 and the second conductive structure 520 is eliminated, and the accuracy of the test result is improved.
In an exemplary embodiment of the present disclosure, detecting a first leakage current between the target word line 200 and the first word line 210, i.e., step S210, may include step S2101 and step S2102, wherein:
step S2101, a first preset voltage is applied to the first conductive structure, and a second preset voltage is applied to the second conductive structure.
A first preset voltage may be applied to the first conductive structure 510 through the nanoprobe, and then the first preset voltage may be transferred to the target word line 200 through the first conductive structure 510. The first preset voltage may be a preset voltage value, for example, the first preset voltage may range from-2V to 2V, and the first preset voltage may be gradually increased or decreased within a range from-2V to 2V according to a preset step. For example, the step pitch may be 0.02V or 0.05V, or other step pitches may be used, and is not particularly limited herein.
Meanwhile, a second preset voltage may be applied to the second conductive structure 520 through the nanoprobe, and then the second preset voltage may be transferred to the first word line 210 through the second conductive structure 520. The second predetermined voltage may be a fixed voltage, for example, the second predetermined voltage may be 0V.
Step S2102 of detecting a first leakage current between the first conductive structure and the second conductive structure.
During the process of applying the voltage to the target word line 200 and the first word line 210 and scanning according to the preset layout, a current between the first conductive structure 510 and the second conductive structure 520 may be detected, and the current may be defined as a first leakage current. For example, the first leakage current may be detected by using an ammeter, a multimeter, a current tester, or the like, but of course, the first leakage current may also be detected by using other instruments or devices, which are not listed herein.
Step S220 is performed to detect a second leakage current between the target word line and the second word line.
After the conductive structure is formed, the leakage current between the target word line 200 and the second word line 220 can be detected, and whether the leakage current is introduced in the process of forming the third conductive structure 530 can be further determined, so that the influence of the leakage current brought in the process of forming the third conductive structure 530 can be eliminated, and the accuracy of the test result can be improved.
In an exemplary embodiment of the present disclosure, detecting the second leakage current between the target word line 200 and the second word line 220, i.e., step S220, may include steps S2201 and S2202, wherein:
step S2201, a first preset voltage is applied to the first conductive structure, and a third preset voltage is applied to the third conductive structure.
A first preset voltage may be applied to the first conductive structure 510 through the nanoprobe, and then the first preset voltage may be transferred to the target word line 200 through the first conductive structure 510. The first preset voltage may be a preset voltage value, for example, the first preset voltage may range from-2V to 2V, and the first preset voltage may be gradually increased or decreased within a range from-2V to 2V according to a preset step. For example, the step pitch may be 0.02V, but other step pitches are also possible, and are not particularly limited herein.
Meanwhile, a third preset voltage may be applied to the third conductive structure 530 through the nanoprobe, and then the third preset voltage may be transferred to the second word line 220 through the third conductive structure 530. The third predetermined voltage may be the same as the second predetermined voltage, that is, the third predetermined voltage may also be a fixed voltage, for example, the third predetermined voltage may be 0V.
Step S2202, detecting a second leakage current between the first conductive structure and the third conductive structure.
During the process of applying the voltage to the target word line 200 and the second word line 220 and scanning according to the preset layout, a current between the first conductive structure 510 and the third conductive structure 530 may be detected, and the current may be defined as a second leakage current. For example, the second leakage current may be detected by using an ammeter, a multimeter, a current tester, or the like, and of course, other instruments or devices may be used to detect the second leakage current, which is not listed here.
Step S230, when the magnitudes of the first leakage current and the second leakage current are smaller than or equal to a first magnitude, applying voltages to the first conductive structure, the second conductive structure, the third conductive structure, the fourth conductive structure, the fifth conductive structure, and the sixth conductive structure, respectively, to complete an electrical test.
The detected first leakage current and the second leakage current can be analyzed, and whether the first leakage current and the second leakage current can affect the electrical test result or not is judged. Specifically, when the magnitude of the first leakage current and the magnitude of the second leakage current are both smaller than or equal to the first magnitude, it is considered that the first leakage current and the second leakage current do not affect the electrical test result, and at this time, voltages may be applied to the first conductive structure 510, the second conductive structure 520, the third conductive structure 530, the fourth conductive structure 540, the fifth conductive structure 550, and the sixth conductive structure 560, respectively, to complete the electrical test. In the process, the influence of leakage current introduced in the process of forming the conductive structure is eliminated, and the accuracy of the electrical test result can be improved.
In an exemplary embodiment of the present disclosure, the first order of magnitude may be 10-15A, the magnitude of the first leakage current and the second leakage current are both 10-15A, or both the first and second leakage currents are less than 10-15A, or, either of the first leakage current and the second leakage current is in the order of 10-15A, another is of the order of less than 10-15And A, judging that the first leakage current and the second leakage current do not influence the electrical property test result.
For example, when the first leakage current is of the order of 10-15A, the second leakage current is of the order of 10-16When A is performed, the first leakage current and the second leakage current can be judged not to influence the electrical property test result; when the first leakage current is of the order of 10- 16A, the second leakage current is of the order of 10-17During A, the first leakage current and the second leakage current can be judged not to influence the electrical property test result; when the magnitude of the first leakage current and the magnitude of the second leakage current are both 10-16During the step A, it can be determined that the first leakage current and the second leakage current do not affect the electrical test result.
In an exemplary embodiment of the present disclosure, the testing method of the present disclosure may further include:
step S240, when at least one of the first leakage current and the second leakage current is larger than the first order of magnitude, reselecting the target word line, the first word line, and the second word line until the detected first leakage current and the detected second leakage current are both smaller than or equal to the first order of magnitude.
When at least one of the first leakage current and the second leakage current is larger than the first order of magnitude, it can be determined that the first leakage current and the second leakage current may affect the electrical test result, and further it can be known that the leakage current is introduced in the process of forming the second conductive structure 520 and the third conductive structure 530, the formed second conductive structure 520 and the third conductive structure 530 do not meet the test standard, the target word line 200, the first word line 210 and the second word line 220 need to be reselected, and a first leakage current between the first conductive structure 510 corresponding to the new target word line 200 and the second conductive structure 520 corresponding to the new first word line 210 and a second leakage current between the first conductive structure 510 corresponding to the new target word line 200 and the third conductive structure 530 corresponding to the new second word line 220 are detected, until the detected first leakage current and second leakage current are smaller than or equal to the first order of magnitude, the new target word line 200 is stopped to be searched, A first word line 210 and a second word line 220.
In one embodiment, when either of the first leakage current and the second leakage current is on the order of 10-15A, another is of the order of magnitude greater than 10-15During A, the first leakage current and the second leakage current can be judged to influence the electrical property test result; the magnitude of the first leakage current and the second leakage current are both larger than 10-15A, it is also determined that the first leakage current and the second leakage current have an effect on the electrical test result.
For example, when the magnitude of the first leakage current and the magnitude of the second leakage current are both 10-14During A, the first leakage current and the second leakage current can be judged to influence the electrical property test result; when the first leakage current is of the order of 10-14A, the second leakage current is of the order of 10-15During A, the first leakage current and the second leakage current can be judged to influence the electrical property test result; when the first leakage current is of the order of 10-14A, the second leakage current is of the order of 10-13During the step A, it can be determined that the first leakage current and the second leakage current will affect the electrical test result.
In an exemplary embodiment of the present disclosure, as shown in fig. 6, the testing method of the present disclosure may further include:
step S310 detects transfer currents of the first word line and the second word line, respectively.
A voltage may be applied to the first word line 210, the conductive contact plug 400, the bit line 300, and the body-drawing region 12 through the nanoprobe, thereby detecting a transfer current of the first word line 210. In addition, voltages may be applied to the second word line 220, the conductive contact plug 400, the bit line 300, and the body lead region 12 through the nanoprobe, thereby detecting a transfer current of the second word line 220.
Step S320, detecting a saturation current corresponding to the conductive contact plug operating in a saturation region.
During the process of detecting the first word line 210 and the second word line 220, the saturation current corresponding to the conductive contact plug 400 operating in the saturation region may be calculated according to the generated I-V curve.
Step S330, controlling the voltage of the first word line and the voltage of the second word line to be 0V, and detecting the corresponding working current value on the conductive contact plug.
The probe can supply 0V to both the first word line 210 and the second word line 220, and thus detect the corresponding operating voltage on the conductive contact plug 400.
Step S340, when the magnitude of the transfer current and the magnitude of the saturation current are both greater than or equal to a second magnitude, and the magnitude of the working current is less than or equal to a third magnitude, applying voltages to the first conductive structure, the second conductive structure, the third conductive structure, the fourth conductive structure, the fifth conductive structure, and the sixth conductive structure, respectively, to complete an electrical test.
When the transfer currents of the first word line 210 and the second word line 220 and the magnitude of the saturation currents corresponding to the conductive contact plugs 400 operating in the saturation region are both greater than or equal to a second magnitude, and the voltages of the first word line 210 and the second word line 220 are both 0V, and the magnitude of the operating currents corresponding to the conductive contact plugs 400 is less than or equal to a third magnitude, it is determined that the second conductive structure 520 corresponding to the first word line 210 and the third conductive structure 530 corresponding to the second word line 220 can normally control the on-off state of the word lines, so that failures can be eliminated, and the accuracy of the electrical test can be further improved.
In an exemplary embodiment of the present disclosure, the second order of magnitude may be 10-6A, the third order of magnitude may be 10- 15A, namely: the transfer current of the first word line 210 and the second word line 220 and the saturation current of the conductive contact plug 400 are both greater than or equal to 10 when they are in the saturation region-6A, when the voltages of the first word line 210 and the second word line 220 are both 0V, the conductive contact plug 400 is corresponding to the first word lineIs of the order of 10 or less-15At a, it is determined that the second conductive structure 520 corresponding to the first word line 210 and the third conductive structure 530 corresponding to the second word line 220 may normally control the on/off state of the word lines.
For example, when the transfer current of the first word line 210 and the second word line 220 and the conductive contact plug 400 operate in the saturation region, the corresponding saturation current is 10 orders of magnitude-6A, when the voltages of the first word line 210 and the second word line 220 are both 0V, the magnitude of the corresponding working current on the conductive contact plug 400 is 10-15At time a, determining that the second conductive structure 520 corresponding to the first word line 210 and the third conductive structure 530 corresponding to the second word line 220 can normally control the on-off state of the word lines; for another example, when the transfer current of the first word line 210 and the second word line 220 and the conductive contact plug 400 operate in the saturation region, the saturation current is 10 orders of magnitude-5A, when the voltages of the first word line 210 and the second word line 220 are both 0V, the magnitude of the corresponding working current on the conductive contact plug 400 is 10-16At time a, the second conductive structure 520 corresponding to the first word line 210 and the third conductive structure 530 corresponding to the second word line 220 are determined to normally control the on/off state of the word lines, but of course, other cases are also possible, and they are not listed here.
It should be noted that although the steps of the method of fabricating a semiconductor structure of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that the steps must be performed in this particular order or that all of the depicted steps must be performed to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken into multiple step executions, etc.
The disclosed embodiments also provide an electrical test structure of a semiconductor device, which may include a semiconductor structure and a plurality of conductive structures, as shown in fig. 2 and 3, wherein:
the semiconductor structure comprises an array region 11 and a body leading-out region 12, wherein the array region 11 comprises a plurality of word lines distributed at intervals, and conductive contact plugs 400 and bit lines 300 are distributed on two sides of each word line respectively;
the plurality of conductive structures, bit line 300, conductive contact plug 400, body pull-out region 12, any word line and the word lines adjacent to the word line on both sides are connected to one conductive structure in a one-to-one correspondence manner.
The electrical test structure of the semiconductor device of the present disclosure can electrically lead out the bit line 300, the body lead-out region 12, the conductive contact plug 400, and each word line through the conductive structure, and further complete an electrical test by applying a voltage to each conductive structure. In the process, other word lines on two sides of the word line to be tested can be tested simultaneously, and further, the influence of other word lines around the word line to be tested is taken into consideration, so that the test result deviation can be reduced, and the test accuracy is improved.
The semiconductor structure may include the substrate 100, and the substrate 100 may be a flat plate structure, which may be rectangular, circular, oval, polygonal or irregular, and the material may be silicon or other semiconductor materials, and the shape and material of the substrate 100 are not particularly limited.
Shallow trench isolation structures, well regions, etc. may also be formed on the substrate 100. The substrate 100 may be p-type and may include spaced apart source and drain regions. The source and drain regions may be doped to form a source 101 and a drain 102. For example, the source and drain regions may be n-doped. For example, the source and drain regions may be doped with an n-type dopant material such that the source and drain regions form an n-type semiconductor. The n-type doping material may be an element in group V of the periodic table, such as phosphorus, but may be other elements, which are not listed here. It should be noted that the substrate 100 may also be n-type, and the source region and the drain region may be p-type doped.
In an embodiment, phosphorus ions may be implanted into the source region and the drain region by ion implantation, but the source region and/or the drain region may also be doped by other processes, which are not limited herein.
It should be noted that a channel region may be disposed between the source region and the drain region, a gate trench may be disposed in the channel region, and a buried word line structure may be formed in the gate trench, and the word line structure may serve as a gate of the transistor and may control the transistor to be turned on or off.
The substrate 100 may include an array region 11 and a body-drawing region 12, wherein the array region 11 is used to form word lines, bit lines 300 and a plurality of storage capacitors 600 distributed in an array, the body-drawing region 12 is used to form metal wirings, and the array region 11 and the body-drawing region 12 may be disposed side by side and adjacently distributed. Each word line may be located in the array region 11, and each word line may be distributed at equal intervals in the array region 11, and each word line has a source 101 and a drain 102 on both sides of the top end. The bit line 300 may be connected to the source 101, and the storage capacitor 600 may be connected to the drain 102 through the conductive contact plug 400; namely: the conductive contact plugs 400 and the bit lines 300 are respectively distributed on two sides of each word line, and each word line and the corresponding conductive contact plug 400 and bit line 300 form a transistor; the word line serves as a gate of the transistor, the bit line 300 serves as a source of the transistor, and the conductive contact plug 400 serves as a drain of the transistor.
For the sake of convenience of distinction, any word line may be defined as the target word line 200, while adjacent word lines on both sides of the target word line 200 are defined as the first word line 210 and the second word line 220, respectively. For example, one word line may be randomly selected as the target word line 200, and two word lines adjacent to the target word line 200 on both sides of the target word line 200 are defined as a first word line 210 and a second word line 220, respectively. That is, the target word line 200 is located between the first word line 210 and the second word line 220.
The number of the conductive structures may be multiple, the multiple conductive structures may be connected to the target word line 200, the first word line 210, the second word line 220, the conductive contact plug 400, the bit line 300, and the body extension region 12 in a one-to-one correspondence manner, and the target word line 200, the first word line 210, the second word line 220, the conductive contact plug 400, the bit line 300, and the body extension region 12 may be respectively electrically extended by each conductive structure.
In an exemplary embodiment of the present disclosure, the material of the conductive structure may be tungsten, and of course, other materials with better conductivity may also be used, which are not listed here.
For convenience of distinction, a conductive structure corresponding to the target word line 200 may be defined as a first conductive structure 510, a conductive structure corresponding to the first word line 210 may be defined as a second conductive structure 520, a conductive structure corresponding to the second word line 220 may be defined as a third conductive structure 530, a conductive structure corresponding to the conductive contact plug 400 may be defined as a fourth conductive structure 540, a conductive structure corresponding to the bit line 300 may be defined as a fifth conductive structure 550, and a conductive structure corresponding to the body lead-out region 12 may be defined as a sixth conductive structure 560.
In an exemplary embodiment of the present disclosure, the second conductive structure 520 is distributed with a misalignment with the first conductive structure 510 to avoid the first conductive structure 510 and the second conductive structure 520 being shorted; the distance between the third conductive structure 530 and the second conductive structure 520 is greater than the distance between two adjacent word lines, so as to prevent the third conductive structure 530 and the second conductive structure 520 from being shorted with the target word line 200.
The electrical test can be completed by applying voltages to the first conductive structure 510, the second conductive structure 520, the third conductive structure 530, the fourth conductive structure 540, the fifth conductive structure 550, and the sixth conductive structure 560 through the nanoprobes, respectively.
For example, 6 nanoprobes can be respectively tied on the first conductive structure 510, the second conductive structure 520, the third conductive structure 530, the fourth conductive structure 540, the fifth conductive structure 550 and the sixth conductive structure 560, and then the voltage applied by each probe is respectively transmitted to the target word line 200, the first word line 210, the second word line 220, the conductive contact plug 400, the bit line 300 and the body leading-out region 12 corresponding to each conductive structure through the first conductive structure 510, the second conductive structure 520, the third conductive structure 530, the fourth conductive structure 540, the fifth conductive structure 550 and the sixth conductive structure 560, so as to complete the electrical test.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims (15)

1. A method for testing electrical properties of a semiconductor device, comprising:
providing a semiconductor structure, wherein the semiconductor structure comprises an array area and a body leading-out area, the array area comprises a plurality of word lines distributed at intervals, and conductive contact plugs and bit lines are distributed on two sides of each word line respectively;
respectively forming a conductive structure for leading out the bit line, the conductive contact plug, the body leading-out region, any word line and word lines adjacent to two sides of the word line;
and applying voltage to each conductive structure respectively to complete the electrical test.
2. The test method according to claim 1, wherein any one of the word lines is defined as a target word line, and the word lines adjacent to both sides of the target word line are defined as a first word line and a second word line, respectively; the conductive structure corresponding to the target word line is a first conductive structure, the conductive structure corresponding to the first word line is a second conductive structure, the conductive structure corresponding to the second word line is a third conductive structure, the conductive structure corresponding to the conductive contact plug is a fourth conductive structure, the conductive structure corresponding to the bit line is a fifth conductive structure, and the conductive structure corresponding to the body leading-out region is a sixth conductive structure;
the test method further comprises:
detecting a first leakage current between the target word line and the first word line;
detecting a second leakage current between the target word line and the second word line;
and when the magnitude of the first leakage current and the magnitude of the second leakage current are smaller than or equal to a first magnitude, respectively applying voltage to the first conductive structure, the second conductive structure, the third conductive structure, the fourth conductive structure, the fifth conductive structure and the sixth conductive structure to finish an electrical test.
3. The method of claim 2, wherein the detecting the first leakage current between the target word line and the first word line comprises:
applying a first preset voltage to the first conductive structure and applying a second preset voltage to the second conductive structure;
a first leakage current is detected between the first conductive structure and the second conductive structure.
4. The method of claim 3, wherein the detecting a second leakage current between the target word line and the second word line comprises:
applying a first preset voltage to the first conductive structure and applying a third preset voltage to the third conductive structure;
detecting a second leakage current between the first conductive structure and the third conductive structure.
5. The test method according to claim 4, wherein the first preset voltage is in a range of-2V to 2V, and the second preset voltage and the third preset voltage are both 0V.
6. The method as claimed in claim 2, wherein the word lines are equally spaced apart from each other, and the second conductive structure is spaced apart from the third conductive structure by a distance greater than a distance between two adjacent word lines.
7. The method as claimed in claim 2, wherein the forming of the conductive structures respectively leading out the bit line, the conductive contact plug, the body lead-out region, any one of the word lines and the word lines adjacent to the word lines at two sides thereof comprises:
forming a first contact hole exposing the target word line, a second contact hole exposing the first word line, a third contact hole exposing the second word line, a fourth contact hole exposing the conductive contact plug and a fifth contact hole exposing the bit line in the array area;
filling conductive materials in the first contact hole, the second contact hole, the third contact hole, the fourth contact hole and the fifth contact hole respectively so as to form a first conductive structure in the first contact hole, a second conductive structure in the second contact hole, a third conductive structure in the third contact hole, a fourth conductive structure in the fourth contact hole and a fifth conductive structure in the fifth contact hole;
forming a sixth contact hole exposing the conductive circuit of the body lead-out area in the body lead-out area;
and filling a conductive material in the sixth contact hole to form a sixth conductive structure.
8. The test method of claim 7, wherein the conductive material is tungsten.
9. The test method of any one of claims 2-8, further comprising:
detecting transfer currents of the first word line and the second word line, respectively;
detecting the corresponding saturation current when the conductive contact plug works in a saturation region;
controlling the voltage of the first word line and the voltage of the second word line to be 0V, and detecting the corresponding working current value on the conductive contact plug;
and when the magnitude of the transfer current and the magnitude of the saturation current are both larger than or equal to a second magnitude and the magnitude of the working current is smaller than or equal to a third magnitude, applying voltages to the first conductive structure, the second conductive structure, the third conductive structure, the fourth conductive structure, the fifth conductive structure and the sixth conductive structure respectively to finish an electrical test.
10. The testing method of claim 2, further comprising:
when at least one of the first leakage current and the second leakage current is larger in magnitude than the first magnitude, reselecting the target word line, the first word line, and the second word line until the detected magnitudes of the first leakage current and the second leakage current are both smaller than or equal to the first magnitude.
11. Test method according to claim 10, characterized in that said first order of magnitude is 10-15A。
12. The test method of claim 9, wherein the second magnitude is 10-6A, said third order of magnitude being 10-15A。
13. An electrical testing structure of a semiconductor device, comprising:
the semiconductor structure comprises an array area and a body leading-out area, wherein the array area comprises a plurality of word lines distributed at intervals, and conductive contact plugs and bit lines are distributed on two sides of each word line respectively;
the bit lines, the conductive contact plugs, the body leading-out regions, any word line and the word lines adjacent to the two sides of the word lines are all connected with one conductive structure in a one-to-one correspondence mode.
14. The test structure as claimed in claim 13, wherein any one of the word lines is defined as a target word line, and adjacent word lines on both sides of the target word line are respectively defined as a first word line and a second word line; the conductive structure corresponding to the target word line is a first conductive structure, the conductive structure corresponding to the first word line is a second conductive structure, the conductive structure corresponding to the second word line is a third conductive structure, the conductive structure corresponding to the conductive contact plug is a fourth conductive structure, the conductive structure corresponding to the bit line is a fifth conductive structure, and the conductive structure corresponding to the body lead-out area is a sixth conductive structure; the first conductive structure, the second conductive structure, the third conductive structure, the fourth conductive structure, the fifth conductive structure and the sixth conductive structure are all made of tungsten.
15. The test structure as claimed in claim 13, wherein the word lines are equally spaced apart from each other, and the second conductive structure is spaced apart from the third conductive structure by a distance greater than a distance between two adjacent word lines.
CN202210398929.9A 2022-04-15 2022-04-15 Electrical test method and test structure of semiconductor device Pending CN114783500A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116540048A (en) * 2023-03-13 2023-08-04 长鑫存储技术有限公司 Semiconductor test method and test structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116540048A (en) * 2023-03-13 2023-08-04 长鑫存储技术有限公司 Semiconductor test method and test structure
CN116540048B (en) * 2023-03-13 2023-12-01 长鑫存储技术有限公司 Semiconductor test method and test structure

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