CN112420633A - 半导体装置及逆变器 - Google Patents

半导体装置及逆变器 Download PDF

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Publication number
CN112420633A
CN112420633A CN202010824330.8A CN202010824330A CN112420633A CN 112420633 A CN112420633 A CN 112420633A CN 202010824330 A CN202010824330 A CN 202010824330A CN 112420633 A CN112420633 A CN 112420633A
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electrode pad
main surface
semiconductor device
control electrode
collector
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CN112420633B (zh
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佐藤克己
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

得到能够减小热破坏的发生风险的半导体装置以及逆变器。半导体基体(1)具有彼此相反侧的第1主面和第2主面。第1主电极(2)形成于第1主面，与半导体基体(1)电连接。第1控制电极焊盘(3)形成于第1主面，在第1控制电极焊盘(3)与半导体基体(1)之间存在第1绝缘膜(14)。外周耐电压保持构造(4)在第1主面形成于将第1主电极(2)和第1控制电极焊盘(3)包围的外周区域。第2主电极(5)形成于第2主面，与半导体基体(1)电连接。第2控制电极焊盘(6)形成于第2主面，在第2控制电极焊盘(6)与半导体基体(1)之间存在第2绝缘膜(29)。第2控制电极焊盘(6)被第2主电极(5)包围。

Description

半导体装置及逆变器
技术领域
本发明涉及在阴极侧和阳极侧各自具有控制电极的双栅极构造的半导体装置以及将该半导体装置用作开关元件的逆变器。
背景技术
将AC-DC转换器和DC-AC逆变器进行组合，变换为任意频率和电压的电路被称为逆变器，其中，该AC-DC转换器将交流变换为直流。由于逆变器能够可变地控制输出电压及其频率，所以能够自由地控制电动机的旋转速度，被用作电动机的可变速装置。
作为逆变器所用的开关元件，以前在小容量区域使用双极晶体管，在中大容量区域使用栅控截止晶闸管(Gate Turn-Off thyristor：GTO)。目前，主要使用兼顾由使用了MOS栅极构造的电压控制实现的控制容易性、高速性和作为双极器件的主要特征的大电流通电性能这两者的绝缘栅型双极晶体管(Insulated Gate Bipolar Transistor：IGBT)。
特别地，为了改善双极器件的通断性能，设计了双栅极构造的半导体装置。目前，正在进行将双栅极构造应用于IGBT的双栅极IGBT的研究。双栅极IGBT为如下构造，即，在发射极侧主面形成栅极电极，在相反侧的集电极侧主面形成控制栅极电极(例如，参照专利文献1)。
专利文献1：日本特开2010-123667号公报
在发射极侧主面的外周区域形成有外周耐电压保持构造。外周耐电压保持构造的电极不与外部引出电极连接，而是被导热率低的保护膜覆盖。另一方面，在集电极侧主面的外周部配置有控制栅极电极焊盘，该控制栅极电极焊盘经由焊料而与引线框电连接。在控制栅极电极焊盘与p+型集电极层之间存在导热率低的栅极绝缘膜。另外，由于只有控制栅极电极焊盘的外周的一条边与集电极(collector)电极(electrode)相对，通过绝缘膜而被绝缘分离，因此难以从控制栅极电极焊盘侧向集电极电极侧散热。因此，在现有的双栅极IGBT中，无论是发射极侧主面还是集电极侧主面，外周区域都成为难以散热的构造。这样，由于散热效率良好的主电极的形成区域和难以散热的外周区域混合存在，因此在产生大的损耗时容易陷入温度不均匀状态。特别地，在产生急剧的温度变化的短路事故发生时，在外周区域或栅极电极焊盘附近发生热破坏的风险升高。
发明内容
本发明就是为了解决上述这样的课题而提出的，其目的在于得到能够减小热破坏的发生风险的半导体装置以及逆变器。
本发明涉及的半导体装置的特征在于，具有：半导体基体，其具有彼此相反侧的第1主面和第2主面；第1主电极，其形成于所述第1主面，与所述半导体基体电连接；第1控制电极焊盘，其形成于所述第1主面，经由第1绝缘膜而与所述半导体基体连接；外周耐电压保持构造，其在所述第1主面形成于将所述第1主电极和所述第1控制电极焊盘包围的外周区域；第2主电极，其形成于所述第2主面，与所述半导体基体电连接；以及第2控制电极焊盘，其形成于所述第2主面，经由第2绝缘膜而与所述半导体基体连接，所述第2控制电极焊盘被所述第2主电极包围。
发明的效果
在本发明中，第2控制电极焊盘被作为散热路径的第2主电极包围。由此，容易从第2控制电极焊盘的周围散热，因此能够减小温度的不均匀。其结果，能够提高半导体装置的动作性能，减小热破坏的发生风险。
附图说明
图1是实施方式1涉及的半导体装置的发射极侧主面的俯视图。
图2是实施方式1涉及的半导体装置的集电极侧主面的俯视图。
图3是沿图1的I-II的剖面图。
图4是对比例涉及的半导体装置的集电极侧主面的俯视图。
图5是沿图4的I-II的剖面图。
图6是实施方式2涉及的半导体装置的发射极主面侧的俯视图。
图7是实施方式2涉及的半导体装置的集电极侧主面的俯视图。
图8是表示实施方式3涉及的逆变器的图。
标号的说明
1半导体基体，2发射极电极(第1主电极)，3栅极电极焊盘(第1控制电极焊盘)，4外周耐电压保持构造，5集电极电极(第2主电极)，6控制栅极电极焊盘(第2控制电极焊盘)，7n+型集电极层(集电极层)，9n-型漂移层(漂移层)，10p型基极层(基极层)，11沟槽(第1沟槽)，13n+型发射极区域(发射极区域)，14栅极绝缘膜(第1绝缘膜)，15栅极电极，28沟槽(第2沟槽)，29栅极绝缘膜(第2绝缘膜)，30控制栅极电极，41键合导线
具体实施方式
参照附图，对实施方式涉及的半导体装置及逆变器进行说明。对相同或相应的结构要素标注相同的标号，有时省略重复说明。
实施方式1.
图1是实施方式1涉及的半导体装置的发射极侧主面的俯视图。半导体基体1是在半导体衬底之上对半导体层进行外延生长而成的，具有彼此相反侧的发射极侧主面和集电极侧主面。在半导体基体1的发射极侧主面形成有发射极侧IGBT区域和将发射极侧IGBT区域包围的外周区域，其中，该发射极侧IGBT区域具有发射极电极2和栅极电极焊盘3。发射极电极2以包围栅极电极焊盘3的三个边的方式配置。在外周区域形成有外周耐电压保持构造4。
图2是实施方式1涉及的半导体装置的集电极侧主面的俯视图。在集电极侧主面形成了具有集电极电极5和控制栅极电极焊盘6的集电极侧IGBT区域。在本实施方式中，控制栅极电极焊盘6配置于芯片中央，外周全部被集电极电极5包围。集电极电极5以将除了控制栅极电极焊盘6以外的集电极侧主面的区域覆盖的方式配置。因此，在与外周耐电压保持构造4相对的集电极侧主面的外周区域全部配置有集电极电极5。
图3是沿图1的I-II的剖面图。在p+型集电极层7之上形成有由高杂质浓度的n+型杂质层构成的场截止层8。在场截止层8之上形成有与场截止层8相比杂质浓度低的n-型漂移层9。在n-型漂移层9之上形成有规定厚度的p型基极层10。
以贯穿p型基极层10而到达n-型漂移层9的方式形成有多个沟槽11。多个沟槽11以规定的间距(间隔)配置，成为与图3的进深方向、即纸面垂直方向平行地延伸的条带构造，或者在平行地延伸之后，在其前端部绕引的环状构造。
通过多个沟槽11将p型基极层10分隔成多个。其中的一部分是构成沟道区域的p沟道层12。n+型发射极区域13在p沟道层12的表层部形成于沟槽11的侧面。n+型发射极区域13与n-型漂移层9相比杂质浓度高，在p型基极层10内终止。
栅极绝缘膜14以覆盖各沟槽11的内壁表面的方式形成。由掺杂多晶硅等构成的栅极电极15隔着栅极绝缘膜14而形成在沟槽11内。以覆盖栅极电极15的上方的方式在半导体基体1的发射极侧主面形成有绝缘膜16。
p型扩散层18在n-型漂移层9之上以包围p型基极层10的方式形成。掺杂多晶硅层17隔着绝缘膜16而形成在p型扩散层18之上。掺杂多晶硅层17与栅极电极15电连接，该掺杂多晶硅层17通过在绝缘膜16形成的接触孔19而与栅极电极焊盘3电连接。因此，栅极电极15通过掺杂多晶硅层17和栅极电极焊盘3而与外部电连接。
发射极电极2形成于绝缘膜16之上。发射极电极2通过在绝缘膜16形成的接触孔20而与n+型发射极区域13以及p沟道层12电连接。这样，构成了发射极侧IGBT区域。
在包围发射极侧IGBT区域的外周区域，在n-型漂移层9之上形成有多个p型保护环层21作为多重环构造。p型扩散层18及p型保护环层21形成得比p型基极层10深。多个外周电极22在绝缘膜16之上与多个p型保护环层21各自对应地配置。多个p型保护环层21通过在绝缘膜16形成的接触孔23而分别与多个外周电极22电连接。多个外周电极22彼此电分离，与p型保护环层21同样地成为多重环构造。
以包围p型保护环层21的方式在n-型漂移层9的表层部形成有n+型层24。电极25形成于n+型层24之上，彼此电连接。n+型层24和电极25构成等电位环(EQR)构造。在外周区域未进行电连接的部位被保护膜26覆盖。这样，构成了发射极侧主面的外周区域的外周耐电压保持构造4。
在p+型集电极层7的集电极侧的表面选择性地形成有高浓度的n+型集电极层27。多个沟槽28以贯穿p+型集电极层7、n+型集电极层27以及场截止层8而到达n-型漂移层9的方式形成。多个沟槽28隔开规定间隔，例如等间隔地配置成条带状。
栅极绝缘膜29以覆盖各沟槽28的内壁表面的方式形成。由掺杂多晶硅等构成的控制栅极电极30隔着栅极绝缘膜29而形成在沟槽28内。
所有的控制栅极电极30在另外的截面彼此电连接。集电极电极5与p+型集电极层7及n+型集电极层27接触而电连接。以覆盖控制栅极电极30的方式在半导体基体1的集电极侧主面形成有绝缘膜31。
控制栅极电极焊盘6通过在绝缘膜31形成的接触孔32而与掺杂多晶硅层33电连接。掺杂多晶硅层33通过在绝缘膜31形成的接触孔34而与控制栅极电极30连接。集电极电极5以将周边被保护膜35覆盖的控制栅极电极焊盘6包围的方式配置，通过绝缘膜31及保护膜35而与控制栅极电极30分离。这样，构成了集电极侧IGBT区域。
如上所述，构成了本实施方式涉及的双栅极IGBT。双栅极IGBT如下所述与外部连接。发射极电极2经由焊料36而与外部引出电极即引线框37连接。集电极电极5经由焊料38而与外部引出电极即引线框39连接。集电极-发射极间的电流通过引线框39、焊料38、集电极电极5、半导体基体1、发射极电极2、焊料36及引线框37而流动。
通过将键合导线40接合至栅极电极焊盘3，从而实现栅极电极15与外部之间的电连接。通过将键合导线41接合至控制栅极电极焊盘6，从而能够进行向控制栅极电极30的电压施加。双栅极IGBT整体通过树脂等的覆盖而被封装，外部引出电极的一部分凸出至封装件之外而成为与设备的触点。另外，由于发射极电极2及集电极电极5经由焊料36、38而与外部引出电极即引线框37、39连接，因此，能够确保大的散热面积、在数微秒内进行热扩散的区域的总体积、热容量。
接下来，对本实施方式涉及的半导体装置的动作进行说明。首先，在断开状态下，由于未对栅极电极15施加栅极电压，因此在p沟道层12不形成反转层。因此，集电极-发射极间的电流断开。然后，如果对栅极电极15施加正的栅极电压，则在p沟道层12形成反转层，在集电极-发射极间流过电流而成为接通状态。
在该动作中，如果对控制栅极电极30施加相对于集电极电压为正的电压(例如电压V＞0)，则该电压经由栅极绝缘膜29而在p+型集电极层7形成n沟道层。n+型集电极层7、n沟道层、场截止层8成为导通路径，由此，使由p+型集电极层7和场截止层8构成的pn结的偏置电位下降。因此，在接通状态时，从p+型集电极层7朝向n+型发射极区域13侧注入的空穴的注入量减少。另外，由n+型集电极层7、n沟道层、场截止层8构成的导通路径在截止动作时成为在n-型漂移层9积蓄的电子向集电极电极5的流出路径。因此，在n-型漂移层9积蓄的电子的消失变快。因此，作为元件特性，能够增大稳态损耗并且降低通断损耗。
另一方面，如果对控制栅极电极30施加相对于集电极电压为负的电压(例如电压V＜0)，则该电压经由栅极绝缘膜29而影响成为集电极区域的p+型集电极层7和场截止层8。由此，在p+型集电极层7内，向空穴被积蓄起来的方向推进。在场截止层8，向电子减少的方向推进。因此，在接通状态时，从p+型集电极层7朝向n+型发射极区域13侧注入的空穴的注入量增加。因此，作为元件特性，能够增大通断损耗并且降低稳态损耗。
如上所述，能够通过控制栅极电极30而调整成为IGBT的集电极区域的p+型集电极层7内的空穴的量和场截止层8内的电子的量。因此，能够在器件制造工艺结束之后，将半导体装置的稳态损耗、通断损耗调整为最佳值。另外，应用设计者或者装置使用者能够通过控制施加于控制栅极电极30的电压而进行基于驱动频率等使用条件的最佳的损耗设定。另外，不需要器件制造条件的配合、应用评价的反复试错等耗时的定制元件制造工序开发。并且，即使在驱动频率及温度在动作时发生变化的情况下，也能够通过调整施加于控制栅极电极30的电压，从而将损耗特性及浪涌特性等器件性能设定为最适于其频率及温度的值。
接下来，与对比例进行比较，对本实施方式的效果进行说明。图4是对比例涉及的半导体装置的集电极侧主面的俯视图。图5是沿图4的I-II的剖面图。在对比例中，控制栅极电极焊盘6配置于集电极侧主面的外周区域。仅控制栅极电极焊盘6的外周的一条边与集电极电极5相对，通过绝缘膜31及保护膜35而被绝缘分离。控制栅极电极焊盘6经由焊料42而与外部引出电极即引线框43电连接。
在集电极侧主面，由损耗产生的半导体基体1的热以与半导体基体1电连接的集电极电极5、与集电极电极5连接的引线框39为散热路径而散热。因此，半导体基体1与集电极电极5的接触面积以及集电极电极5与引线框39的接触面积越大，集电极电极5与引线框39的导热率越大，则越高效地散热。另一方面，在控制栅极电极焊盘6与半导体基体1之间存在导热率小的栅极绝缘膜29。因此，难以从控制栅极电极焊盘6散热。
在对比例中，由于仅控制栅极电极焊盘6的外周的一条边与集电极电极5相对，因此难以从控制栅极电极焊盘6侧向集电极电极5侧散热。与此相对，在本实施方式中，控制栅极电极焊盘6被作为散热路径的集电极电极5包围。由此，容易从控制栅极电极焊盘6的周围散热，因此能够减小温度的不均匀。其结果，能够提高半导体装置的动作性能，减小热破坏的发生风险。
另外，由于在控制栅极电极焊盘6与半导体基体1之间存在导热率低的栅极绝缘膜29，因此半导体基体1的热难以从控制栅极电极焊盘6散热。因此，需要使控制栅极电极焊盘6的区域的热从发射极侧主面散热。具体地说，如果与控制栅极电极焊盘6相对的发射极侧主面的区域的大于或等于一半配置于发射极电极2区域外，则向发射极电极2的散热下降，开始影响IGBT性能，短路耐量成为小于或等于大致三分之二。
与此相对，在本实施方式中，控制栅极电极焊盘6配置于半导体基体1的集电极侧主面的中央部。因此，与控制栅极电极焊盘6相对的发射极侧主面的区域不是难以散热的外周区域，而是发射极电极2的形成区域。由于发射极电极2与n+型发射极区域13电连接，因此发射极电极2的形成区域的散热性优良。由此，能够确保良好的散热。
此外，由于还从栅极电极焊盘3经由键合导线40而进行一定程度的散热，因此与控制栅极电极焊盘6相对的发射极侧主面的区域也可以是栅极电极焊盘3的形成区域。
即使在短路事故时能够安全地、不发生热破坏地实施电流切断保护，在保护动作刚刚完成之后，电源电压VCE也会施加于IGBT。在发生了温度不均匀的IGBT高温部处流过由电源电压引起的泄漏电流，泄漏电流与电源电压之积作为损耗而产生，成为热而被消耗。如果温度高，则泄漏电流变大，如果由泄漏电流引起的损耗大至大于或等于散热能力，则产生正反馈，有时导致热破坏。因此，就IGBT而言，提供抑制温度不均匀的构造是重要的。特别地，在形成了用于阻止电压的外周耐电压保持构造4的外周区域，泄漏电流密度容易变得比发射极电极2的形成区域大。并且，在发射极侧主面，外周区域几乎不具有高效的散热路径。与此相对，在本实施方式中，在与外周耐电压保持构造4相对的集电极侧主面的外周区域配置有集电极电极5。集电极电极5经由焊料38而与外部引出电极即引线框39电连接。因此，集电极侧主面的外周区域也具有散热路径。
另外，键合导线41作为外部引出电极而与控制栅极电极焊盘6接合。与如对比例那样对引线框43进行焊接的情况相比，键合导线41与控制栅极电极焊盘6的对位精度高。因此，能够减小对位偏差，所以能够使控制栅极电极焊盘6的尺寸小型化。由此，能够使集电极电极5的尺寸相对地变大，因此能够提高从集电极电极5的散热，能够减小由控制栅极电极焊盘6引起的温度不均匀。
实施方式2.
图6是实施方式2涉及的半导体装置的发射极主面侧的俯视图。图7是实施方式2涉及的半导体装置的集电极侧主面的俯视图。控制栅极电极焊盘6的尺寸和配置与实施方式1不同。控制栅极电极焊盘6的尺寸是1.2mm×1.5mm的长方形，长方形的一条边位于芯片外周端。
向集电极电极5的散热效率的指标是通过用控制栅极电极焊盘6的单位周长除以控制栅极电极焊盘6的单位面积而计算出的。能够通过控制栅极电极焊盘6的小型化而使该指标增加，实现快速的散热，减小温度的不均匀。另外，由于控制栅极电极焊盘6的平面形状为四边形，因此即使一条边位于未被集电极电极5包围的芯片外周端，也会从被集电极电极5包围的三条边向集电极电极5侧散热。
此外，控制栅极电极焊盘6的平面形状不限于是四边形，也可以是半圆形、扇形或大于或等于五边形的多边形。无论在哪种情况下，只要控制栅极电极焊盘6的外周的除了一条边以外被集电极电极5包围即可。由此，从被包围的部分向集电极电极5散热。具体地说，优选控制栅极电极焊盘6的外周的大于或等于75％被集电极电极5包围。在这种情况下，只要控制栅极电极焊盘6能够小型化，则会得到与包围整周同等的效果。例如，在如本实施方式那样控制栅极电极焊盘6被小型化为1.2mm×1.5mm的情况下，不会产生对IGBT性能带来影响的程度的温度不均匀。
另外，在与栅极电极焊盘3相对的区域配置有集电极电极5，在与控制栅极电极焊盘6相对的区域配置有发射极电极2。即，栅极电极焊盘3与控制栅极电极焊盘6是以在俯视观察时投影不重叠的方式而配置的。因此，栅极电极焊盘3与控制栅极电极焊盘6未配置于彼此相对的区域。由此，能够防止热在散热性差的栅极电极焊盘3与控制栅极电极焊盘6之间积聚。
实施方式1、2的双栅极构造不限于能够进行短路保护自切断动作的IGBT，也能够应用于GTO这样的不具有电流饱和特性而无法进行短路保护自切断的器件。例如，如果在由浪涌电流引起的GTO的温度升高的影响下刚刚产生了温度不均匀之后施加断开电压，则可能发生由泄漏电流引起的热失控。因此，减小温度不均匀对GTO也是重要的。但是，由于GTO的动作频率比IGBT低1至2个数量级，因此本实施方式的影响不大。另一方面，对于需要用于短路保护的自切断动作的晶体管而言，数微秒内的温度不均匀会影响性能，因此实施方式1、2的结构特别有效。
此外，半导体基体1不限于由硅形成，也可以由与硅相比带隙大的宽带隙半导体形成。宽带隙半导体例如是碳化硅、氮化镓类材料、或金刚石。由这样的宽带隙半导体形成的半导体装置由于耐电压性、容许电流密度高，因此能够小型化。通过使用该小型化的半导体装置，从而组装了该半导体装置的半导体模块也能够小型化、高集成化。另外，由于半导体装置的耐热性高，因此能够使散热器的散热鳍片小型化，能够使水冷部空冷化，因而能够使半导体模块进一步小型化。另外，由于半导体装置的电力损耗低且高效，因此能够使半导体模块高效化。
实施方式3.
图8是表示实施方式3涉及的逆变器的图。AC-DC转换器100将电源101的交流电力变换为直流电力。AC-DC转换器100具有二极管D1、D2、D3、D4和电源平滑电容器C1。DC-AC逆变器102将从AC-DC转换器100输出的直流电力变换为交流电力，供给至电动机103的线圈。DC-AC逆变器102具有IGBT等开关元件Q1～Q6、和与它们逆并联连接的续流二极管D5～D10。驱动电路104对开关元件Q1～Q6进行驱动。驱动电路104具有信号处理部105和输出部106。信号处理部105具有微型计算机107、和对来自微型计算机107的信号进行处理的信号处理电路105a～105f。输出部106具有将来自信号处理电路105a～105f的控制信号分别输出至开关元件Q1～Q6的输出电路106a～106f。通过使用实施方式1或2的半导体装置作为开关元件Q1～Q6，从而能够减小热破坏的发生风险，因此能够得到可靠性高的逆变器。

Claims (11)

1.一种半导体装置，其特征在于，具有：
半导体基体，其具有彼此相反侧的第1主面和第2主面；
第1主电极，其形成于所述第1主面，与所述半导体基体电连接；
第1控制电极焊盘，其形成于所述第1主面，在所述第1控制电极焊盘与所述半导体基体之间存在第1绝缘膜；
外周耐电压保持构造，其在所述第1主面形成于将所述第1主电极和所述第1控制电极焊盘包围的外周区域；
第2主电极，其形成于所述第2主面，与所述半导体基体电连接；以及
第2控制电极焊盘，其形成于所述第2主面，在所述第2控制电极焊盘与所述半导体基体之间存在第2绝缘膜，
所述第2控制电极焊盘被所述第2主电极包围。
2.根据权利要求1所述的半导体装置，其特征在于，
与所述第2控制电极焊盘相对的所述第1主面的区域不是所述外周区域。
3.根据权利要求2所述的半导体装置，其特征在于，
与所述第2控制电极焊盘相对的所述第1主面的区域是所述第1主电极的形成区域。
4.根据权利要求1所述的半导体装置，其特征在于，
所述第2控制电极焊盘的除了一条边以外被所述第2主电极包围。
5.根据权利要求1至4中任一项所述的半导体装置，其特征在于，
在与所述外周耐电压保持构造相对的所述第2主面的区域配置有所述第2主电极。
6.根据权利要求1至5中任一项所述的半导体装置，其特征在于，
在所述第2控制电极焊盘接合有键合导线。
7.根据权利要求1至6中任一项所述的半导体装置，其特征在于，
所述第1控制电极焊盘和所述第2控制电极焊盘未配置于彼此相对的区域。
8.根据权利要求1至7中任一项所述的半导体装置，其特征在于，
还具有在所述半导体基体形成的晶体管。
9.根据权利要求8所述的半导体装置，其特征在于，
所述晶体管具有：
第1导电型的集电极层，其与所述第2主电极电连接；
第2导电型的漂移层，其形成于所述集电极层之上；
第1导电型的基极层，其形成于所述漂移层之上；
第1沟槽，其贯穿所述基极层；
栅极电极，其隔着所述第1绝缘膜而形成在所述第1沟槽内，与所述第1控制电极焊盘电连接；
第2导电型的发射极区域，其在所述基极层形成于所述第1沟槽的侧面，与所述第1主电极电连接；
第2沟槽，其形成于所述集电极层；以及
控制栅极电极，其隔着所述第2绝缘膜而形成在所述第2沟槽内，与所述第2控制电极焊盘电连接。
10.根据权利要求1至9中任一项所述的半导体装置，其特征在于，
所述半导体基体由宽带隙半导体形成。
11.一种逆变器，其特征在于，将权利要求1至10中任一项所述的半导体装置用作开关元件。
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