CN112382599B - Temporary bonding and debonding method of semiconductor device and semiconductor device - Google Patents
Temporary bonding and debonding method of semiconductor device and semiconductor device Download PDFInfo
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8334—Bonding interfaces of the layer connector
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Abstract
A method for temporary bonding and debonding of a semiconductor device and a semiconductor device are disclosed. The temporary bonding and debonding method of the semiconductor device comprises the following steps: forming a first metal layer on a first wafer, wherein a device structure is formed in the first wafer and the first metal layer is formed on one side, close to the device structure, of the first wafer; forming a second metal layer corresponding to the first metal layer on the second wafer; bonding a second metal layer to the first metal layer such that the second wafer is bonded to the first wafer; performing a back process on one side of the first wafer far away from the device structure; and performing debonding through electrochemical anodic metal dissolution to separate the first wafer from the second wafer.
Description
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a method for temporarily bonding and debonding a semiconductor device and a semiconductor device.
Background
In a semiconductor integration process, after device layer processing is performed on the front surface of a wafer, related processes are sometimes performed on the back surface of the wafer. In order to avoid the situation that the wafer is broken or bent and deformed in the back process, the wafer can be temporarily bonded on another wafer or a slide with similar diameter before the back process is carried out on the wafer, so that the wafer is supported. After the wafer is subjected to a backside process, the wafer is debonded from another wafer or carrier to effect separation of the two.
Temporary bonding of the wafer to another wafer or carrier may be achieved using temporary bonding materials, for example, organic materials such as temporary bonding glue or photoresist may be used. However, such temporary bonding materials have poor high temperature resistance and poor compatibility with a backside process after bonding. To achieve debonding, either mechanical debonding or solvent debonding may be used. However, the shear force during mechanical debonding tends to damage the wafer, resulting in lower yield. In the process of dissolving and bonding by the solvent, the temporary bonding glue is slowly dissolved by the solvent from the edge of the wafer, so that the time for the solvent to reach the center of the wafer is long, and the bonding dissolving efficiency is low.
Disclosure of Invention
It would be advantageous to provide a mechanism that alleviates, mitigates or even eliminates one or more of the above-mentioned problems.
According to some embodiments of the present disclosure, there is provided a method of temporary bonding and debonding of a semiconductor device, comprising: forming a first metal layer on a first wafer, wherein a device structure is formed in the first wafer and the first metal layer is formed on one side, close to the device structure, of the first wafer; forming a second metal layer corresponding to the first metal layer on the second wafer; bonding a second metal layer to the first metal layer such that the second wafer is bonded to the first wafer; performing a back process on one side of the first wafer far away from the device structure; and debonding by electrochemical anodic metal dissolution to separate the first wafer from the second wafer.
According to some embodiments of the present disclosure, there is provided a semiconductor device manufactured by the method described above.
These and other aspects of the disclosure will be apparent from and elucidated with reference to the embodiments described hereinafter.
Drawings
Further details, features and advantages of the disclosure are disclosed in the following description of exemplary embodiments, taken in conjunction with the accompanying drawings, in which:
fig. 1 is a flowchart of a method of temporary bonding and debonding of a semiconductor device according to an exemplary embodiment of the present disclosure;
fig. 2A through 2F are schematic diagrams of example structures of semiconductor devices formed in various steps of a temporary bonding and debonding method of semiconductor devices according to example embodiments of the present disclosure; and
fig. 3A through 3C are schematic diagrams of debonding by electrochemical anodic metal dissolution according to exemplary embodiments of the present disclosure.
Detailed Description
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
Spatially relative terms such as "below …," "below …," "lower," "below …," "above …," "upper," and the like may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" or "under" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" may encompass both an orientation above … and below …. Terms such as "before …" or "before …" and "after …" or "next to" may similarly be used, for example, to indicate the order in which light passes through the elements. The devices may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items, and the phrase "at least one of a and B" refers to a alone, B alone, or both a and B.
It will be understood that when an element or layer is referred to as being "on," "connected to," "coupled to" or "adjacent to" another element or layer, it can be directly on, connected to, coupled to or adjacent to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to," or "directly adjacent to" another element or layer, there are no intervening elements or layers present. However, neither "on … nor" directly on … "should be construed as requiring that one layer completely cover an underlying layer in any event.
Embodiments of the present disclosure are described herein with reference to schematic illustrations (and intermediate structures) of idealized embodiments of the present disclosure. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present disclosure should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Exemplary embodiments of the present disclosure provide a method of temporary bonding and debonding of a semiconductor device. In this method, temporary bonding between wafers may be achieved by metal-metal bonding, and debonding by electrochemical anodic metal dissolution. Therefore, the bonding strength of temporary bonding is high, the high-temperature resistance is good, and the bonding debonding efficiency can be improved.
As used herein, the term "substrate" may refer to a substrate of a diced wafer, or may refer to a substrate of an unslit wafer. Similarly, the terms chip and die may be used interchangeably unless such interchange causes a conflict. It should be understood that the term "layer" includes films and, unless otherwise specified, should not be construed as indicating a vertical or horizontal thickness.
Fig. 1 is a flow chart of a method 100 of temporary bonding and debonding of a semiconductor device according to an exemplary embodiment of the present disclosure, and fig. 2A-2F are schematic diagrams of an example structure of a semiconductor device formed in various steps of the method of temporary bonding and debonding of a semiconductor device according to an exemplary embodiment of the present disclosure. Methods of temporary bonding and debonding of semiconductor devices according to exemplary embodiments of the present disclosure are described below with reference to fig. 1 and 2A-2F.
As shown in fig. 1 and 2A, in step 110, a first metal layer 214 is formed on the first wafer 210. Device structures 211 are formed in first wafer 210 and first metal layer 214 is formed on a side of first wafer 210 proximate to device structures 211.
The first wafer 210 may be any type of wafer. For example, first wafer 210 may include a substrate and device structures 211 formed on the substrate. The substrate may be made of any suitable material, for example at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and the like. Further, the substrate may be an N-type substrate or a P-type substrate. As used herein, the term "wafer" may refer to a diced wafer, or may refer to an unsingulated wafer. Device structure 211 may be any semiconductor device structure formed by a semiconductor process. For example, device structure 211 may be a passive device, an active device, a MEMS (Micro Electro Mechanical Systems) device, an interconnect structure, or the like.
According to some embodiments, the method according to an exemplary embodiment of the present disclosure may further include forming a passivation layer 212 on the first wafer 210 before forming the first metal layer 214 on the first wafer 210. Forming the passivation layer 212 and the first metal layer 214 on the first wafer 210 may include: forming a passivation material layer on a side of the first wafer 210 close to the device structure 211; forming a first metal material layer on the passivation material layer; and sequentially patterning the first metallic material layer and the passivation material layer to form a passivation layer 212 and a first metallic layer 214. The first metallic material layer and the passivation material layer may be patterned, for example, by photolithography and etching processes, but the disclosure is not limited thereto. Any suitable process that is capable of patterning the first metallic material layer and the passivation material layer may be selected according to the particular application and/or requirements.
The passivation layer 212 may be formed of a passivation material such as an oxide, nitride, or oxynitride. By forming passivation layer 212, a metal wiring electrically connected to device structure 211 can be prevented from directly contacting first metal layer 214, thereby preventing the occurrence of a short circuit. The passivation layer 212 may also be formed of a good temperature resistant polymer, such as polyimide, according to some embodiments. By selecting a polymer with good temperature resistance to form the passivation layer, damage to the passivation layer during formation of the first metal layer and during bonding of the first metal layer and the second metal layer can be avoided.
The passivation layer may be formed by a deposition process. It should be understood that other processes are possible and not limited herein.
In some examples, the first metal layer may be formed on the passivation layer by any suitable process. For example, evaporation, sputtering, or the like.
It should be understood that the passivation layer may be omitted in other possible embodiments, and is not limited herein. For convenience of description, an example including the passivation layer 212 is described below in the method of temporary bonding and debonding of a semiconductor device according to an exemplary embodiment of the present disclosure with reference to fig. 2A to 2F.
As shown in fig. 2A, in some embodiments, the passivation layer 212 and the first metal layer 214 expose a pad region 213 formed on the first wafer 210. This helps to enable device structures 211 formed in first wafer 210 to be conveniently electrically connected to other structures after debonding.
As shown in fig. 1 and 2B, in step 120, a second metal layer 218 corresponding to the first metal layer 214 is formed on the second wafer 216
In some examples, the second metal layer 218 may be formed on the second wafer 216 by any suitable process. For example, evaporation, sputtering, or the like.
The location of the second metal layer 218 formed on the second wafer 216 may correspond to the location of the first metal layer 214. For example, the second metal layer 218 may be formed by forming a second metal material layer on the second wafer 216 and patterning the second metal material layer. In some examples, the second metal material layer formed on the second wafer 216 may not be patterned, and the formed second metal material layer may be directly used as the second metal layer 218, so as to save the process flow. The second wafer 216 can be used as a support wafer to enable support of the first wafer 210.
According to some embodiments, the material of the second metal layer 218 may be the same as the material of the first metal layer 214, for example, the material forming the first metal layer 214 and the second metal layer 218 may be aluminum. Aluminum metal has good compatibility with semiconductor processes, and the aluminum-aluminum metal bond has high bonding strength and good high temperature resistance, which is particularly advantageous in the case where other high temperature processes are required for the first wafer 210 after bonding. Although aluminum may be selected as the material forming the first and second metal layers 214 and 218, the present disclosure is not limited thereto. Any metallic material capable of achieving metal-metal bonding and capable of being debonded by electrochemical anodic metal dissolution may be selected depending on the particular application and/or requirements.
In some embodiments, the material of the second metal layer 218 may also be different from the material of the first metal layer 214, for example, the material of the first metal layer 214 may be aluminum, and the material of the second metal layer 218 may be aluminum-copper alloy, aluminum-silicon-copper alloy, and the like, without limitation.
The second wafer 216 may be formed of a conductive material or a non-conductive material. For example, the second wafer 216 may be formed of silicon, glass, or a ceramic material. According to some embodiments, the second wafer 216 may be formed of doped low resistivity silicon to be conductive.
In the case where the second wafer 216 is formed of a non-conductive material, as shown in fig. 2B', the method of temporarily bonding and debonding a semiconductor device according to an exemplary embodiment of the present disclosure may further include: a third metal layer 217 is formed on the second wafer 216 before a second metal layer 218 corresponding to the first metal layer 214 is formed on the second wafer 216. The corrosion potential of the material forming the third metal layer 217 is higher than the corrosion potential of the material forming the first and second metal layers so that the third metal layer is less susceptible to electrochemical dissolution than the first and second metal layers.
When the material of the first and second metal layers is aluminum, the material of the third metal layer may be a metal having a higher corrosion potential than aluminum, such as chromium or copper. In some examples, the material of the third metal layer may also be an alloy, such as an alloy in which two or more metal crystals form a mechanical mixture or other forms of alloys, and the like.
In the following description, the second wafer structure shown in fig. 2B is mainly described, but it should be understood that the second wafer structure shown in fig. 2B' may also be used.
As shown in fig. 1 and 2C, in step 130, a second metal layer 218 is bonded to the first metal layer 214 such that the second wafer 216 is bonded to the first wafer 210.
Step 130 may be implemented by a bonding process. In the example shown in fig. 2C, the structure shown in fig. 2B is now flipped so that the second metal layer 218 formed on the second wafer 216 in fig. 2B can bond with the first metal layer 214 formed on the first wafer 210. For example, the second metal layer 218 may be bonded to the first metal layer 214 by thermocompression. Fig. 2C shows a schematic diagram after bonding the second metal layer 218 and the first metal layer 214, wherein the metal layer 214/218 is a state after bonding the first metal layer 214 and the second metal layer 218.
According to some embodiments, the thickness of each of the first and second metal layers 214 and 218 may be 0.1 μm to 50 μm.
The bonding temperature for bonding the second metal layer 218 to the first metal layer 214 may be 25 deg.c to 500 deg.c, according to some embodiments. This temperature range generally does not affect device structures 211 of first wafer 210 and bonds first metal layer 214 and second metal layer 218 together well.
As shown in fig. 1 and fig. 2D and 2E, in step 140, a backside process is performed on a side of the first wafer 210 away from the device structure 211.
In this disclosure, any process performed on the side of the first wafer away from the device structure may be referred to as a backside process.
In some embodiments, after bonding second metal layer 218 to first metal layer 214, the temperature of the backside process performed on the side of first wafer 210 away from device structure 211 does not exceed the withstand temperature of the materials forming first metal layer 214 and second metal layer 218. The metal has a higher temperature tolerance, so that wafers using metal-metal bonding are more adaptable to backside processes of various forms and conditions.
According to some exemplary embodiments, after the bonding is completed, the first wafer may be thinned, or other backside processes may be performed according to specific applications and/or requirements, and the like, without limitation.
For example, as shown in fig. 2D, the backside process may include thinning the first wafer 210 on a side of the first wafer 210 away from the device structures 211. The thinned first wafer can exhibit flexibility such as bending and extending, and the like, so that a flexible semiconductor device is formed.
As shown in fig. 2E, according to some embodiments, the backside process may further include forming a protection layer 220 on a side of the first wafer 210 away from the device structure 211 after thinning the first wafer 210.
According to some embodiments, forming the protection layer 220 on the side of the first wafer 210 away from the device structure 211 may include: a protective material layer is formed on a side of the first wafer 210 away from the device structure 211, and the protective material layer is cured to form the protective layer 220. By forming the protective layer, a protective effect can be formed on the thinned first wafer, and the flexible semiconductor device which can be bent or folded after the bonding is released is further facilitated.
According to some embodiments, the protective material layer may include Polyimide (PI). For example, polyimide may be formed on a side of first wafer 210 away from device structure 211 by a spin-on process. The polyimide is then cured at a temperature of about 350 c to form a protective layer.
Although the schematic diagram shown in fig. 2E illustrates the first wafer 210 being thinned and the protective layer 220 being further formed, it should be understood that the protective layer 220 may be formed directly on the first wafer 210 that is not thinned without thinning the first wafer 210.
According to some embodiments, the backside process may include forming another device structure on a side of the first wafer 210 away from the device structure 211. The other device structure may be a device structure formed by any suitable semiconductor process and is not limited herein. For example, the other device structure may be a passive device, an active device, a MEMS device, an interconnect structure, or the like, depending on the particular application and/or requirements.
As shown in fig. 1 and 2F, in step 150, debonding is performed by electrochemical anodic metal dissolution to separate the first wafer 210 from the second wafer 216. Fig. 2F shows the first wafer after debonding.
It should be understood that fig. 2A through 2F are merely schematic diagrams of example structures formed in various steps of a method of temporarily bonding and debonding a semiconductor device according to example embodiments of the present disclosure, and the thicknesses and sizes shown in the figures do not necessarily represent actual thicknesses and sizes.
Fig. 3A through 3C are schematic diagrams of debonding by electrochemical anodic metal dissolution according to exemplary embodiments of the present disclosure.
As shown in fig. 3A, according to some embodiments, the positive pole of the voltage source for electrochemical anodic metal dissolution is connected to the second wafer 216, and the negative pole of the voltage source is connected to the cathode 312, the cathode 312 being immersed in the solution 310 for electrochemical anodic metal dissolution.
According to some embodiments, the second wafer 216 may be formed of a conductive material and the positive electrode of the voltage source is connected to a predetermined location of the second wafer 216, for example, as shown in fig. 3A. In this case, the second wafer 216, which is connected to the positive pole of the voltage source, can be used as an anode in an electrochemical anode metal dissolution process.
According to some embodiments, as shown in fig. 2B' above, the second wafer 216 may also be formed of a non-conductive material, and a third metal layer 217 is formed on the second wafer 216 before a second metal layer 218 corresponding to the first metal layer 214 is formed on the second wafer 216, the corrosion potential of the material forming the third metal layer 217 being higher than the corrosion potential of the material forming the first and second metal layers 214 and 218. In the case where the third metal layer 217 is formed on the second wafer 216, the positive electrode of the voltage source for electrochemical anodic metal dissolution may be connected to the third metal layer 217. In this case, the third metal layer 217 connected to the positive electrode of the voltage source can act as an anode in the electrochemical anode metal dissolution process.
According to some embodiments, the material forming the cathode 312 is an inert material. For example, the cathode 312 may be formed of a material such as platinum, gold, lead, or graphite, or a mixture thereof.
According to some embodiments, the solution 310 for electrochemical anode metal dissolution may be a neutral aqueous electrolyte solution. For example, the neutral electrolyte aqueous solution may be one of the group consisting of: NaCl solution, Na2SO4Solution, MgCl2Solution, KCl solution, K2SO4Solution, KNO3Solution and NaNO3And (3) solution. The neutral solution has less environmental pollution and accords with the current industrial environmental protection trend.
According to some embodiments, the solution used for electrochemical anodic metal dissolution may also be a weakly acidic or a weakly alkaline solution, such as MgSO4Etc., without limitation.
Fig. 3B schematically shows the reaction process of electrochemical anode metal dissolution. As shown in fig. 3B, by using electrochemical anodic metal dissolution, the first metal layer and the second metal layer 214/218 that have been bonded together can be dissolved.
For example, when the material of the first metal layer and the second metal layer is aluminum, during the electrochemical anode metal dissolution process, the anode reaction can generate aluminum ions: al → Al3++3e-The cathodic reaction is capable of producing hydrogen: 2H++2e-→H2。
Unlike conventional solvent dissolution bonding, in the electrochemical anodic metal dissolution process, although metal regions such as pads exposed by the passivation layer 212 and the first metal layer 214 may be soaked in the solution, since these metal regions do not participate in the anodic reaction, dissolution does not occur. This increases the freedom of material selection for the metal regions, such as pads, formed on the first wafer to some extent.
According to some embodiments, as shown in fig. 2B' above, in the case where the third metal layer 217 is formed on the second wafer 216, the voltage applied by the voltage source may be within a predetermined range, at least such that the first metal layer 214 is soluble but the third metal layer 217 is not. For example, when the material of the first and second metal layers is aluminum and the material of the third metal layer is chromium, the voltage of the voltage source is adjusted so that aluminum can be dissolved but chromium is not dissolved during the electrochemical anode metal dissolution process.
Fig. 3C schematically shows the state after the electrochemical anode metal dissolution process is finished. As shown in fig. 3C, the first metal layer 214 and the second metal layer 218 have dissolved, causing the first wafer 210 and the second wafer 216 to debond and separate.
During the electrochemical anodic metal dissolution process as shown in fig. 3A to 3C, the debonding speed of the first wafer 210 and the second wafer 216 may be controlled by appropriately adjusting the voltage value of the voltage source until the first wafer 210 and the second wafer 216 are completely separated.
By performing metal-metal bonding and utilizing electrochemical anodic metal dissolution for debonding, the removal rate of the bonded metal layer can be made high, thereby improving the debonding efficiency. Furthermore, the speed of the debonding may be controlled by selecting the respective materials and adjusting the voltage value of the voltage source for the electrochemical anodic metal dissolution, which helps to achieve better controllability. Compared with a mechanical bonding removal mode, the wafer can be prevented from being damaged due to shearing force by performing bonding removal through electrochemical anode metal dissolution, and the yield is improved.
Methods of temporary bonding and debonding of semiconductor devices according to exemplary embodiments of the present disclosure and various variations thereof are described above with respect to fig. 1, 2A-2F, and 3A-3C. It will be understood that it is not required that all of the described steps or operations be performed in the particular order described, nor that all of the described steps or operations be performed to achieve desirable results. For example, the step of forming the second metal layer on the second wafer may be performed before the step of forming the first metal layer on the first wafer.
According to an embodiment of the present disclosure, there is also provided a semiconductor device, which can be manufactured by the above-described method. Having described embodiments of methods for temporary bonding and debonding of semiconductor devices, the structure of the resulting semiconductor devices will be apparent. Embodiments of the semiconductor device can provide the same or corresponding advantages as method embodiments, and a detailed description of these advantages is omitted for the sake of brevity.
While the disclosure has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative and exemplary and not restrictive; the present disclosure is not limited to the disclosed embodiments. Variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed subject matter, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps not listed, the indefinite article "a" or "an" does not exclude a plurality, and the term "a plurality" means two or more. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
Aspect 1. a method of temporary bonding and debonding of a semiconductor device, comprising:
forming a first metal layer on a first wafer, wherein a device structure is formed in the first wafer and the first metal layer is formed on one side of the first wafer close to the device structure;
forming a second metal layer corresponding to the first metal layer on a second wafer;
bonding the second metal layer to the first metal layer such that the second wafer is bonded to the first wafer;
performing a back surface process on one side of the first wafer far away from the device structure; and
debonding by electrochemical anodic metal dissolution to separate the first wafer from the second wafer.
Aspect 3. the method of aspect 2, wherein the material of the second metal layer is one of the group consisting of: aluminum, aluminum copper, aluminum silicon copper.
Aspect 4 the method of aspect 1, wherein the temperature of the backside process does not exceed a withstand temperature of a material forming the first and second metal layers.
Aspect 5 the method of aspect 1, wherein a positive electrode of a voltage source for the electrochemical anode metal dissolution is connected to the second wafer, and,
wherein the negative pole of the voltage source is connected to a cathode, which is immersed in a solution for metal dissolution of the electrochemical anode.
Aspect 6 the method of aspect 5, wherein the material forming the cathode is an inert material.
Aspect 7 the method of aspect 6, wherein the inert material is one of the group consisting of: platinum, gold, graphite.
Aspect 8 the method of aspect 5, wherein the second wafer is formed of a conductive material and the positive electrode of the voltage source is connected to a predetermined location of the second wafer.
Aspect 9 the method of aspect 5, wherein the second wafer is formed of a non-conductive material, and the method further comprises:
forming a third metal layer on the second wafer before forming the second metal layer corresponding to the first metal layer on the second wafer,
wherein the corrosion potential of the material forming the third metal layer is higher than the corrosion potential of the material forming the first and second metal layers, and the positive electrode of the voltage source is connected to the third metal layer.
Aspect 10 the method of aspect 9, wherein the voltage applied by the voltage source is within a predetermined range such that the first metal layer is soluble but the third metal layer is not.
Aspect 11 the method of aspect 1, wherein the solution used for electrochemical anode metal dissolution is a neutral electrolyte aqueous solution.
The method of aspect 11, aspect 12 wherein the neutral aqueous electrolyte solution is one or more of the group consisting of: NaCl solution, Na2SO4Solution, MgCl2Solution, KCl solution, K2SO4Solution, KNO3Solution and NaNO3And (3) solution.
Aspect 13 the method of aspect 1, further comprising: forming a passivation layer on the first wafer before forming a first metal layer on the first wafer, and
wherein forming the passivation layer and the first metal layer on the first wafer comprises:
forming a passivation material layer on one side of the first wafer close to the device structure;
forming a first metal material layer on the passivation material layer; and
and patterning the first metal material layer and the passivation material layer in sequence to form the passivation layer and the first metal layer.
Aspect 14 the method of aspect 13, wherein the passivation layer and the first metal layer expose a pad region formed on the first wafer.
Aspect 15 the method of aspect 1, wherein the backside processing comprises: and thinning the first wafer on the side of the first wafer far away from the device structure.
The method of aspect 15, wherein the backside processing further comprises: and after the first wafer is thinned, forming a protective layer on one side of the first wafer, which is far away from the device structure.
Aspect 17 the method of aspect 16, wherein forming a protective layer on a side of the first wafer away from the device structure comprises:
forming a protective material layer on one side of the first wafer far away from the device structure; and
and curing the protective material layer to form the protective layer.
Aspect 18 the method of aspect 17, wherein the protective material layer comprises polyimide.
Aspect 19 the method of aspect 1, wherein the backside processing comprises: and forming another device structure on the side of the first wafer far away from the device structure.
Aspect 20 a semiconductor device, wherein the semiconductor device is manufactured by the method of any of aspects 1-19.
Claims (20)
1. A method of temporary bonding and debonding of a semiconductor device, comprising:
forming a first metal layer on a first wafer, wherein a device structure is formed in the first wafer and the first metal layer is formed on one side of the first wafer close to the device structure;
forming a second metal layer corresponding to the first metal layer on a second wafer;
bonding the second metal layer to the first metal layer such that the second wafer is bonded to the first wafer;
performing a back surface process on one side of the first wafer far away from the device structure; and
debonding by electrochemical anodic metal dissolution to separate the first wafer from the second wafer.
2. The method of claim 1, wherein a material forming the first metal layer is aluminum.
3. The method of claim 2, wherein the material of the second metal layer is one of the group consisting of: aluminum, aluminum copper, aluminum silicon copper.
4. The method of claim 1, wherein the temperature of the backside process does not exceed a withstand temperature of a material forming the first and second metal layers.
5. The method of claim 1, wherein a positive electrode of a voltage source for the electrochemical anodic metal dissolution is connected to the second wafer, and,
wherein the negative pole of the voltage source is connected to a cathode, which is immersed in a solution for metal dissolution of the electrochemical anode.
6. The method of claim 5, wherein the material forming the cathode is an inert material.
7. The method of claim 6, wherein the inert material is one of the group consisting of: platinum, gold, graphite.
8. The method of claim 5, wherein the second wafer is formed of a conductive material and the positive electrode of the voltage source is connected to a predetermined location of the second wafer.
9. The method of claim 5, wherein the second wafer is formed of a non-conductive material, and further comprising:
forming a third metal layer on the second wafer before forming the second metal layer corresponding to the first metal layer on the second wafer,
wherein the corrosion potential of the material forming the third metal layer is higher than the corrosion potential of the material forming the first and second metal layers, and the positive electrode of the voltage source is connected to the third metal layer.
10. The method of claim 9, wherein the voltage applied by the voltage source is within a predetermined range such that the first metal layer is soluble but the third metal layer is not.
11. The method of claim 1, wherein the solution used for the electrochemical anode metal dissolution is a neutral electrolyte aqueous solution.
12. The method of claim 11, wherein the neutral aqueous electrolyte solution is one or more of the group consisting of: NaCl solution, Na2SO4Solution, MgCl2Solution, KCl solution, K2SO4Solution, KNO3Solution and NaNO3And (3) solution.
13. The method of claim 1, further comprising: forming a passivation layer on the first wafer before forming a first metal layer on the first wafer, and
wherein forming the passivation layer and the first metal layer on the first wafer comprises:
forming a passivation material layer on one side of the first wafer close to the device structure;
forming a first metal material layer on the passivation material layer; and
and patterning the first metal material layer and the passivation material layer in sequence to form the passivation layer and the first metal layer.
14. The method of claim 13, wherein the passivation layer and the first metal layer expose a pad region formed on the first wafer.
15. The method of claim 1, wherein the backside process comprises: and thinning the first wafer on the side of the first wafer far away from the device structure.
16. The method of claim 15, wherein the backside process further comprises: and after the first wafer is thinned, forming a protective layer on one side of the first wafer, which is far away from the device structure.
17. The method of claim 16, wherein forming a protective layer on a side of the first wafer away from the device structure comprises:
forming a protective material layer on one side of the first wafer far away from the device structure; and
and curing the protective material layer to form the protective layer.
18. The method of claim 17, wherein the layer of protective material comprises polyimide.
19. The method of claim 1, wherein the backside process comprises: and forming another device structure on the side of the first wafer far away from the device structure.
20. A semiconductor device, wherein the semiconductor device is manufactured by the method of any one of claims 1-19.
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| CN202011256672.0A CN112382599B (en) | 2020-11-11 | 2020-11-11 | Temporary bonding and debonding method of semiconductor device and semiconductor device |
| PCT/CN2020/129749 WO2022099744A1 (en) | 2020-11-11 | 2020-11-18 | Method for temporarily bonding and de-bonding semiconductor device, and semiconductor device |
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| CN105244308A (en) * | 2015-11-16 | 2016-01-13 | 华天科技（昆山）电子有限公司 | Method for holding thin wafer through temporary bonding of porous slide glass |
| US10703941B2 (en) * | 2013-09-27 | 2020-07-07 | Lintec Corporation | Electrically peelable adhesive composition and electrically peelable pressure sensitive adhesive sheet, and method for using electrically peelable pressure sensitive adhesive sheet |
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| US6340822B1 (en) * | 1999-10-05 | 2002-01-22 | Agere Systems Guardian Corp. | Article comprising vertically nano-interconnected circuit devices and method for making the same |
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| US6468824B2 (en) * | 2001-03-22 | 2002-10-22 | Uni Light Technology Inc. | Method for forming a semiconductor device having a metallic substrate |
| US7498240B2 (en) * | 2005-08-31 | 2009-03-03 | Micron Technology, Inc. | Microfeature workpieces, carriers, and associated methods |
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| US10703941B2 (en) * | 2013-09-27 | 2020-07-07 | Lintec Corporation | Electrically peelable adhesive composition and electrically peelable pressure sensitive adhesive sheet, and method for using electrically peelable pressure sensitive adhesive sheet |
| CN105244308A (en) * | 2015-11-16 | 2016-01-13 | 华天科技（昆山）电子有限公司 | Method for holding thin wafer through temporary bonding of porous slide glass |
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