CN112054019A - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
- Publication number
- CN112054019A CN112054019A CN202010490048.0A CN202010490048A CN112054019A CN 112054019 A CN112054019 A CN 112054019A CN 202010490048 A CN202010490048 A CN 202010490048A CN 112054019 A CN112054019 A CN 112054019A
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- electrode film
- region
- diode
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- semiconductor device
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Abstract
本发明涉及半导体装置。就RC‑IGBT芯片(1)而言,阳极电极膜(21)和发射极电极膜(17)隔开距离地配置。阳极电极膜(21)和发射极电极膜(17)通过具有外部阻抗(27)及外部阻抗(29)的配线导体(41)电连接。外部阻抗(27)及外部阻抗(29)包含配线导体(41)的电阻和配线导体(41)的电感。
Description
技术领域
本发明涉及一种电力用半导体装置。
背景技术
作为电力用半导体装置的一个方式,为了实现封装件的小型化等,存在将绝缘栅型双极晶体管和二极管形成于一个半导体基板的半导体装置。该半导体装置被称为RC-IGBT(反向导通型IGBT:Reverse Conducting Insulated Gate Bipolar Transistor)。作为公开了这样的半导体装置的专利文献,例如有专利文献1(国际公开WO2018/225571号)、专利文献2(日本特开2012-50065号公报)、专利文献3(日本特开2011-210800号公报)及专利文献4(日本特开2016-72359号公报)。
就RC-IGBT而言,在IGBT的发射极侧配置有二极管的阳极。在IGBT的集电极侧配置有二极管的阴极。RC-IGBT主要作为电压逆变器,广泛地应用于以2电平逆变器电路(半桥电路)为代表、组合了该半桥电路的多电平逆变器电桥电路等。
在构成电压逆变器的电路中,由于输出电流的朝向由负载决定,因此无论在电路流动的输出电流的朝向如何,都将电路控制为所期望的输出电位。实现该控制的最简单的方法是在应该使IGBT接通时,无论电流的流动朝向如何都使IGBT接通的方法。
电流的波形受到与电路连接的负载的电感等影响,具有相对于电压的波形延迟的性质。因此,在电压的极性刚刚从负(正)切换为正(负)之后,存在电流与电压的极性反向地流动的期间。该电流在相对于IGBT反向并联连接的二极管流动。这样,即使在电流流过二极管的期间,IGBT也会被接通,在IGBT形成沟道。
就RC-IGBT中的二极管而言,为了在断开状态下扩大耗尽层来确保耐压,采用了包含杂质浓度极低的本征半导体层(Intrinsic Layer)的PIN构造。本征半导体层被夹在p层(阳极)和n层(阴极)之间。
另一方面,为了使二极管接通,通过在p层和n层之间正向地施加电压,从而向本征半导体层从p层注入空穴,并且从n层注入电子,在本征半导体层蓄积电子和空穴。由此,本征半导体层成为金属状态,接通电阻下降。
本征半导体层原本处于几乎没有电子和空穴的状态,该状态为热平衡状态。因此,蓄积电子和空穴而成为金属状态的本征半导体层处于热不平衡状态。在电流流过二极管的期间,如果在IGBT形成沟道,则在本征半导体层,电子和空穴进行消除热不平衡状态的动作。
即,电子从IGBT的发射极起通过沟道而流入本征半导体层,另一方面,对流入的电子的负电荷进行中和,因此产生在本征半导体层蓄积的空穴流入沟道的现象等。因此,在形成有IGBT的IGBT区域与形成有二极管的二极管区域的边界附近,二极管的接通电阻上升,二极管的接通电压上升。此外,二极管的接通电压被称为正向压降。
从对二极管的这样的接通电阻的上升进行抑制的观点出发,作为IGBT区域与二极管区域的边界,优选边界的长度尽可能短。为了缩短边界的长度,优选不将IGBT区域和二极管区域细分地配置。就半导体装置而言,IGBT区域与二极管区域大多被配置成条带状。为了缩短边界的长度,例如需要将该条带的宽度设定得宽。
另外,就RC-IGBT而言,在电流流过IGBT的状态下,电流没有流过二极管。在电流流过二极管的状态下,在IGBT没有流过电流。因此,在电流流过IGBT而IGBT产生热量时,没有流过电流的二极管区域成为该热量的散热路径。在电流流过二极管而二极管产生热量时,没有流过电流的IGBT区域成为该热量的散热路径。因此,从提高散热效果的观点出发,优选IGBT区域与二极管区域的边界长。为了使边界的长度长,例如需要将条带的宽度设定得窄。
这样,就RC-IGBT而言,例如,在条带的宽度宽、边界的长度短的情况下,在对二极管的接通电压的上升进行抑制这一点上是有利的,但另一方面,在对散热效果进行抑制这一点上是不利的。相反,在条带的宽度窄、边界的长度长的情况下,在提高散热效果这一点上是有利的,但在二极管的接通电压容易上升这一点上是不利的。
发明内容
本发明就是鉴于这样的半导体装置(RC-IGBT)的倾向而提出的,其目的在于,提供确保散热效果,并且对二极管的接通电压的上升进行抑制的半导体装置。
本发明涉及的一个半导体装置具有包含第1半导体芯片的半导体芯片部。第1半导体芯片具有相对的第1主面及第2主面。在第1主面规定的第1元件区域形成有第1开关元件。在第1主面规定的第2元件区域形成有第1二极管元件。第1开关元件包含第1发射极层、第1集电极层、第1栅极电极和第1电极膜。第1发射极层形成于第1主面侧。第1集电极层形成于第2主面侧。第1栅极电极形成于第1主面侧。第1电极膜以与第1发射极层接触的方式形成。第1二极管元件包含第1阳极层、第1阴极层和第2电极膜。第1阳极层形成于第1主面侧。第1阴极层形成于第2主面侧。第2电极膜以与第1阳极层接触的方式形成。第1开关元件的第1电极膜与第1二极管元件的第2电极膜隔开距离。具有配线导体,该配线导体包含将第1电极膜与第2电极膜电连接的部分,该配线导体具有阻抗。
本发明涉及的另一个半导体装置具有包含第1半导体芯片和第2半导体芯片的半导体芯片部。第1半导体芯片具有相对的第1主面及第2主面。在第1主面规定的第1元件区域形成有第1开关元件。在第1主面规定的第2元件区域形成有第1二极管元件。第2半导体芯片具有相对的第3主面及第4主面。在第3主面规定的第3元件区域形成有第2开关元件。在第3主面规定的第4元件区域形成有第2二极管元件。第1开关元件包含第1发射极层、第1集电极层、第1栅极电极和第1电极膜。第1发射极层形成于第1主面侧。第1集电极层形成于第2主面侧。第1栅极电极形成于第1主面侧。第1电极膜以与第1发射极层接触的方式形成。第1二极管元件包含第1阳极层、第1阴极层和第2电极膜。第1阳极层形成于第1主面侧。第1阴极层形成于第2主面侧。第2电极膜以与第1阳极层接触的方式形成。第2开关元件包含第2发射极层、第2集电极层、第2栅极电极和第3电极膜。第2发射极层形成于第3主面侧。第2集电极层形成于第4主面侧。第2栅极电极形成于第3主面侧。第3电极膜以与第2发射极层接触的方式形成。第2二极管元件包含第2阳极层、第2阴极层和第4电极膜。第2阳极层形成于第3主面侧。第2阴极层形成于第4主面侧。第4电极膜以与第2阳极层接触的方式形成。第1开关元件的第1电极膜与第1二极管元件的第2电极膜隔开距离。第2开关元件的第3电极膜与第2二极管元件的第4电极膜隔开距离。第1集电极层和第1阴极层电连接。第2集电极层和第2阴极层电连接。具有包含第1导线和第2导线的配线导体。第1导线将第1开关元件的第1电极膜和第2二极管元件的第4电极膜电连接。第2导线将第1二极管元件的第2电极膜和第2开关元件的第3电极膜电连接。
本发明涉及的另一个半导体装置具有半导体芯片。半导体芯片具有相对的第1主面及第2主面。在第1主面规定的第1元件区域形成有开关元件。在第1主面规定的第2元件区域形成有二极管元件。开关元件包含发射极层、集电极层和栅极电极。发射极层形成于第1主面侧。集电极层形成于第2主面侧。栅极电极形成于第1主面侧。二极管元件包含阳极层和阴极层。阳极层形成于第1主面侧。阴极层形成于第2主面侧。具有电极膜和配线导体。电极膜形成为以与发射极层及阳极层接触的方式覆盖第1主面。配线导体与电极膜电连接。配线导体连接于相对于位于第1元件区域和第2元件区域的边界的正上方的电极膜的部分隔开距离的位置。
根据本发明涉及的一个半导体装置,第1开关元件的第1电极膜和第1二极管元件的第2电极膜隔开距离。具有配线导体,该配线导体包含将第1电极膜与第2电极膜电连接的部分,该配线导体具有阻抗。由此,在正向电流流过第1二极管元件的期间,在第1开关元件接通而形成了沟道的状态下,能够阻止注入至第1二极管元件的载流子流入沟道。其结果,能够对第1二极管元件的接通电压的上升进行抑制。
根据本发明涉及的另一个半导体装置,第1半导体芯片的第1开关元件的第1电极膜和第2半导体芯片的第2二极管元件的第4电极膜通过第1导线电连接。第1半导体芯片的第1二极管元件的第2电极膜和第2半导体芯片的第2开关元件的第3电极膜通过第2导线电连接。在正向电流流过第1半导体芯片的第1二极管元件的期间,在第1开关元件接通而形成了沟道的状态下,能够阻止注入至第1二极管元件的载流子流入沟道。其结果,能够对第1二极管元件的接通电压的上升进行抑制。
根据本发明涉及的另一个半导体装置,与电极膜电连接的配线导体连接于相对于位于第1元件区域和第2元件区域的边界的正上方的电极膜的部分隔开距离的位置。由此,在正向电流流过二极管元件的期间,在开关元件接通而形成了沟道的状态下,能够阻止注入至二极管元件的载流子流入沟道。其结果,能够对二极管元件的接通电压的上升进行抑制。
根据与附图相关联地理解的关于本发明的以下的详细说明,可清楚了解本发明的上述及其它的目的、特征、方面以及优点。
附图说明
图1是表示2电平逆变器电路和3电平逆变器电路的一个例子的图,在该2电平逆变器电路和3电平逆变器电路中应用了各实施方式涉及的半导体装置。
图2是用于说明逆变器电路的动作的图。
图3是用于说明3电平逆变器电路的动作的第1图。
图4是用于说明3电平逆变器电路的动作的第2图。
图5是表示实施方式1涉及的半导体装置的平面构造的一个例子的俯视图。
图6是在该实施方式中,图5所示的剖面线VI-VI处的局部剖视图。
图7是表示在该实施方式中,半导体装置的平面构造的另一个例子的俯视图。
图8是表示对比例涉及的半导体装置的平面构造的俯视图。
图9是图8所示的剖面线IX-IX处的局部剖视图。
图10是用于说明对比例涉及的半导体装置的动作的局部剖视图。
图11是用于说明在该实施方式中的半导体装置的动作的局部剖视图。
图12是表示实施方式2涉及的半导体装置的平面构造的俯视图。
图13是表示实施方式3涉及的半导体装置的平面构造的第1例的俯视图。
图14是表示在该实施方式中的半导体装置的平面构造的第2例的俯视图。
图15是表示在该实施方式中的IGBT区域及二极管区域的尺寸关系的局部俯视图。
图16是表示实施方式4涉及的半导体装置的平面构造的俯视图。
图17是表示实施方式5涉及的半导体装置的平面构造的俯视图。
图18是表示实施方式6涉及的半导体装置的平面构造的俯视图。
图19是表示实施方式7涉及的半导体装置的平面构造的俯视图。
图20是表示实施方式8涉及的半导体装置的平面构造的俯视图。
图21是表示对比例涉及的半导体装置的平面构造的俯视图。
图22是表示逆变器电路的一个例子的图,在该逆变器电路中应用了实施方式9涉及的半导体装置。
图23是表示在该实施方式中的半导体装置的平面构造的俯视图。
图24是用于说明在该实施方式中的逆变器电路的一个动作的第1图。
图25是用于说明在该实施方式中的逆变器电路的一个动作的第2图。
图26是表示实施方式10涉及的半导体装置的平面构造的俯视图。
图27是表示实施方式11涉及的半导体装置的平面构造的俯视图。
图28是表示在该实施方式中的包含图27所示的剖面线XXVIII-XXVIII处的剖面的侧视图。
图29是表示在该实施方式中的IGBT区域与二极管区域的边界附近的局部剖视图。
图30是表示实施方式12涉及的半导体装置的平面构造的俯视图。
图31是表示在该实施方式中,图30所示的半导体装置的侧视图。
图32是表示实施方式13涉及的半导体装置的平面构造的俯视图。
图33是表示在该实施方式中,图32所示的半导体装置的侧视图。
图34是表示实施方式14涉及的半导体装置的平面构造的俯视图。
图35是表示在该实施方式中,图34所示的半导体装置的侧视图。
具体实施方式
首先,作为应用半导体装置的电压逆变器电路,对组合了2电平逆变器电路(半桥电路)的3电平逆变器电路进行说明。图1示出3电平逆变器电路和作为其基本电路的半桥电路。作为3电平逆变器电路,举出中性点钳位电路(Neutral Point Clamped;中性点钳位)。这里,例如,示出将中点电位设为基准电位的情况下的3电平逆变器电路。
半桥电路由两个IGBT(T1)及IGBT(T2)、两个二极管D1及二极管D2构成。在该情况下,作为输出的电压,输出+E、-E这两个电平的电压。另一方面,3电平逆变器电路由4个IGBT(TR1)、IGBT(TR2)、IGBT(TR3)及IGBT(TR4)、6个二极管DI1、二极管DI2、二极管DI3、二极管DI4、二极管DI5及二极管DI6构成。在该情况下,作为输出的电压,输出+E、0、-E这三个电平的电压。
如图2所示,在3电平逆变器电路中,在输出上侧的两个电位(+E、0)的期间,在使IGBT(TR2)始终接通、IGBT(TR4)始终断开的状态下,将IGBT(TR1)和IGBT(TR3)作为互补开关,进行使一个接通、另一个断开的控制。在该情况下,由虚线框包围的IGBT(TR1)和IGBT(TR3)作为半桥电路进行动作。
在输出下侧的两个电位(0、-E)的期间,在使IGBT(TR1)始终断开、IGBT(TR3)始终接通的状态下,将IGBT(TR2)和IGBT(TR4)作为互补开关,进行使一个接通、另一个断开的控制。在该情况下,由虚线框包围的IGBT(TR2)和IGBT(TR4)作为半桥电路进行动作。
在半桥电路中,存在输出的电压为高电位(High)的情况和为低电位(Low)的情况。另外,输出的电流的朝向具有动力运行(箭头YP)和再生(箭头YR)(参照图1)。动力运行是指相对于中性点的电位,与输出电位的关系(极性)对应的电流的方向。另一方面,再生是指相对于中性点的电位,与输出电位的关系(极性)反向的电流的方向。
根据以上关系,图3和图4分别示出3电平逆变器电路中的电流的流动。在图3中示出输出上侧的两个电位(+E、0)的期间中的电流的流动的4个模式(状态C1、状态C2、状态C3、状态C4)。在图4中示出在输出下侧的两个电位(0、-E)的期间中的电流的流动的4个模式(状态C5、状态C6、状态C7、状态C8)。
在图3所示的4个电流的流动模式中,在状态C2下,存在在二极管DI1及二极管DI2正向地流过电流的期间。这是因为受到与3电平逆变器电路连接的负载的电感等的影响,输出的电流的波形相对于输出电压的波形延迟的缘故。该状态C2的期间对应于在输出电压的极性刚刚从负切换为正之后电流与输出电压的极性反向地流动的期间。
在该期间,虽然在IGBT(TR1)及IGBT(TR2)中还没有流过电流,但在3电平逆变器电路的控制上,IGBT(TR1)及IGBT(TR2)这两者处于接通状态。如图3所示,该状态C2对应于在半桥电路中,在电流正向地流过二极管D1的期间IGBT(T1)接通的状态。
在图4所示的4个电流的流动模式中,在状态C8下,存在电流正向地流过二极管DI3及二极管DI4的期间。该状态C8的期间对应于在输出电压的极性刚刚从正切换为负之后,电流与输出电压的极性反向地流动的期间。
在该期间中,在IGBT(TR3)及IGBT(TR4)还没有流过电流,但在3电平逆变器电路的控制上,IGBT(TR3)及IGBT(TR4)这两者处于接通状态。如图4所示,该状态C8对应于在半桥电路中,在电流正向地流过二极管D2的期间IGBT(T2)接通的状态。
这样,以半桥电路为代表,在组合了半桥电路的多电平电压逆变器电路中,在电流正向地流过二极管的期间,存在IGBT接通,在IGBT形成了沟道的状态。就RC-IGBT而言,在电流流过二极管的期间,如果在IGBT形成沟道,则由于注入至二极管(本征半导体层)的电子和空穴消除热不平衡状态的动作而导致二极管的接通电阻上升,二极管的接通电压上升。以下,在各实施方式中,具体说明使二极管的接通电压的上升得到抑制的RC-IGBT。
实施方式1.
对实施方式1涉及的半导体装置进行说明。这里,IGBT(TR)与第1开关元件对应。二极管DI与第1二极管元件对应。
如图5及图6所示,在半导体装置SED的RC-IGBT芯片1的半导体基板2的第1主面2a规定有晶体管区域IR和二极管区域DR。在晶体管区域IR形成有IGBT(TR)。在二极管区域DR形成有二极管DI。以包围晶体管区域IR及二极管区域DR的方式形成有保护环区域33。
在晶体管区域IR,在半导体基板2的第1主面2a侧形成有n型的发射极层15。以与发射极层15接触的方式形成有发射极电极膜17。在沟槽9内隔着栅极绝缘膜11形成有沟槽栅极电极13。形成有与沟槽栅极电极13电连接的栅极焊盘31。
在发射极层15的下方形成有用于形成沟道的p型杂质层7。在半导体基板2的第2主面2b侧形成有p型的集电极层19。在p型杂质层7和集电极层19之间形成有作为本征半导体层的n-层3。
在二极管区域DR,在半导体基板2的第1主面2a侧形成有p+型的阳极层5。以与阳极层5接触的方式形成有阳极电极膜21。在半导体基板2的第2主面2b侧形成有n+型的阴极层23。在阳极层5和阴极层23之间形成有作为本征半导体层的n-层3。在半导体基板2的第2主面2b侧,以与集电极层19和阴极层23接触的方式形成有背面电极膜25。
就RC-IGBT芯片1而言,阳极电极膜21和发射极电极膜17隔开距离地配置。阳极电极膜21和发射极电极膜17通过具有外部阻抗27及外部阻抗29的配线导体41电连接。外部阻抗27及外部阻抗29包含配线导体41的电阻和配线导体41的电感。图1所示的配线导体41表示阳极电极膜21和发射极电极膜17以电路方式电连接,并不是对配线导体41的构造进行特定。
此外,RC-IGBT芯片1的晶体管区域IR和二极管区域DR的配置图案并不限于图5所示的配置图案,也可以是如图7所示使晶体管区域IR和二极管区域DR调换后的配置图案。
就上述半导体装置SED而言,通过将阳极电极膜21和发射极电极膜17隔开距离地由具有外部阻抗27、29的配线导体41电连接,从而能够对二极管DI的接通电压的上升进行抑制。与对比例涉及的半导体装置相比较地,对其进行说明。此外,关于对比例涉及的半导体装置,对与实施方式1涉及的半导体装置的结构相同的结构标注相同标号,除了必要的情况以外不重复其说明。
如图8及图9所示,在对比例涉及的半导体装置SED的RC-IGBT芯片101的半导体基板2的第1主面2a规定有晶体管区域IR和二极管区域DR。在晶体管区域IR形成有IGBT(TR)。在二极管区域DR形成有二极管DI。
在第1主面2a以与IGBT(TR)的发射极层15和二极管DI的阳极层5接触的方式形成有发射极-阳极电极膜103。在发射极-阳极电极膜103连接导线151而与外部配线143电连接。在第2主面2b形成有与背面电极膜25电连接的导体板49。对比例涉及的半导体装置SED以如上所述的方式构成。
接着,说明对比例涉及的半导体装置SED的动作。如上所述,以半桥电路为代表,在多电平的电压逆变器电路中,在电流正向地流过二极管的期间,存在IGBT被接通,在IGBT形成了沟道的状态(状态C2、状态C8)。
为了使二极管DI接通而正向地流过电流,需要对作为本征半导体层的n-层3进行电导率调制。电导率调制是本征载流子密度增加的热不平衡状态。为了增加本征载流子密度,作为本征半导体层的n-层3需要在电位上处于浮置状态。换言之,需要能够稳定地产生大幅远离费米能级的准费米能级(quasi Fermi level)。
如图10所示,如果正向地对具有n-层3的二极管DI施加电压而将空穴(h)注入至n-层3,则n-层3的准温度(quasi temperature)成为超高温,在n-层3,电子(e)和空穴(h)这两者的载流子增加。由此,n-层3变得呈金属性,电阻降低,成为在阳极层5与阴极层23之间正向地流过电流的状态。
在电流正向地流过二极管DI的期间,如果IGBT(TR)接通,则形成沟道。通过形成沟道,n-层3的电位与阳极电极膜21的电位、即费米能级附近的电位连接。
因此,为了消除本征半导体层即n-层3的热不平衡状态,电子(e)流入至n-层3,准温度降低,发生注入的空穴的大部分为了中和流入进来的电子的负电荷而向沟道流入的现象等。由此,在位于沟道附近的二极管区域DR的部分,n-层3的电阻上升。其结果,在IGBT(TR)和二极管DI的边界附近,二极管DI的接通电压上升。
相对于对比例涉及的半导体装置SED,就实施方式1涉及的半导体装置SED而言,阳极电极膜21和发射极电极膜17隔开距离地配置。阳极电极膜21和发射极电极膜17通过具有外部阻抗27及外部阻抗29的配线导体41电连接。
此时,如图11所示,如果在二极管DI正向地流过电流,则在与阳极电极膜21电连接的配线导体41中,由外部阻抗27而产生电位差。与发射极电极膜17电连接的部分的电位比与阳极电极膜21连接的部分的电位高。由于在IGBT(TR)没有流过电流,因此与配线导体41电连接的发射极电极膜17的电位比阳极电极膜21的电位高。
此外,从IGBT(TR)的动作的观点和进一步对压降进行抑制的观点出发,优选与发射极电极膜17电连接的配线导体41的外部阻抗29比外部阻抗27小。
这样,由于发射极电极膜17的电位被偏置为比阳极电极膜21的电位高,因此流入至沟道的空穴难以向发射极电极膜17侧逃逸。由此,在二极管DI的n-层3处,能够阻止电子(e)和空穴(h)减少,其结果,能够对二极管DI的接通电压的上升进行抑制。
并且,就半导体装置SED而言,通过利用施加于发射极电极膜17的偏置电位对二极管DI的接通电压的上升进行抑制,即使将晶体管区域IR和二极管区域DR的边界的长度设得长,二极管DI的接通电压也不会受到影响。其结果,能够将晶体管区域IR和二极管区域DR的边界的长度设定得长来保持散热效果,并且对二极管DI的接通电压的上升进行抑制。
实施方式2.
对实施方式2涉及的半导体装置进行说明。如图12所示,在半导体装置SED的RC-IGBT芯片1的半导体基板2的第1主面2a规定有晶体管区域IR和二极管区域DR。在晶体管区域IR形成有IGBT(TR)。以与发射极层15接触的方式形成有发射极电极膜17。在二极管区域DR形成有二极管DI。以与阳极层5接触的方式形成有阳极电极膜21。
阳极电极膜21和发射极电极膜17隔开距离地配置。阳极电极膜21和发射极电极膜17通过具有外部阻抗27、29的配线导体41电连接。
发射极电极膜17(晶体管区域IR)和阳极电极膜21(二极管区域DR)是以一个区域进入另一区域的方式形成的。位于发射极电极膜17(晶体管区域IR)和阳极电极膜21(二极管区域DR)之间的部分的图案具有弯曲的部分。
此外,除此以外的结构与图5及图6等所示的半导体装置SED相同,因此对相同部件标注相同标号,除了必要的情况以外不重复其说明。
上述半导体装置与前述半导体装置SED相同地,由于发射极电极膜17的电位被偏置为比阳极电极膜21的电位高,因此流入至沟道的空穴难以向发射极电极膜17侧逃逸。由此,在二极管DI的n-层3处,能够阻止电子(e)和空穴(h)减少,其结果,能够对二极管DI的接通电压的上升进行抑制。
另外,以位于发射极电极膜17与阳极电极膜21之间的边界部分的图案具有弯曲的部分的方式形成发射极电极膜17和阳极电极膜21,边界部分的长度比边界部分形成为一条直线状的情况长。
如上所述,就半导体装置SED而言,通过利用施加于发射极电极膜17的偏置电位对二极管DI的接通电压的上升进行抑制,从而二极管DI的接通电压不会受到晶体管区域IR和二极管区域DR的边界的长度的影响。
由此,电流流过IGBT(TR)而在晶体管区域IR产生的热量能够有效地向没有流过电流的二极管区域DR散热。另一方面,能够将电流流过二极管DI而在二极管区域DR产生的热量有效地向没有流过电流的晶体管区域IR散热。其结果,能够提高散热效果,并且对二极管DI的接通电压的上升进行抑制。
实施方式3.
对实施方式3涉及的半导体装置进行说明。这里,在逆变器电路中,IGBT(TR)与第1开关元件第1部分和第1开关元件第2部分对应。在逆变器电路中,二极管DI与第1二极管元件第1部分和第1二极管元件第2部分对应。
如图13所示,在半导体装置SED的RC-IGBT芯片1的半导体基板2的第1主面2a规定有晶体管区域IR和二极管区域DR。以包围晶体管区域IR及二极管区域DR的方式形成有保护环区域33。
保护环区域33是沿RC-IGBT芯片1的外周形成的。保护环区域33包含各自沿X轴方向延伸,并且在Y轴方向隔开距离的第1外周部33a和第2外周部33b。以与第1外周部33a相对的方式配置有一个发射极电极膜17(晶体管区域IR)。以与第2外周部33b相对的方式配置有另一个发射极电极膜17(晶体管区域IR)。二极管区域DR配置于一个晶体管区域IR和另一个晶体管区域IR之间。
此外,除此以外的结构与图5及图6等所示的半导体装置SED相同,因此对相同部件标注相同标号,除了必要的情况以外不重复其说明。
上述半导体装置SED除了具有在实施方式1中说明过的对二极管DI的接通电压的上升进行抑制的效果之外,还具有如下效果。
例如,在具有RC-IGBT芯片1的半导体装置SED被应用于逆变器电路的情况下,IGBT(TR)的发热量大于二极管DI的发热量。因此,通过使晶体管区域IR与保护环区域33(第1外周部33a、第2外周部33b)相对的长度比二极管区域DR与保护环区域33相对的长度长,能够使在发热量大的晶体管区域IR产生的热量容易地向RC-IGBT芯片1外散热。
另一方面,例如,在具有RC-IGBT芯片1的半导体装置SED被应用于转换器电路的情况下,二极管DI的发热量大于IGBT(TR)的发热量。在该情况下,如图14所示,使二极管区域DR与保护环区域33(第1外周部33a、第2外周部33b)相对的长度比晶体管区域IR与保护环区域33相对的长度长。由此,能够容易地使在发热量大的二极管区域DR产生的热量向RC-IGBT芯片1外散热。
另外,在逆变器电路的情况下,就半导体装置SED而言,例如考虑感应电动机的功率因数,在晶体管区域IR产生的热量的散热能力大多设计成在二极管区域DR产生的热量的散热能力的约2倍。这样,如图15所示,优选在RC-IGBT芯片1的一条边,将晶体管区域IR的长度L1设定为大于或等于保护环区域33的第1外周部33a的长度L2的2/3的长度。
另一方面,在转换器电路的情况下,相反地,优选在RC-IGBT芯片1的一条边,将发热量大的二极管区域DR的长度L1设定为大于或等于保护环区域33的第1外周部33a的长度L2的2/3的长度。
实施方式4.
对实施方式4涉及的半导体装置进行说明。如图16所示,在半导体装置SED的RC-IGBT芯片1的半导体基板2的第1主面2a规定有晶体管区域IR和二极管区域DR。以包围晶体管区域IR及二极管区域DR的方式形成有保护环区域33。保护环区域33是沿RC-IGBT芯片1的外周形成的。
发射极电极膜17(晶体管区域IR)与保护环区域33相对。阳极电极膜21(二极管区域DR)不与保护环区域33相对。此外,除此以外的结构与图5及图6等所示的半导体装置SED相同,因此对相同部件标注相同标号,除了必要的情况以外不重复其说明。
就上述半导体装置SED而言,除了具有在实施方式1中说明过的对二极管DI的接通电压的上升进行抑制的效果之外,还得到如下效果。
在RC-IGBT芯片1的外周,为了防止漏电流而形成保护环区域33。发射极电极膜17(晶体管区域IR)与保护环区域33相对,阳极电极膜21(二极管区域DR)不与保护环区域33相对。
由此,二极管DI的载流子会流入保护环区域33,对载流子滞留于保护环区域33进行抑制。其结果,能够缩短二极管DI的恢复时间。
实施方式5.
对实施方式5涉及的半导体装置进行说明。这里,IGBT(TR)与第1开关元件第3部分和第1开关元件第4部分对应。二极管DI与第1二极管元件第3部分和第1二极管元件第4部分对应。
如图17所示,在半导体装置SED的RC-IGBT芯片1的半导体基板2的第1主面2a规定有晶体管区域IR和二极管区域DR。以包围晶体管区域IR及二极管区域DR的方式形成有保护环区域33。
如果将一个发射极电极膜17(晶体管区域IR)的宽度设为宽度W1,将其他发射极电极膜17(晶体管区域IR)的宽度设为宽度W3,则宽度W1被设定为比宽度W3宽。包含宽度W1在内的一个发射极电极膜17(晶体管区域IR)与保护环区域33相对的长度比包含宽度W3在内的其他发射极电极膜17(晶体管区域IR)与保护环区域33相对的长度长。一个发射极电极膜17(晶体管区域IR)的面积被设定得比其他发射极电极膜17(晶体管区域IR)的面积大。
如果将一个二极管区域DR的宽度设为宽度W2,将其他二极管区域DR的宽度设为宽度W4,则宽度W4被设定为比宽度W2宽。包含宽度W4在内的一个阳极电极膜21(二极管区域DR)与保护环区域33相对的长度比包含宽度W2在内的其他阳极电极膜21(二极管区域DR)与保护环区域33相对的长度长。一个阳极电极膜21(二极管区域DR)的面积被设定为比其他阳极电极膜21(二极管区域DR)的面积大。
此外,除此以外的结构与图5及图6等所示的半导体装置SED相同,因此对相同部件标注相同标号,除了必要的情况以外不重复其说明。
就上述半导体装置SED而言,除了具有在实施方式1中说明过的对二极管DI的接通电压的上升进行抑制的效果之外,还得到如下效果。
将RC-IGBT芯片1的一个发射极电极膜17(晶体管区域IR)与保护环区域33相对的长度设置为比其他发射极电极膜17(晶体管区域IR)与保护环区域33相对的长度长。并且,将一个发射极电极膜17(晶体管区域IR)的面积设定得比其他发射极电极膜17(晶体管区域IR)的面积大。
将一个阳极电极膜21(二极管区域DR)与保护环区域33相对的长度设定为比其他阳极电极膜21(二极管区域DR)与保护环区域33相对的长度长。此外,将一个阳极电极膜21(二极管区域DR)的面积设定为比其他阳极电极膜21(二极管区域DR)的面积大。
由此,相对于面积(宽度W2)小而有利于散热的其他发射极电极膜17(晶体管区域IR),面积(宽度W1)大的一个发射极电极膜17(晶体管区域IR)位于RC-IGBT芯片1的端部。此外,相对于面积(宽度W3)小而有利于散热的其他阳极电极膜21(二极管区域DR),面积(宽度W4)大的一个阳极电极膜21(二极管区域DR)位于RC-IGBT芯片1的端部。
因此,在正向电流流过二极管DI的期间,在面积小的其他二极管区域DR的二极管DI流过的正向压降(接通电压)上升,在其他二极管区域DR的二极管DI中难以流过正向电流。在面积大的一个二极管区域DR的二极管DI流过的电流相应地增加。
由于面积大的一个二极管区域DR配置于RC-IGBT芯片1的端部,因此能够使由包含多余地流过的正向电流的在二极管DI流过的正向电流而产生的热量有效地向RC-IGBT芯片1外散热。此外,IGBT(TR)也是相同的。
实施方式6.
对实施方式6涉及的半导体装置进行说明。这里,IGBT(TR)与第1开关元件第5部分和第1开关元件第6部分对应。二极管DI与第1二极管元件第5部分和第1二极管元件第6部分对应。
如图18所示,在半导体装置SED的RC-IGBT芯片1的半导体基板2的第1主面2a规定有晶体管区域IR和二极管区域DR。晶体管区域IR及二极管区域DR的每一者例如在Y轴方向具有宽度,沿X轴方向延伸。RC-IGBT芯片1载置于导体板49。导体板49与背面电极膜25(参照图6)接触。
在RC-IGBT芯片1的侧方配置有作为配线导体41的第1外部配线43。一个发射极电极膜17(IGBT(TR))与另一个发射极电极膜17(IGBT(TR))通过导线53与第1外部配线43电连接。导线53在与晶体管区域IR延伸的方向交叉的方向(Y轴方向)延伸。
一个阳极电极膜21(二极管DI)与另一个阳极电极膜21(二极管DI)通过导线55与第1外部配线43电连接。导线55在与二极管区域DR延伸的方向交叉的方向(Y轴方向)延伸。
此外,除此以外的结构与图5及图6等所示的半导体装置SED相同,因此对相同部件标注相同标号,除了必要的情况以外不重复其说明。
就上述半导体装置SED而言,在正向电流流过二极管DI的期间,与阳极电极膜21的电位相比,与由二极管DI和第1外部配线43之间的导线55所具有的阻抗引起的电位差相当的高的电位经由导线53而施加于IGBT(TR)的发射极电极膜17。由此,与通过导线使相邻的发射极电极膜17和阳极电极膜21连接的情况相比,能够有效地对二极管DI的接通电压的上升进行抑制。
另外,IGBT(TR)彼此通过导线53电连接。二极管DI彼此通过导线55电连接。导线53在与晶体管区域IR延伸的方向交叉的方向延伸。导线55在与二极管区域DR延伸的方向交叉的方向延伸。由此,IGBT(TR)彼此及二极管DI彼此的各自的电气连接以大致最短距离连结。其结果,能够使电流的平衡良好。
实施方式7.
对实施方式7涉及的半导体装置进行说明。
如图19所示,在半导体装置SED的RC-IGBT芯片1的半导体基板2的第1主面2a规定有晶体管区域IR和二极管区域DR。晶体管区域IR及二极管区域DR的每一者例如在Y轴方向具有宽度,在X轴方向延伸。在RC-IGBT芯片1的侧方配置有作为配线导体41的第1外部配线第1部分43a、第1外部配线第2部分43b及连接部43c。第1外部配线第1部分43a与第1外部配线第2部分43b通过连接部43c而连接。
一个发射极电极膜17(IGBT(TR))与另一个发射极电极膜17(IGBT(TR))通过导线53与第1外部配线第1部分43a电连接。导线53在与晶体管区域IR延伸的方向交叉的方向(Y轴方向)延伸。
一个阳极电极膜21(二极管DI)与另一个阳极电极膜21(二极管DI)通过导线55与第1外部配线第2部分43b电连接。导线55在与二极管区域DR延伸的方向交叉的方向(Y轴方向)延伸。
此外,除此以外的结构与图18或图5及图6等所示的半导体装置SED的结构相同,因此对相同部件标注相同标号,除了必要的情况外不重复其说明。
就上述半导体装置SED而言,将IGBT(TR)彼此电连接的导线53与第1外部配线第1部分43a连接。将二极管DI彼此电连接的导线55与第1外部配线第2部分43b连接。第1外部配线第1部分43a与第1外部配线第2部分43b通过连接部43c而连接。
由此,与配置第1外部配线43(参照图18)的情况相比,能够向IGBT(TR)的发射极电极膜17施加比阳极电极膜21的电位高的电位。能够有效地对二极管DI的接通电压的上升进行抑制。
实施方式8.
对实施方式8涉及的半导体装置进行说明。这里,第1RC-IGBT芯片的IGBT(TR)与第1开关元件对应,二极管DI与第1二极管元件对应。第2RC-IGBT芯片的IGBT(TR)与第2开关元件对应,二极管DI与第2二极管元件对应。
如图20所示,就半导体装置SED而言,作为RC-IGBT芯片1,配置第1RC-IGBT芯片1a和第2RC-IGBT芯片1b。导体板49被配置为与第1RC-IGBT芯片1a及第2RC-IGBT芯片1b的每一者的背面电极膜25(参照图6)接触。
在第1RC-IGBT芯片1a的半导体基板2的第1主面2a规定有晶体管区域IR和二极管区域DR。以包围晶体管区域IR及二极管区域DR的方式形成保护环区域33。在第2RC-IGBT芯片1b的半导体基板2的第1主面2a规定有晶体管区域IR和二极管区域DR。以包围晶体管区域IR及二极管区域DR的方式形成有保护环区域33。在第2RC-IGBT芯片1b的侧方配置有第2外部配线45。
第1RC-IGBT芯片1a的发射极电极膜17(IGBT(TR))和第2RC-IGBT芯片1b的阳极电极膜21(二极管(DI))通过导线52a与第2外部配线45电连接。第1RC-IGBT芯片1a的阳极电极膜21(二极管DI)和第2RC-IGBT芯片1b的发射极电极膜17(IGBT(TR))通过导线52b与第2外部配线45电连接。
另外,第1RC-IGBT芯片1a的栅极焊盘31和第2RC-IGBT芯片1b的栅极焊盘31通过导线57电连接。此外,除此以外的结构与图18或图5及图6等所示的半导体装置SED相同,因此对相同部件标注相同标号,除了必要的情况以外不重复其说明。
就半导体装置SED而言,通常所控制的电流量较大,在该情况下,应用并联地电连接有多个RC-IGBT芯片1的半导体装置SED。就上述半导体装置SED而言,第1RC-IGBT芯片1a和第2RC-IGBT芯片1b以如下方式并联地电连接。
第1RC-IGBT芯片1a的发射极电极膜17和第2RC-IGBT芯片1b的阳极电极膜21通过导线52a与第2外部配线45电连接。第1RC-IGBT芯片1a的阳极电极膜21和第2RC-IGBT芯片1b的发射极电极膜17通过导线52b与第2外部配线45电连接。
就上述半导体装置而言,除了在实施方式1中说明过的效果之外,还能够实现电流的平衡。与对比例涉及的半导体装置相比较地,对其进行说明。
如图21所示,就对比例涉及的半导体装置SED而言,多个RC-IGBT芯片1以如下方式并联地电连接。第1RC-IGBT芯片1a的发射极电极膜17和第2RC-IGBT芯片1b的发射极电极膜17通过导线153a和153b与第2外部配线143电连接。
第1RC-IGBT芯片1a的发射极电极膜17通过导线153a与第2RC-IGBT芯片1b的发射极电极膜17电连接。第2RC-IGBT芯片1b的发射极电极膜17通过导线153b与外部配线143电连接。将导线153b的粗细设定为比导线153a的粗细大。
第1RC-IGBT芯片1a的阳极电极膜21和第2RC-IGBT芯片1b的阳极电极膜21通过导线155a和155b与第2外部配线143电连接。
第1RC-IGBT芯片1a的阳极电极膜21通过导线155a与第2RC-IGBT芯片1b的阳极电极膜21电连接。第2RC-IGBT芯片1b的阳极电极膜21通过导线155b与外部配线143电连接。将导线155b的粗细设定为比导线155a的粗细大。
就对比例涉及的半导体装置SED而言,特别地,在导线153b中流过第1RC-IGBT芯片1a的IGBT(TR)和第2RC-IGBT芯片1b的IGBT(TR)这两个器件的量的电流。在导线153a流过第1RC-IGBT芯片1a的IGBT(TR)这一个器件的量的电流。因此,在并联地电连接的两个IGBT(TR)的每一者流过的电流随时间的变化(di/dt)的平衡变差。
相对于对比例涉及的半导体装置SED,就实施方式8涉及的半导体装置SED而言,第1RC-IGBT芯片1a的发射极电极膜17、第2RC-IGBT芯片1b的阳极电极膜21通过导线52a与第2外部配线45电连接。第1RC-IGBT芯片1a的阳极电极膜21、第2RC-IGBT芯片1b的发射极电极膜17通过导线52b与第2外部配线45电连接。
由此,在导线52a中流过第1RC-IGBT芯片1a的IGBT(TR)这一个器件的量的电流。在导线52b中流过第2RC-IGBT芯片1b的IGBT(TR)这一个器件的量的电流。其结果,与对比例涉及的半导体装置SED相比,能够改善在并联地电连接的两个IGBT(TR)的每一者流过的电流随时间的变化(di/dt)的平衡。
实施方式9.
对实施方式9涉及的半导体装置进行说明。这里,第1RC-IGBT芯片的IGBT(TR)与第1开关元件对应,二极管DI与第1二极管元件对应。第2RC-IGBT芯片的IGBT(TR)与第2开关元件对应,二极管DI与第2二极管元件对应。
在实施方式1等中,作为3电平逆变器电路的一个例子,举出了中性点钳位电路(Neutral Point Clamped)。这里,作为另一个例子,举出中点开关型的3电平逆变器电路而进行说明。
在图22示出中点开关型的3电平逆变器电路。如图22所示,中点开关型的3电平逆变器电路由4个IGBT(TR5)、IGBT(TR6)、IGBT(TR7)及IGBT(TR8)、4个二极管DI7、二极管DI8、二极管DI9及二极管DI10构成。
IGBT(TR(TR5))及二极管DI(DI7)形成于第1RC-IGBT芯片1c。IGBT(TR(TR6))及二极管DI(DI8)形成于第2RC-IGBT芯片1d。
如图23所示,第1RC-IGBT芯片1c的IGBT(TR(TR5))的发射极电极膜17、第2RC-IGBT芯片1d的二极管DI(DI8)的阳极电极膜21通过导线52a电连接。第1RC-IGBT芯片1c的二极管DI(DI7)的阳极电极膜21、第2RC-IGBT芯片1d的IGBT(TR6)的发射极电极膜17通过导线52b电连接。就半导体装置SED而言,除此之外还配置有未图示的IGBT(TR6)、IGBT(TR8)、二极管DI9及二极管DI10。
关于中点开关型的3电平逆变器电路,也与中性点钳位电路的情况相同地,就RC-IGBT芯片1而言,在正向电流流过二极管DI的期间,存在IGBT(TR)接通,形成了沟道的状态。图24示出了该状态的一个例子。在图24中示出了例如在IGBT(TR6)始终接通时,在正向电流流过二极管DI7的期间,IGBT(TR5)接通,形成了沟道的状态。
如图25所示,在该状态下,就3电平逆变器电路而言,电流如粗的实线所示那样依次流过IGBT(TR6)和二极管DI7。此时,在与IGBT(TR6)电连接的二极管DI8的阳极侧,电位以IGBT(TR6)的接通电压(VCEsat)的量上升(参照记号+)。
由于在二极管DI8中没有流过电流,因此处于浮置的状态。因此,在二极管DI8的阴极与阳极之间,由于耗尽层电场等而产生电位差,二极管DI8的阳极侧的电位(参照记号++)比二极管DI8的阴极侧的电位(参照记号+)高。
由此,能够阻止注入至二极管DI7中的空穴向接通的IGBT(TR5)的沟道流入。其结果,能够对二极管DI7的接通电压的上升进行抑制。
另外,图23所示的晶体管区域IR和二极管区域DR的边界的长度也不会对接通电压造成影响,能够保持散热效果,并且对二极管DI的接通电压的上升进行抑制。
实施方式10.
对实施方式10涉及的半导体装置进行说明。
如图26所示,在半导体装置SED的RC-IGBT芯片1的半导体基板2的第1主面2a规定有晶体管区域IR和二极管区域DR。在RC-IGBT芯片1的侧方配置有作为配线导体的第1外部配线第1部分43a、第1外部配线第2部分43b、连接部43c及感测电阻63、65。感测电阻63介于第1外部配线第1部分43a和连接部43c之间。感测电阻65介于第1外部配线第2部分43b和连接部43c之间。
此外,除此以外的结构与图19所示的半导体装置SED的结构相同,因此对相同部件标注相同标号,除了必要的情况以外不重复其说明。
就上述半导体装置SED而言,将IGBT(TR)彼此电连接的导线53与第1外部配线第1部分43a连接。将二极管DI彼此电连接的导线55与第1外部配线第2部分43b连接。在连接部43c的基础上,第1外部配线第1部分43a和第1外部配线第2部分43b作为感测电阻61通过感测电阻63、65连接。
由此,与配置第1外部配线43的情况相比,能够向IGBT(TR)的发射极电极膜17施加比阳极电极膜21的电位更高的电位。其结果,能够更有效地对二极管DI的接通电压的上升进行抑制。
实施方式11。
对实施方式11涉及的半导体装置进行说明。这里,对将发射极电极膜和阳极电极膜一体化,在导线的连接方式上具有特征的半导体装置的第1例进行说明。IGBT(TR)与开关元件对应,二极管DI与二极管元件对应。
如图27、图28及图29所示,在半导体装置SED的RC-IGBT芯片1的半导体基板2的第1主面2a规定有晶体管区域IR和二极管区域DR。在晶体管区域IR形成有IGBT(TR)。在二极管区域DR形成有二极管DI。以与发射极层15及阳极层5这两者接触的方式形成有发射极-阳极电极膜71。
在发射极-阳极电极膜71,以横跨配置有晶体管区域IR的部分、配置有二极管区域DR的部分的方式连接导线59。该导线59与导体部48连接。导线59与发射极-阳极电极膜71中的相对于晶体管区域IR和二极管区域DR的边界BN隔开距离的位置连接。
具体而言,如图29所示,导线59与配置有二极管区域DR的发射极-阳极电极膜71的部分连接的位置相对于晶体管区域IR和二极管区域DR的边界BN隔开距离LW。如果将二极管DI的作为本征半导体层的n-层3的厚度设为厚度LT,则将距离LW设定得比与厚度LT相当的距离长。
RC-IGBT芯片1的第2主面2b通过焊料47与导体板49接合。此外,除此以外的结构与图5及图6等所示的半导体装置SED相同,因此对相同部件标注相同标号,除了必要的情况以外不重复其说明。
就上述半导体装置SED而言,发射极-阳极电极膜71与发射极层15及阳极层5这两者接触。作为发射极-阳极电极膜71,例如应用铝膜。铝是容易流过电流的材料之一。适用于半导体装置SED的铝膜较薄,在大电流流过该铝膜的情况下,在铝膜的面方向产生电阻。
在二极管区域DR,导线59连接于发射极-阳极电极膜71中的相对于晶体管区域IR和二极管区域DR的边界BN隔开比与n-层3的厚度LT相当的距离长的距离LW的位置。
因此,在正向电流流过二极管DI时,由于在发射极-阳极电极膜71的面方向产生的电阻,在从连接有导线59的位置至边界BN为止的n-层3的区域CR内注入的载流子比在导线59的正下方的n-层3的部分注入的载流子少。
由此,在正向电流流过二极管DI的期间,即使在IGBT(TR)接通,IGBT(TR)形成了沟道的状态下,也会对载流子向沟道流入的量进行抑制。其结果,能够对二极管DI的接通电压的上升进行抑制。另外,通过与发射极层15及阳极层5这两者接触的发射极-阳极电极膜71,也能够实现散热效果。
实施方式12.
对实施方式12涉及的半导体装置进行说明。这里,对导线的连接方式的一个变形例进行说明。IGBT(TR)与开关元件第1部分和开关元件第2部分对应。二极管DI与二极管元件第1部分和二极管元件第2部分对应。
如图30及31所示,在半导体装置SED的RC-IGBT芯片1的半导体基板2的第1主面2a规定有晶体管区域IR和二极管区域DR。在晶体管区域IR形成有IGBT(TR)。在二极管区域DR形成有二极管DI。以与发射极层15及阳极层5这两者接触的方式形成有发射极-阳极电极膜71。
发射极-阳极电极膜71中的配置有一个晶体管区域IR的部分和配置有其他晶体管区域IR的部分通过导线53连接。该导线53与导体部48连接。
发射极-阳极电极膜71中的配置有一个二极管区域DR的部分和配置有其他二极管区域DR的部分通过导线55连接。该导线55与导体部48连接。在二极管区域DR,导线55连接于发射极-阳极电极膜71中的相对于晶体管区域IR和二极管区域DR的边界BN隔开比与n-层3的厚度LT相当的距离长的距离LW的位置(参照图29)。
此外,关于除此以外的结构,由于与图27及图28所示的半导体装置的结构相同,因此对相同部件标注相同标号,除了必要的情况以外,不重复其说明。
就上述半导体装置SED而言,相邻的IGBT(TR)和二极管DI不是通过导线直接连接,而是经由导线53、导体部48和导线55电连接。由此,通过由导线55所具有的阻抗引起的电位差,与实施方式11中说明过的半导体装置SED的情况相比,IGBT(TR)的发射极侧的电位稍微上升。
由此,在正向电流流过二极管DI的期间,在IGBT(TR)接通,IGBT(TR)形成了沟道的状态下,进一步对载流子从n-层3向沟道流入的量进行抑制。其结果,能够有效地对二极管DI的接通电压的上升进行抑制。
实施方式13.
对实施方式13涉及的半导体装置进行说明。这里,对导线的连接方式的其他变形例进行说明。IGBT(TR)与开关元件第3部分和开关元件第4部分对应。二极管DI与二极管元件第3部分和二极管元件第4部分对应。
如图32及图33所示,在半导体装置SED的RC-IGBT芯片1的半导体基板2的第1主面2a规定有晶体管区域IR和二极管区域DR。在晶体管区域IR形成有IGBT(TR)。在二极管区域DR形成有二极管DI。以与发射极层15及阳极层5这两者接触的方式形成有发射极-阳极电极膜71。
发射极-阳极电极膜71中的配置有一个晶体管区域IR的部分和配置有一个二极管区域DR的部分通过导线59连接。该导线59与导体部48连接。
发射极-阳极电极膜71中的配置有其他二极管区域DR的部分和配置有其他晶体管区域IR的部分通过导线59连接。该导线59与导体部48连接。
在二极管区域DR,导线59连接于发射极-阳极电极膜71中的相对于晶体管区域IR和二极管区域DR的边界BN隔开比与n-层3的厚度LT相当的距离长的距离LW的位置(参照图29)。
此外,关于除此以外的结构,由于与图27及图28所示的半导体装置的结构相同,因此对相同部件标注相同标号,除了必要的情况以外,不重复其说明。
就上述半导体装置SED而言,除了在实施方式11中说明过的效果之外,还得到如下效果。导线59与发射极-阳极电极膜71中的配置有一个晶体管区域IR的部分、配置有一个二极管区域DR的部分连接,并且与导体部48连接。
另外,导线59与发射极-阳极电极膜71中的配置有其他二极管区域DR的部分、其他晶体管区域IR连接,并且与导体部48连接。
不会在IGBT(TR)和二极管DI同时流过电流。因此,在各个导线59中,仅流过IGBT(TR)这一个器件的量的电流或二极管DI这一个器件的量的电流。由此,例如,与在一根导线流过两个IGBT(TR)的量的电流的情况相比,能够实现电流的平衡。
实施方式14.
对实施方式14涉及的半导体装置进行说明。这里,对能够将导线连接于发射极-阳极电极膜中的所期望的位置的半导体装置进行说明。
如图34及图35所示,在半导体装置SED的RC-IGBT芯片1的半导体基板2的第1主面2a例如形成有聚酰亚胺膜81。在聚酰亚胺膜81中,在应该连接导线51的位置处形成有使发射极-阳极电极膜71露出的开口部。
此外,关于除此以外的结构,由于与图27及图28所示的半导体装置的结构相同,因此对相同部件标注相同标号,除了必要的情况以外,不重复其说明。
就上述半导体装置SED而言,以覆盖发射极-阳极电极膜71的方式形成有聚酰亚胺膜81。在该聚酰亚胺膜81形成有使发射极-阳极电极膜71露出的开口部。开口部形成于应该连接导线51的位置。由此,能够将导线51可靠地连接于相对于晶体管区域IR与二极管区域DR的边界BN(参照图29)离开距离LW的位置(参照图29)。
此外,关于在各实施方式中说明过的半导体装置,可以与需要对应地进行各种组合。
本次公开的实施方式只是例示,并不限于此。本发明不是由上述说明的范围表示,而是由权利要求书表示,旨在包含与权利要求书等同的含义及范围内的所有变更。
本发明可有效地用于电力用半导体装置。
Claims (18)
1.一种半导体装置,其具有半导体芯片部,该半导体芯片部包含第1半导体芯片,该第1半导体芯片具有相对的第1主面及第2主面,在所述第1主面规定的第1元件区域形成有第1开关元件,在所述第1主面规定的第2元件区域形成有第1二极管元件,
所述第1开关元件包含:
第1发射极层,其形成于所述第1主面侧;
第1集电极层,其形成于所述第2主面侧;
第1栅极电极,其形成于所述第1主面侧;以及
第1电极膜,其形成为与所述第1发射极层接触,
所述第1二极管元件包含:
第1阳极层,其形成于所述第1主面侧;
第1阴极层,其形成于所述第2主面侧;以及
第2电极膜,其形成为与所述第1阳极层接触,
所述第1开关元件的所述第1电极膜、所述第1二极管元件的所述第2电极膜隔开距离,
该半导体装置具有配线导体,该配线导体包含将所述第1电极膜和所述第2电极膜电连接的部分,该配线导体具有阻抗。
2.根据权利要求1所述的半导体装置,其中,
所述第1电极膜和所述第2电极膜是以位于隔开所述距离的所述第1电极膜和所述第2电极膜之间的部分的图案具有弯曲的部分的方式形成的。
3.根据权利要求1所述的半导体装置,其中,
该半导体装置具有保护环区域,该保护环区域是以包围所述第1元件区域及所述第2元件区域的方式沿所述第1半导体芯片的外周形成的,
所述保护环区域包含各自沿第1方向延伸并且在与所述第1方向交叉的第2方向隔开距离而相对的第1外周部及第2外周部,
所述第1元件区域包含第1元件区域第1部分和第1元件区域第2部分,
在所述第1元件区域第1部分形成有作为所述第1开关元件的第1开关元件第1部分,
在所述第1元件区域第2部分形成有作为所述第1开关元件的第1开关元件第2部分,
所述第1开关元件第1部分包含作为所述第1电极膜的第1电极膜第1部分,
所述第1开关元件第2部分包含作为所述第1电极膜的第1电极膜第2部分,
所述第1电极膜第1部分配置为沿所述第1方向与所述第1外周部相对,
所述第1电极膜第2部分配置为沿所述第1方向与所述第2外周部相对,
在所述第1电极膜第1部分与所述第1电极膜第2部分之间配置有所述第2电极膜。
4.根据权利要求3所述的半导体装置,其中,
如果将所述第1外周部的所述第1方向的长度设为第1长度,
将所述第1电极膜第1部分的所述第1方向的长度设为第2长度,
则所述第2长度设定为大于或等于所述第1长度的三分之二。
5.根据权利要求1所述的半导体装置,其中,
该半导体装置具有保护环区域,该保护环区域是以包围所述第1元件区域及所述第2元件区域的方式沿所述第1半导体芯片的外周形成的,
所述保护环区域包含各自沿第1方向延伸并且在与所述第1方向交叉的第2方向隔开距离而相对的第1外周部及第2外周部,
所述第2元件区域包含第2元件区域第1部分和第2元件区域第2部分,
在所述第2元件区域第1部分形成有作为所述第1二极管元件的第1二极管元件第1部分,
在所述第2元件区域第2部分形成有作为所述第1二极管元件的第1二极管元件第2部分,
所述第1二极管元件第1部分包含作为所述第2电极膜的第2电极膜第1部分,
所述第1二极管元件第2部分包含作为所述第2电极膜的第2电极膜第2部分,
所述第2电极膜第1部分配置为沿所述第1方向与所述第1外周部相对,
所述第2电极膜第2部分配置为沿所述第1方向与所述第2外周部相对,
在所述第2电极膜第1部分和所述第2电极膜第2部分之间配置有所述第1电极膜。
6.根据权利要求1所述的半导体装置,其中,
该半导体装置具有保护环区域,该保护环区域是以包围所述第1元件区域及所述第2元件区域的方式沿所述第1半导体芯片的外周形成的,
所述第2电极膜不与所述保护环区域相对,
所述第1电极膜与所述保护环区域相对。
7.根据权利要求1所述的半导体装置,其中,
该半导体装置具有保护环区域,该保护环区域是以包围所述第1元件区域及所述第2元件区域的方式沿所述第1半导体芯片的外周形成的,
所述第1元件区域包含第1元件区域第3部分和第1元件区域第4部分,
在所述第1元件区域第3部分形成有作为所述第1开关元件的第1开关元件第3部分,
在所述第1元件区域第4部分形成有作为所述第1开关元件的第1开关元件第4部分,
所述第1开关元件第3部分包含作为所述第1电极膜的第1电极膜第3部分,
所述第1开关元件第4部分包含作为所述第1电极膜的第1电极膜第4部分,
如果将所述第1电极膜第3部分与所述保护环区域相对的部分的长度设为第1长度,
将所述第1电极膜第4部分与所述保护环区域相对的部分的长度设为第2长度,
则所述第1长度比所述第2长度长,
所述第1电极膜第3部分的面积设定为比所述第1电极膜第4部分的面积大。
8.根据权利要求1所述的半导体装置,其中,
该半导体装置具有保护环区域,该保护环区域是以包围所述第1元件区域及所述第2元件区域的方式沿所述第1半导体芯片的外周形成的,
所述第2元件区域包含第2元件区域第3部分和第2元件区域第4部分,
在所述第2元件区域第3部分形成有作为所述第1二极管元件的第1二极管元件第3部分,
在所述第2元件区域第4部分形成有作为所述第1二极管元件的第1二极管元件第4部分,
所述第1二极管元件第3部分包含作为所述第2电极膜的第2电极膜第3部分,
所述第1二极管元件第4部分包含作为所述第2电极膜的第2电极膜第4部分,
如果将所述第2电极膜第3部分与所述保护环区域相对的部分的长度设为第3长度,
将所述第2电极膜第4部分与所述保护环区域相对的部分的长度设为第4长度,
则所述第3长度比所述第4长度长,
所述第2电极膜第3部分的面积设定为比所述第2电极膜第4部分的面积大。
9.根据权利要求1所述的半导体装置,其中,
所述第1元件区域包含第1元件区域第5部分和第1元件区域第6部分,
在所述第1元件区域第5部分形成有作为所述第1开关元件的第1开关元件第5部分,
在所述第1元件区域第6部分形成有作为所述第1开关元件的第1开关元件第6部分,
所述第1开关元件第5部分包含作为所述第1电极膜的第1电极膜第5部分,
所述第1开关元件第6部分包含作为所述第1电极膜的第1电极膜第6部分,
所述第2元件区域包含第2元件区域第5部分和第2元件区域第6部分,
在所述第2元件区域第5部分形成有作为所述第1二极管元件的第1二极管元件第5部分,
在所述第2元件区域第6部分形成有作为所述第1二极管元件的第1二极管元件第6部分,
所述第1二极管元件第5部分包含作为所述第2电极膜的第2电极膜第5部分,
所述第1二极管元件第6部分包含作为所述第2电极膜的第2电极膜第6部分,
所述第1电极膜第5部分、所述第1电极膜第6部分、所述第2电极膜第5部分及所述第2电极膜第6部分各自沿第1方向延伸,并且是沿与所述第1方向交叉的第2方向配置的,
所述配线导体包含:
第1外部配线;
第1导线,其沿所述第2方向将所述第1电极膜第5部分、所述第1电极膜第6部分及所述第1外部配线电连接;以及
第2导线,其沿所述第2方向将所述第2电极膜第5部分、所述第2电极膜第6部分及所述第1外部配线电连接。
10.根据权利要求9所述的半导体装置,其中,
所述第1外部配线包含:
第1外部配线第1部分;
第1外部配线第2部分;以及
连接部,其将所述第1外部配线第1部分和所述第1外部配线第2部分连接,
所述第1导线与所述第1外部配线第1部分连接,
所述第2导线与所述第1外部配线第2部分连接。
11.根据权利要求10所述的半导体装置,其中,
在所述第1外部配线第1部分与所述第1外部配线第2部分之间连接有感测电阻。
12.根据权利要求1所述的半导体装置,其中,
所述半导体芯片部包含第2半导体芯片,该第2半导体芯片具有相对的第3主面及第4主面,在所述第3主面规定的第3元件区域形成有第2开关元件,在所述第3主面规定的第4元件区域形成有第2二极管元件,
所述第2开关元件包含:
第2发射极层,其形成于所述第3主面侧;
第2集电极层,其形成于所述第4主面侧;
第2栅极电极,其形成于所述第3主面侧;以及
第3电极膜,其形成为与所述第2发射极层接触,
所述第2二极管元件包含:
第2阳极层,其形成于所述第3主面侧;
第2阴极层,其形成于所述第4主面侧;以及
第4电极膜,其形成为与所述第2阳极层接触,
所述第2开关元件的所述第3电极膜、所述第2二极管元件的所述第4电极膜隔开距离,
所述第1集电极层、所述第1阴极层、所述第2集电极层及所述第2阴极层电连接,
所述配线导体包含第3导线、第4导线及第2外部配线,
所述第3导线将所述第1开关元件的所述第1电极膜、所述第2二极管元件的所述第4电极膜、所述第2外部配线电连接,
所述第4导线将所述第1二极管元件的所述第2电极膜、所述第2开关元件的所述第3电极膜、所述第2外部配线电连接。
13.一种半导体装置,其具有半导体芯片部,该半导体芯片部包含:
第1半导体芯片,其具有相对的第1主面及第2主面,在所述第1主面规定的第1元件区域形成有第1开关元件,在所述第1主面规定的第2元件区域形成有第1二极管元件;以及
第2半导体芯片,其具有相对的第3主面及第4主面,在所述第3主面规定的第3元件区域形成有第2开关元件,在所述第3主面规定的第4元件区域形成有第2二极管元件,
所述第1开关元件包含:
第1发射极层,其形成于所述第1主面侧;
第1集电极层,其形成于所述第2主面侧;
第1栅极电极,其形成于所述第1主面侧;以及
第1电极膜,其形成为与所述第1发射极层接触,
所述第1二极管元件包含:
第1阳极层,其形成于所述第1主面侧;
第1阴极层,其形成于所述第2主面侧;以及
第2电极膜,其形成为与所述第1阳极层接触,
所述第2开关元件包含:
第2发射极层,其形成于所述第3主面侧;
第2集电极层,其形成于所述第4主面侧;
第2栅极电极,其形成于所述第3主面侧;以及
第3电极膜,其形成为与所述第2发射极层接触,
所述第2二极管元件包含:
第2阳极层,其形成于所述第3主面侧;
第2阴极层,其形成于所述第4主面侧;以及
第4电极膜,其形成为与所述第2阳极层接触,
所述第1开关元件的所述第1电极膜、所述第1二极管元件的所述第2电极膜隔开距离,
所述第2开关元件的所述第3电极膜、所述第2二极管元件的所述第4电极膜隔开距离,
所述第1集电极层与所述第1阴极层电连接,
所述第2集电极层与所述第2阴极层电连接,
该半导体装置具有配线导体,该配线导体包含:
第1导线,其将所述第1开关元件的所述第1电极膜、所述第2二极管元件的所述第4电极膜电连接;以及
第2导线,其将所述第1二极管元件的所述第2电极膜、所述第2开关元件的所述第3电极膜电连接。
14.一种半导体装置,其具有半导体芯片,该半导体芯片具有相对的第1主面及第2主面,在所述第1主面规定的第1元件区域形成有开关元件,在所述第1主面规定的第2元件区域形成有二极管元件,
所述开关元件包含:
发射极层,其形成于所述第1主面侧;
集电极层,其形成于所述第2主面侧;以及
栅极电极,其形成于第1主面侧,
所述二极管元件包含:
阳极层,其形成于所述第1主面侧;以及
阴极层,其形成于所述第2主面侧,
该半导体装置具有:
电极膜,其形成为以与所述发射极层及所述阳极层接触的方式覆盖所述第1主面;以及
配线导体,其与所述电极膜电连接,
所述配线导体连接于相对于位于所述第1元件区域和所述第2元件区域的边界的正上方的所述电极膜的部分隔开距离的位置。
15.根据权利要求14所述的半导体装置,其中,
所述半导体芯片包含形成于所述阳极层和所述阴极层之间、具有第1厚度的第1导电型的半导体层,
所述配线导体连接于相对于位于所述边界的正上方的所述电极膜的所述部分作为所述距离而隔开了比与所述第1厚度相当的距离长的距离的位置。
16.根据权利要求14所述的半导体装置,其中,
所述第1元件区域包含第1元件区域第1部分和第1元件区域第2部分,
在所述第1元件区域第1部分形成有作为所述开关元件的开关元件第1部分,
在所述第1元件区域第2部分形成有作为所述开关元件的开关元件第2部分,
所述第2元件区域包含第2元件区域第1部分和第2元件区域第2部分,
在所述第2元件区域第1部分形成有作为所述二极管元件的二极管元件第1部分,
在所述第2元件区域第2部分形成有作为所述二极管元件的二极管元件第2部分,
所述第1元件区域第1部分和所述第1元件区域第2部分隔开距离地配置,
所述第2元件区域第1部分和所述第2元件区域第2部分隔开距离地配置,
所述配线导体包含:
第1导线,其将位于所述第1元件区域第1部分的正上方的所述电极膜的第1部分、位于所述第1元件区域第2部分的正上方的所述电极膜的第2部分电连接;
第2导线,其将位于所述第2元件区域第1部分的正上方的所述电极膜的第3部分、位于所述第2元件区域第2部分的正上方的所述电极膜的第4部分电连接;以及
第1外部配线,其将所述第1导线和所述第2导线电连接。
17.根据权利要求14所述的半导体装置,其中,
所述第1元件区域包含第1元件区域第3部分和第1元件区域第4部分,
在所述第1元件区域第3部分形成有作为所述开关元件的开关元件第3部分,
在所述第1元件区域第4部分形成有作为所述开关元件的开关元件第4部分,
所述第2元件区域包含第2元件区域第3部分和第2元件区域第4部分,
在所述第2元件区域第3部分形成有作为所述二极管元件的二极管元件第3部分,
在所述第2元件区域第4部分形成有作为所述二极管元件的二极管元件第4部分,
所述第1元件区域第3部分和所述第1元件区域第4部分隔开距离地配置,
所述第2元件区域第3部分和所述第2元件区域第4部分隔开距离地配置,
所述配线导体包含:
第3导线,其将位于所述第1元件区域第3部分的正上方的所述电极膜的第5部分、位于所述第2元件区域第3部分的正上方的所述电极膜的第6部分电连接;
第4导线,其将位于所述第1元件区域第4部分的正上方的所述电极膜的第7部分、位于所述第2元件区域第4部分的正上方的所述电极膜的第8部分电连接;以及
第2外部配线,其将所述第3导线和所述第4导线电连接。
18.根据权利要求14至17中任一项所述的半导体装置,其中,
以覆盖所述第1主面的方式形成有保护膜,
在所述保护膜,在连接所述配线导体的部位形成有开口部。
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