CN104465646A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN104465646A
CN104465646A CN201410077962.7A CN201410077962A CN104465646A CN 104465646 A CN104465646 A CN 104465646A CN 201410077962 A CN201410077962 A CN 201410077962A CN 104465646 A CN104465646 A CN 104465646A
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semiconductor layer
semiconductor
substrate
type
switch element
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高桥启太
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Toshiba Corp
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Toshiba Corp
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Abstract

本发明提供一种半导体装置。根据实施方式，半导体装置具备设置于相同基板上的开关元件以及二极管。开关元件具有第一半导体层、第一半导体区域、第二半导体区域、沟道区域、栅极绝缘膜、栅极电极、第一电极以及第二电极。第一半导体层设置于基板内，与基板电分离。二极管具有第二半导体层、阳极区域、阴极区域、阳极电极以及阴极电极。第二半导体层设置于基板内，与基板电分离。

Description

半导体装置
本申请享受于2013年9月13日提交的日本专利申请2013-191112的优先权利益，该日本专利申请的全部内容被援用于本申请。
技术领域
本发明的实施方式涉及一种半导体装置。
背景技术
例如在与线圈等电感性负载连接的开关元件中，在栅极截止时通过蓄积于电感性负载的能量而在开关元件的体二极管(寄生二极管)中流动电流。这可能成为使在开关元件、形成有开关元件的基板、以及形成于相同基板的其他元件之间寄生的晶闸管动作并引起其他元件的破坏的原因。
发明内容
本发明要解决的课题在于，提供一种能够抑制开关元件的寄生元件的动作的半导体装置。
一个实施方式的半导体装置的特征在于，具备设置于相同基板上的开关元件以及二极管，
上述开关元件具有：
第一半导体层，设置于上述基板内，与上述基板电分离；
第一半导体区域，设置于上述第一半导体层的表面；
第二半导体区域，相对于上述第一半导体区域离开地设置于上述第一半导体层的表面，其导电型与上述第一半导体区域为相同；
沟道区域，设置于上述第一半导体层的表面的上述第一半导体区域与上述第二半导体区域之间，其导电型与上述第一半导体区域以及上述第二半导体区域的导电型相反；
栅极绝缘膜，设置于上述沟道区域上；
栅极电极，设置于上述栅极绝缘膜上；
第一电极，与上述第一半导体区域连接；以及
第二电极，与上述第二半导体区域连接，
上述二极管具有：
第二半导体层，设置于上述基板内，与上述基板电分离；
阳极区域，设置于上述第二半导体层的表面；
阴极区域，相对于上述阳极区域离开地设置于上述第二半导体层的表面；
阳极电极，与上述阳极区域连接；以及
阴极电极，与上述阴极区域连接。
根据上述构成的半导体装置，能够抑制开关元件的寄生元件的动作。
附图说明
图1是实施方式的半导体装置的模式截面图。
图2是实施方式的半导体装置的电路图。
图3是表示实施方式的半导体装置的杂质浓度的一例的图。
图4是实施方式的半导体装置的电路图。
图5是其他实施方式的半导体装置的模式截面图。
图6是其他实施方式的半导体装置的模式截面图。
图7是其他实施方式的半导体装置的电路图。
图8是其他实施方式的半导体装置的模式截面图。
图9A～图9C是其他实施方式的半导体装置的模式平面图。
具体实施方式
根据实施方式，半导体装置具备设置于相同基板上的开关元件以及二极管。上述开关元件具有第一半导体层、第一半导体区域、第二半导体区域、沟道区域、栅极绝缘膜、栅极电极、第一电极以及第二电极。上述第一半导体层设置于上述基板内，与上述基板电分离。上述第一半导体区域设置于上述第一半导体层的表面。上述第二半导体区域相对于上述第一半导体区域离开地设置于上述第一半导体层的表面，其导电型与上述第一半导体区域相同。上述沟道区域设置于上述第一半导体层的表面的上述第一半导体区域与上述第二半导体区域之间，其导电型与上述第一半导体区域以及上述第二半导体区域的导电型相反。上述栅极绝缘膜设置于上述沟道区域上。上述栅极电极设置于上述栅极绝缘膜上。上述第一电极与上述第一半导体区域连接。上述第二电极与上述第二半导体区域连接。上述二极管具有第二半导体层、阳极区域、阴极区域、阳极电极以及阴极电极。上述第二半导体层设置于上述基板内，与上述基板电分离。上述阳极区域设置于上述第二半导体层的表面。上述阴极区域相对于上述阳极区域离开地设置于上述第二半导体层的表面。上述阳极电极与上述阳极区域连接。上述阴极电极与上述阴极区域连接。
以下，参照附图对实施方式进行说明。另外，在各附图中对相同要素赋予相同符号。在以下的实施方式中，将第一导电型设为p型、将第二导电型设为n型来进行说明，但将第一导电型设为n型、将第二导电型设为p型也能够实施。
图1是实施方式的半导体装置的模式截面图。
实施方式的半导体装置具有开关元件5、二极管6以及逻辑元件7混合搭载在相同的基板10上的构造。
基板10是P型半导体基板，例如是P型硅基板。此外，以下说明的半导体层(区域)是硅层(区域)。或者，基板10、半导体层(区域)不限定于硅，例如也可以是碳化硅、氮化镓等。
在半导体层的表面上在想要分离的要素之间，例如设置有STI(ShallowTrench Isolation：浅沟槽隔离)构造的绝缘膜30。
在芯片状的半导体装置的中心侧区域，形成有包括逻辑元件7的例如模拟集成电路。开关元件5以及二极管6例如形成于芯片周边区域。开关元件5例如形成于逻辑元件7与二极管6之间的区域。
逻辑元件7和开关元件5通过形成于它们之间的绝缘膜30而绝缘分离。开关元件5和二极管6通过形成于它们之间的绝缘膜30而绝缘分离。
开关元件5例如是P沟道型的DMOS(double diffused metal oxidesemiconductor field effect transistor：双扩散金属氧化物半导体场效应晶体管)。在DMOS中，沟道通过双扩散来形成，将扩散区域的横向扩散的差利用为有效沟道长度。
开关元件5具有形成于基板10内的作为第一半导体层的N型半导体层11。N型半导体层11和P型的基板10进行pn结合，N型半导体层11相对于基板10电分离。基板10接地，N型半导体层11经由N型半导体区域24以及N+型半导体区域33与开关元件5的源极电位连接。
在N型半导体层11的表面上形成有一对P-型半导体区域26，在该P-型半导体区域26之间形成有P型半导体区域23。P型半导体区域23的P型杂质浓度比P-型半导体区域26的P型杂质浓度高。
在P型半导体区域23的表面上作为第一半导体区域形成有P+型漏极区域21。P+型漏极区域21的P型杂质浓度比P型半导体区域23的P型杂质浓度高。
P+型漏极区域21的两侧面与形成于P-型半导体区域26的表面的绝缘膜30相接。
在N型半导体层11的表面上，相对于一对P-型半导体区域26分别离开地形成有一对N型半导体区域24。
在各个N型半导体区域24的表面上，作为第二半导体区域形成有P+型源极区域22。
此外，在各个N型半导体区域24的表面上，与P+型源极区域22邻接地形成有N+型半导体区域33。N+型半导体区域33的N型杂质浓度比N型半导体区域24的N型杂质浓度高。
N+型半导体区域33的一方的侧面与P+型源极区域22相接，另一方的侧面与绝缘膜30相接。
P+型源极区域22的P+型漏极区域21侧的侧面处于N型半导体区域24内。在该N型半导体区域24与P-型半导体区域26之间形成有N型半导体层11。
形成于P+型源极区域22与P-型半导体区域26之间的N型半导体区域24的表面区域以及N型半导体层11的表面区域，作为沟道区域27起作用。
在沟道区域27上以及与该沟道区域27邻接的P-型半导体区域26的表面上设置有栅极绝缘膜29。在栅极绝缘膜29上设置有栅极电极28。
在P+型漏极区域21上作为第一电极设置有漏极电极31。P+型漏极区域21与漏极电极31，通过直接或者经由金属硅化物层等所希望的方法进行欧姆接触，并进行电连接。
在P+型源极区域22上作为第二电极设置有源极电极32。P+型源极区域22与源极电极32，通过直接或者经由金属硅化物层等所希望的方法进行欧姆接触，并进行电连接。
此外，源极电极32还设置在N+型半导体区域33上，并与N+型半导体区域33相接。
开关元件5的各半导体区域以及栅极电极28例如以条纹状的平面图案来形成。
在以上说明的开关元件5中，当对栅极电极28施加所希望的栅极电压时，在沟道区域27形成反型层(P沟道)，通过P+型源极区域22、沟道区域27、P-型半导体区域26、P型半导体区域23以及P+型漏极区域21，在源极电极32与漏极电极31间流动电流。在P-型半导体区域26以及P型半导体区域23中，电流以在绝缘膜30之下的区域绕过的方式流通。
形成于漏极侧的绝缘膜30提高开关元件5的耐压。此外，与P+型漏极区域21相比P型杂质浓度更低的P-型半导体区域26为，当栅极截止时耗尽化，使耐压提高。
此外，在P-型半导体区域26与P+型漏极区域21之间设置有P型杂质浓度处于P-型半导体区域26的P型杂质浓度与P+型漏极区域21的P型杂质浓度的中间的P型半导体区域23，由此能够抑制由于从P-型半导体区域26到P+型漏极区域21杂质浓度急剧变化而引起的耐压降低。
接着，对二极管6进行说明。
二极管6具有形成于基板10内的作为第二半导体层的N型半导体层12。N型半导体层12和P型的基板10进行pn结合，N型半导体层12相对于基板10电分离。基板10接地，N型半导体层12经由N型半导体区域44以及N+型阴极区域42与二极管6的阴极电极52连接。
在N型半导体层12的表面上形成有多个P型半导体区域43以及多个N型半导体区域44。P型半导体区域43以及N型半导体区域44例如以条纹状的平面图案交替排列。P型半导体区域43和N型半导体区域44分离。
在各个P型半导体区域43的表面上形成有P+型阳极区域41。P+型阳极区域41的P型杂质浓度比P型半导体区域43的P型杂质浓度高。
在各个N型半导体区域44的表面上形成有N+型阴极区域42。N+型阴极区域42的N型杂质浓度比N型半导体区域44的N型杂质浓度高。
在P+型阳极区域41与N+型阴极区域42之间设置有绝缘膜30，P+型阳极区域41与N+型阴极区域42通过绝缘膜30而分离。
在P+型阳极区域41上设置有阳极电极51。P+型阳极区域41与阳极电极51，通过直接或者经由金属硅化物层等所希望的方法来进行欧姆接触，并进行电连接。
在N+型阴极区域42上设置有阴极电极52。N+型阴极区域42与阴极电极52，通过直接或者经由金属硅化物层等所希望的方法来进行欧姆接触，并进行电连接。
逻辑元件7具有与DMOS构造的开关元件5、二极管6不同的构造，例如具有CMOS构造。图1中图示出逻辑元件7的一部分(例如N沟道型MOSFET)。
逻辑元件7例如具有形成于基板10内的N型半导体层13。N型半导体层13和P型的基板10进行pn结合，N型半导体层13相对于基板10电分离。
在N型半导体层13的表面上形成有P型半导体区域65。在P型半导体区域65的表面上形成有N+型半导体区域61和N+型半导体区域62。N+型半导体区域61以及N+型半导体区域62的一方作为漏极区域起作用、另一方作为源极区域起作用。
在N+型半导体区域61与N+型半导体区域62之间的沟道区域(P型半导体区域65的表面区域)上，经由栅极绝缘膜29设置有栅极电极28。
此外，在N型半导体层13的表面上与P型半导体区域65邻接地形成有N型半导体区域66。在N型半导体区域66的表面上形成有N+型半导体区域64。
N+型半导体区域64的N型杂质浓度比N型半导体区域66的N型杂质浓度高。
此外，在P型半导体区域65的表面上形成有P+型半导体区域63。在P+型半导体区域63与N+型半导体区域62之间形成有绝缘膜30。在P+型半导体区域63与N+型半导体区域64之间形成有绝缘膜30。
开关元件5、二极管6以及逻辑元件7分别形成在相对于基板10电分离的N型半导体层11、N型半导体层12以及N型半导体层13的表面上。即，开关元件5、二极管6以及逻辑元件7不通过基板10而电连接。
基板10接地，与此相对，N型半导体层11以及N型半导体层12的电位处于高电位。因而，难以从开关元件5、二极管6以及逻辑元件7向基板10流动电流。
开关元件5例如用于输出大电流的H电桥电路、倒相电路、DC-DC转换电路等。
图2是具备实施方式的半导体装置的电路的电路图。
在与电源连接且被供给电源电压(输入电压)Vcc的电源线(输入线)111与接地端子之间，串联连接有上述开关元件(高侧开关元件：high sideswitch)5以及低侧开关元件(low side switch)4。
开关元件5的源极端子(源极电极32)与电源线111连接，漏极端子(漏极电极31)与输出线112连接。
低侧开关元件4例如是N沟道型MOSFET。低侧开关元件4的漏极端子与开关元件5的漏极端子以及输出线112连接。低侧开关元件4的源极端子与接地端子连接。
此外，在电源线111与输出线112之间连接有上述二极管6。二极管6的阳极端子(阳极电极51)与输出线112连接，阴极端子(阴极电极52)与电源线111连接。
在输出线112上作为电感性负载连接有线圈L。因而，开关元件5和二极管6并联连接在电源与线圈L之间。即，开关元件5以及二极管6具有与电源连接的端子以及与线圈L连接的端子。
高侧开关元件5、低侧开关元件4、以及驱动它们的驱动电路、控制电路被集成化为一个芯片。
例如在DC-DC转换器(buck converter)中，通过使高侧开关元件5和低侧开关元件4交替地导通截止，由此输出比输入电压Vcc低的平均输出电压。
在低侧开关元件4导通、高侧开关元件5截止时，从输出端子经由线圈L向低侧开关元件4以及接地端子输出电流。此时，在线圈L中流动电流并蓄积能量。
接着，当高侧开关元件5和低侧开关元件4同时导通时，从电源线111经由开关元件5、4向接地端子流动穿透电流。为了避免该情况，在对开关元件5、4的导通截止的占空进行设定时，设定有开关元件5、4均成为截止的期间即死区时间。
在死区时间期间，开关元件5的栅极截止，但线圈L通过所蓄积的能量而持续流动电流，因此在开关元件5的体二极管(图1中的P型半导体区域23与N型半导体区域11的pn结合)中流动再生电流。此时，存在寄生PNP晶体管91动作的情况。
通过从N型半导体层11和P型基板10的pn结合扩展的耗尽层，实现开关元件5的高耐压化。因此，N型半导体层11的N型杂质浓度以及P型基板10的P型杂质浓度被抑制得较低。
由于N型半导体层11的N型杂质浓度较低，因此寄生PNP晶体管91的基极的复合电流减少、基极电阻94变高，变得容易向基板10流动电流。
并且，由于基板10的寄生电阻93也较高，因此基板10的电位变得容易上升，寄生于开关元件5、基板10以及其他元件7的NPN晶体管100(图1)的基极电位上升，寄生NPN晶体管100动作。
当寄生NPN晶体管100动作时，持续供给寄生PNP晶体管91的基极电流，因此寄生PNP晶体管91不返回到截止，寄生PNP晶体管91持续动作，因此寄生NPN晶体管100也不返回到截止。即，由于寄生晶闸管的动作而引起闭锁，向逻辑元件7流入大电流，担心破坏逻辑元件7。
但是，根据实施方式，在电源与线圈L之间相对于开关元件5并联连接有二极管6。
因而，在死区时间期间中，从线圈L流动的电流I1被分散为向开关元件5的漏极侧流动的电流I"1以及向二极管6的阳极侧流动的电流I'1，能够减小经由开关元件5的寄生PNP晶体管91向基板10流动的电流I"3。
另外，在二极管6也与开关元件5相同地产生寄生PNP晶体管92，但通过减小寄生PNP晶体管92的基极电阻95，能够抑制在基板10流动的电流I'3。
即，二极管6的寄生电阻比开关元件5的寄生电阻低。因此，从线圈L流动的电流I1作为电流I'1以及I'2容易从二极管6的阳极向阴极流动，能够抑制在基板10流动的电流I'3。
通过抑制在基板10流动的电流I"3以及I'3，能够抑制高电阻的基板10的电位上升，能够防止由寄生晶闸管动作引起的闭锁所导致的元件破坏。
在实施方式中，为了使二极管6的寄生电阻比开关元件5的寄生电阻低，例如使N型半导体层12的N型杂质浓度比N型半导体层11的N型杂质浓度高。
图3表示二极管6的N型半导体层12的N型杂质浓度(实线)、开关元件5的N型半导体层11的N型杂质浓度(虚线)的一例。横轴的深度(μm)表示离N型半导体层12以及N型半导体层11各自的表面的深度。
例如，当使二极管6的N型半导体层12的峰值浓度为约5×1016(cm-3)、使开关元件5的N型半导体层11的峰值浓度为约1.3×1016(cm-3)时，与寄生电阻较大的开关元件5的体二极管的N型半导体层11相比，能够使在寄生电阻较小的二极管6的N型半导体层12流动的再生电流更大。
N型半导体层12以及N型半导体层11的N型杂质浓度的范围，虽然也基于所要求的耐压，但设定为1×1016(cm-3)～1×1018(cm-3)。
此外，在图1所示的实施方式中，开关元件5的N型半导体层11以及二极管6的N型半导体层12在P型基板10内分离地形成。即，在N型半导体层11与N型半导体层12之间形成有导电型与它们相反的P型半导体区域。
因此，N型半导体层11和N型半导体层12之间的载流子移动被抑制，能够分别使开关元件5以及二极管6难以进行误动作。
此外，为了使二极管6的寄生电阻比开关元件5的寄生电阻低，例如使二极管6的阳极区域41与阴极区域42之间的距离比开关元件5的漏极区域21与源极区域22之间的距离短。此处的距离表示按照最短距离来连结两个区域间的直线距离。
此外，为了使二极管6的寄生电阻比开关元件5的寄生电阻低，例如还能够使二极管6的布线电阻比开关元件5的布线电阻低。
二极管6的布线电阻是图4所示的阳极布线电阻Rax与阴极布线电阻Rkx之和。阳极布线电阻Rax表示将阳极区域41和输出线112连接的布线的电阻(也包括阳极电极51的电阻)。阴极布线电阻Rkx表示将阴极区域42和电源线111连接的布线的电阻(也包括阴极电极52的电阻)。
开关元件5的布线电阻是图4所示的漏极布线电阻Rdx与源极布线电阻Rsx之和。漏极布线电阻Rdx表示将漏极区域21和输出线112连接的布线的电阻(也包括漏极电极31的电阻)。源极布线电阻Rsx表示将源极区域22和电源线111连接的布线的电阻(也包括源极电极32的电阻)。
例如，如果将开关元件5的布线电阻(Rsx+Rdx)设定为10mΩ、将二极管6的布线电阻(Rax+Rkx)设定为5mΩ，则与开关元件5相比、来自线圈L的再生电流I1更容易向二极管6流动。
例如，通过使二极管6的布线(也包括阳极电极51以及阴极电极52)的宽度大于开关元件5的布线(也包括漏极电极31以及源极电极32)的宽度，由此能够使二极管6的布线电阻比开关元件5的布线电阻低。
此外，通过使电极相对于二极管6的阳极区域41以及阴极区域42进行接触的通孔的数量比电极相对于开关元件5的漏极区域21以及源极区域22进行接触的通孔的数量多，由此能够使二极管6的布线电阻比开关元件5的布线电阻低。
图5是其他实施方式的半导体装置的模式截面图。
在图5所示的半导体装置中，在开关元件5的N型半导体层11和基板10之间设置有N+型埋层120。此外，在二极管6的N型半导体层12和基板10之间设置有N+型埋层120。此外，在逻辑元件7的N型半导体层13和基板10之间设置有N+型埋层120。
N+型埋层120的N型杂质浓度比N型半导体层11的N型杂质浓度、N型半导体层12的N型杂质浓度以及N型半导体层13的N型杂质浓度高。
N+型埋层120的电位被赋予电源电位Vcc。通过该N+型埋层120，开关元件5、二极管6以及逻辑元件7分别可靠地从基板电位分离。
图6是又一个实施方式的半导体装置的模式截面图。
在图6所示的半导体装置中，开关元件5以及二极管6形成于在这些元件间不分离地相连的相同N型半导体层15的表面上。在该情况下，开关元件5以及二极管6也通过N型半导体层15而从P型基板10电分离。
此外，实施方式的开关元件4、5、二极管6能够应用于图7所示的马达控制驱动(Motor Control Driver)电路。图7表示双极驱动方式的马达控制驱动电路，在两个方向上向线圈L流动电流而进行驱动，因此使用两组的高侧开关元件5和低侧开关元件4。
向高侧开关元件5以及低侧开关元件4的栅极输出包括逻辑元件7在内的控制电路70的控制信号。即，控制电路70对开关元件5、4的导通截止进行控制。
如图8所示，低侧开关元件4也与高侧开关元件5、二极管6以及逻辑元件7一起形成在相同的基板10上。
图9A是表示基板10上的逻辑元件7、高侧开关元件5、二极管6以及低侧开关元件4的配置关系的模式平面图。
低侧开关元件4例如是N沟道型的DMOS，具有与P沟道型的DMOS即高侧开关元件5对应的要素的导电型相反的相同构造。在图8所示的低侧开关元件4中，对与上述高侧开关元件5的各要素对应的要素标注符号“N”。
根据以上说明的实施方式，与高侧开关元件5相比，再生电流容易向二极管6侧流动。因此，为了抑制再生电流向逻辑元件7侧流动，优选使基板10上的二极管6的位置与逻辑元件7的位置分离。
在马达控制驱动电路等中，在高侧赋予有马达电源电压的最高电压VM，因此二极管6与高侧开关元件5间的寄生动作不会成为问题，但逻辑元件7的电源电压Vcc比VM低的情况较多，因此当经由基板10向逻辑元件7流动再生电流时，容易因闭锁而产生破坏。
因此，如图8以及图9A所示，在基板10上，在逻辑元件7与二极管6之间配置高侧开关元件5，由此能够抑制在二极管6中流动的再生电流经由基板10向逻辑元件7流动。
或者，也可以如图9B所示，在逻辑元件7与二极管6之间配置高侧开关元件5和低侧开关元件4的双方。
或者，也可以如图9C所示，在逻辑元件7与二极管6之间配置低侧开关元件4。
对本发明的几个实施方式进行了说明，但这些实施方式作为例子来提示的，并不意图对发明的范围进行限定。这些新的实施方式能够以其他各种方式进行实施，在不脱离发明的主旨的范围内能够进行各种省略、置换、变更。这些实施方式及其变形包含于发明的范围及主旨中，并且同样包含于专利请求范围所记载的发明和与其等同的范围中。
例如，作为开关元件也可以使用N型MOSFET。在该情况下，第一半导体层成为P型半导体。例如，通过进一步增加包含第一半导体层周围的N型的半导体层，由此能够使P型的第一半导体层与P型半导体基板电分离。因而，并不限定于半导体基板与第一半导体层成为不同的导电型。通过设置使基板与第一半导体层电分离的半导体层，由此即便基板与第一半导体层为相同导电型，也能够获得本发明的效果。
进而，在二极管中，即便是使第二半导体层为P型的二极管，例如通过进一步增加包含第二半导体层周围的N型的半导体层，由此也能够使P型的第二半导体层和P型半导体基板电分离。

Claims (16)

1.一种半导体装置，其中，
具备设置于相同基板上的开关元件以及二极管，
所述开关元件具有：
第一半导体层，设置于所述基板内，与所述基板电分离；
第一半导体区域，设置于所述第一半导体层的表面；
第二半导体区域，相对于所述第一半导体区域离开地设置于所述第一半导体层的表面，其导电型与所述第一半导体区域相同；
沟道区域，设置于所述第一半导体层的表面的所述第一半导体区域与所述第二半导体区域之间，其导电型与所述第一半导体区域以及所述第二半导体区域的导电型相反；
栅极绝缘膜，设置于所述沟道区域上；
栅极电极，设置于所述栅极绝缘膜上；
第一电极，与所述第一半导体区域连接；以及
第二电极，与所述第二半导体区域连接，
所述二极管具有：
第二半导体层，设置于所述基板内，与所述基板电分离；
阳极区域，设置于所述第二半导体层的表面；
阴极区域，相对于所述阳极区域离开地设置于所述第二半导体层的表面；
阳极电极，与所述阳极区域连接；以及
阴极电极，与所述阴极区域连接。
2.如权利要求1所述的半导体装置，其中，
所述第一半导体层以及所述第二半导体层具有与所述基板的导电型相反的导电型，
所述第一半导体层以及所述第二半导体层相对于所述基板进行pn结合。
3.如权利要求1所述的半导体装置，其中，
所述二极管的寄生电阻比所述开关元件的寄生电阻低。
4.如权利要求1所述的半导体装置，其中，
所述第二半导体层的杂质浓度比所述第一半导体层的杂质浓度高。
5.如权利要求1所述的半导体装置，其中，
所述二极管的所述阳极区域与所述阴极区域之间的距离比所述开关元件的所述第一半导体区域与所述第二半导体区域之间的距离短。
6.如权利要求1所述的半导体装置，其中，
所述二极管的布线电阻比所述开关元件的布线电阻低。
7.如权利要求1所述的半导体装置，其中，
所述第一半导体层以及所述第二半导体层为相同导电型，
所述第一半导体层和所述第二半导体层通过与所述第一半导体层以及所述第二半导体层相反导电型的区域而分离。
8.如权利要求1所述的半导体装置，其中，
还具备埋层，该埋层设置于所述基板与所述第一半导体层之间以及所述基板与所述第二半导体层之间，该埋层的导电型与所述基板相反。
9.如权利要求1所述的半导体装置，其中，
所述开关元件具有DMOS构造。
10.如权利要求1所述的半导体装置，其中，
所述第二电极以及所述阴极电极具有与电源连接的连接端子，所述第一电极以及所述阳极电极具有与电感性负载连接的连接端子。
11.如权利要求1所述的半导体装置，其中，
在所述基板上还具备与所述开关元件以及所述二极管不同构造的逻辑元件。
12.如权利要求11所述的半导体装置，其中，
在所述基板上的所述逻辑元件与所述二极管之间设置有所述开关元件。
13.如权利要求1所述的半导体装置，其中，
所述开关元件具有P沟道型DMOS以及与所述P沟道型DMOS串联连接的N沟道型DMOS。
14.如权利要求13所述的半导体装置，其中，
所述二极管相对于所述P沟道型DMOS并联连接。
15.如权利要求13所述的半导体装置，其中，
在所述基板上还具备与所述P沟道型DMOS、所述N沟道型DMOS以及所述二极管不同构造的逻辑元件。
16.如权利要求15所述的半导体装置，其中，
在所述基板上的所述逻辑元件和所述二极管之间设置有所述P沟道型DMOS以及所述N沟道型DMOS中的至少一方。
CN201410077962.7A 2013-09-13 2014-03-05 半导体装置 Pending CN104465646A (zh)

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