CN111969040B - 一种超结mosfet - Google Patents

一种超结mosfet Download PDF

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CN111969040B
CN111969040B CN202010869506.1A CN202010869506A CN111969040B CN 111969040 B CN111969040 B CN 111969040B CN 202010869506 A CN202010869506 A CN 202010869506A CN 111969040 B CN111969040 B CN 111969040B
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CN111969040A (zh
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任敏
郭乔
蓝瑶瑶
李吕强
高巍
李泽宏
张金平
张波
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University of Electronic Science and Technology of China
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Abstract

本发明属于功率半导体技术领域，涉及一种超结MOSFET。本发明提供的一种超结MOSFET器件，在漂移区引入长度渐变，浓度渐变的第二导电类型半导体柱，通过减小靠近JFET区耐压柱的长度来避免相邻耐压柱横向耗尽，纵向扩展造成的Cgd电容迅速下降，使Cgd～Vds曲线上的最小值点向Vds更大的方向移动，在Vds较小时抬高Cgd电容值，并使Cgd～Vds曲线更平坦。从而既能加快开关时间，减小开关功耗，又能减小开关振荡，缓解EMI，从而改善超结器件的动态特性。

Description

一种超结MOSFET
技术领域
本发明属于功率半导体技术领域，涉及一种超结MOSFET。
背景技术
功率超结MOSFET结构利用相互交替的P柱与N柱代替传统的功率器件的N漂移区，从而有效降低了导通电阻，得到较低的导通功耗。由于其独特的高输入阻抗、低驱动功率、高开关速度、优越的频率特性、以及很好的热稳定性等特点，广泛地应用于开关电源、汽车电子、马达驱动等各种领域。传统的超结MOSFET结构如图1所示。
电容特性对于功率超结器件的开启和关断过程至关重要。其中，栅漏电容Cgd和Vds的曲线会影响到器件的开关速度以及EMI(Electromagnetic Interference)特性。若Cgd曲线出现较大程度的陡降，则超结器件在开关过程中越容易出现电压震荡和电流震荡，造成了EMI噪声损害周围的设备。
发明内容
本发明针对上述问题，提供一种改善动态特性的超结MOSFET器件，在不影响器件耐压的前提下，使Cgd～Vds曲线上的最小值点向Vds更大的方向移动，因而Cgd在低漏压下增大，且Cgd～Vds曲线更平坦，达到既能加快开关速度，减小开关功耗，又能减小开关振荡，缓解EMI的目的，从而改善超结器件的动态特性。
本发明的技术方案是：一种超结MOSFET，如图2所示，包括金属化漏极1、位于金属化漏极1之上的重掺杂第一导电类型半导体衬底2、位于第一导电类型半导体衬底2之上的轻掺杂第一导电类型半导体区3；所述轻掺杂第一导电类型半导体区3顶部两侧具有第二导电类型半导体体区5；所述第二导电类型半导体体区5之间为第一导电类型轻掺杂JFET区8；所述第二导电类型半导体体区5中具有第二导电类型半导体重掺杂接触区6和第一导电类型半导体源区7，所述第一导电类型半导体源区7与第一导电类型轻掺杂JFET区8之间的第二导电类型半导体体区5为沟道区；重掺杂多晶硅电极10覆盖在所述沟道区和第一导电类型JFET区8；重掺杂多晶硅电极10与沟道区和JFET区8之间由栅氧层9相间隔；所述第二导电类型半导体重掺杂接触区6的上表面和第一导电类型半导体源区7的部分上表面与金属化源极11直接接触；金属化源极11与多晶硅电极10之间由绝缘介质层实现电气隔离。第二导电类型半导体体区5的底部还具有2个或2个以上的第二导电类型半导体柱41、42......4n(n大于等于2)，所述第二导电类型半导体柱41、42......4n的顶部与第二导电类型半导体体区5之间接触，相邻第二导电类型半导体柱41、42......4n的侧面互相接触。从远离JFET区8到靠近JFET区8的方向上，第二导电类型半导体柱41、42......4n的长度和掺杂浓度依次递减。
进一步的，所述第二导电类型半导体柱41、42......4n的杂质总量和轻掺杂第一导电类型半导体区3的杂质总量满足电荷平衡。
进一步的，所述栅氧层9的材质为氧化硅、氮化硅、氮氧化硅、氧化铅中的一种。
本发明的有益效果为：在漂移区引入长度渐变，浓度渐变的第二导电类型半导体柱，通过减小靠近JFET区耐压柱的长度来避免相邻耐压柱横向耗尽，纵向扩展造成的Cgd电容迅速下降，使Cgd～Vds曲线上的最小值点向Vds更大的方向移动，在Vds较小时抬高Cgd电容值，并使Cgd～Vds曲线更平坦。从而既能加快开关时间，减小开关功耗，又能减小开关振荡，缓解EMI，从而改善超结器件的动态特性。
附图说明
图1为传统超结MOSFET的结构的主视图；
图2为本发明的超结MOSFET结构的主视图；
图3为实施例2的超结MOSFET结构的主视图；
图4为低漏压下的传统超结器件的Cgd示意图；
图5为Vds＝7V时，传统超结MOSFET结构(a)和本发明超结MOSFET结构(b)的耗尽层仿真对比；
图6为Vds＝20V时，传统超结MOSFET结构(a)和本发明超结MOSFET结构(b)的耗尽层仿真对比；
图7为传统超结MOSFET结构(a)和本发明超结MOSFET结构(b)的Cgd～Vds曲线仿真对比；
图8为传统超结MOSFET结构(a)和本发明超结MOSFET结构(b)的漏极关断电压仿真对比。
附图标记说明：1为金属化漏极，2为第一导电类型半导体衬底，3为第一导电类型半导体轻掺杂外延层，41、42......4n为第二导电类型半导体柱，5为第二导电类型半导体体区，6为第二导电类型半导体重掺杂接触区，7为第一导电类型半导体源区，8为JFET区，9为栅氧层，10为多晶硅电极，11为金属化源极。
具体实施方式
下面结合附图和实施例，详细描述本发明的技术方案：
实施例1
如图2所示，包括金属化漏极1、位于金属化漏极1之上的重掺杂第一导电类型半导体衬底2、位于第一导电类型半导体衬底2之上的轻掺杂第一导电类型半导体区3；所述轻掺杂第一导电类型半导体区3顶部两侧具有第二导电类型半导体体区5；所述第二导电类型半导体体区5之间为第一导电类型轻掺杂JFET区8；所述第二导电类型半导体体区5中具有第二导电类型半导体重掺杂接触区6和第一导电类型半导体源区7，所述第一导电类型半导体源区7与第一导电类型轻掺杂JFET区8之间的第二导电类型半导体体区5为沟道区；重掺杂多晶硅电极10覆盖在所述沟道区和第一导电类型JFET区8；重掺杂多晶硅电极10与沟道区和JFET区8之间由栅氧层9相间隔；所述第二导电类型半导体重掺杂接触区6的上表面和第一导电类型半导体源区7的部分上表面与金属化源极11直接接触；金属化源极11与多晶硅电极10之间由绝缘介质层实现电气隔离。第二导电类型半导体体区5的底部还具有2个或2个以上的第二导电类型半导体柱41、42......4n(n大于等于2)，所述第二导电类型半导体柱41、42......4n的顶部与第二导电类型半导体体区5之间接触，相邻第二导电类型半导体柱41、42......4n的侧面互相接触。从远离JFET区8到靠近JFET区8的方向上，第二导电类型半导体柱41、42......4n的长度和掺杂浓度依次递减。所述第二导电类型半导体柱41、42......4n的杂质总量和轻掺杂第一导电类型半导体区3的杂质总量满足电荷平衡。
本例的工作原理为：
对于传统超结器件，在较小的漏源电压Vds下，轻掺杂第二导电类型体区和低掺杂第一导电类型外延层形成的PN结相互耗尽，栅极与漏极之间的耗尽层宽度决定了耗尽层电容的大小，其Cgd电容在低漏压下的示意图如图4所示。对传统超结MOSFET而言，由于轻掺杂第二导电类型耐压柱和相邻的第一导电类型耐压柱形成的PN结相互横向耗尽，在Vds很小时，如图5(a)和6(a)所示，其横向的耗尽层迅速合并导致了耗尽层的纵向展宽，从而Cgd的值迅速下降，造成Cgd～Vds曲线出现严重的陡降，如图7(a)所示。本发明提出的结构，在漂移区引入长度渐变，浓度渐变的耐压柱，保证其维持电荷平衡，耐压特性不降低。通过减小靠近JFET区耐压柱的长度来避免相邻耐压柱横向耗尽，纵向扩展造成的Cgd电容迅速下降，如图5(b)和6(b)所示，在相同的Vds下，对比传统超结MOSFET，本专利提出的结构其栅极与漏极之间的耗尽层宽度更短，从而Cgd的值更大。可见本专利提出的渐变式耐压柱可以使Cgd最小时对应的Vds值更大，在Vds较小时抬高Cgd电容值，使Cgd～Vds曲线更平坦，如图7(b)所示。在漏极电源电压Vdd＝400V的条件下进行感性负载开关仿真，漏极电压的震荡情况见图8，可见本专利提出的结构可以有效减小开关时超结MOSFET器件的电压震荡和电流震荡，从而抑制开关回路中的EMI电磁辐射噪声。
在实施过程中，可以根据具体情况，在基本结构不变的情况下，进行一定的变通设计。制作器件时还可用碳化硅、砷化镓、磷化铟或锗硅等半导体材料代替体硅。
实施例2
如图3所示，在实施例1的基础上，确定第二导电类型半导体体区5的底部为3个第二导电类型半导体柱41、42和43，所述第二导电类型半导体柱41、42、43的顶部与第二导电类型半导体体区5之间接触，相邻第二导电类型半导体柱41、42、43的侧面互相接触。41、42和43的长度和掺杂浓度分为依次递减。其特征还在于，所述第二导电类型半导体柱41、42和43的杂质总量和轻掺杂第一导电类型半导体区3的杂质总量满足电荷平衡。

Claims (3)

1.一种超结MOSFET，包括金属化漏极（1）、位于金属化漏极（1）之上的重掺杂第一导电类型半导体衬底（2）、位于重掺杂第一导电类型半导体衬底（2）之上的轻掺杂第一导电类型半导体区（3）；所述轻掺杂第一导电类型半导体区（3）顶部两侧具有第二导电类型半导体体区（5）；所述第二导电类型半导体体区（5）之间为第一导电类型轻掺杂JFET区（8）；所述第二导电类型半导体体区（5）中具有并列设置的第二导电类型半导体重掺杂接触区（6）和第一导电类型半导体源区（7），所述第一导电类型半导体源区（7）与第一导电类型轻掺杂JFET区（8）之间的第二导电类型半导体体区（5）为沟道区；重掺杂多晶硅电极（10）覆盖在沟道区、第一导电类型JFET区（8）和部分第一导电类型半导体源区（7）上表面；重掺杂多晶硅电极（10）与第一导电类型半导体源区（7）、沟道区和JFET区（8）之间由栅氧层（9）隔离；所述第二导电类型半导体重掺杂接触区（6）的上表面和第一导电类型半导体源区（7）的部分上表面与金属化源极（11）直接接触；金属化源极（11）与多晶硅电极（10）之间由绝缘介质层电气隔离；其特征在于，第二导电类型半导体体区（5）的底部还具有多个第二导电类型半导体柱，所述第二导电类型半导体柱的顶部与第二导电类型半导体体区（5）接触，相邻第二导电类型半导体柱的侧面接触；从远离第一导电类型轻掺杂JFET区（8）的一端到靠近第一导电类型轻掺杂JFET区（8）的一端，第二导电类型半导体柱的长度和掺杂浓度依次递减。
2.根据权利要求1所述的一种超结MOSFET，其特征在于，所述多个第二导电类型半导体柱的杂质总量和轻掺杂第一导电类型半导体区（3）的杂质总量满足电荷平衡。
3.根据权利要求2所述的一种超结MOSFET，其特征在于所述第一导电类型半导体为n型半导体，所述第二导电类型半导体为p型半导体；或者所述第一导电类型半导体为p型半导体，所述第二导电类型半导体为n型半导体。
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