CN113921607B - Stepped groove transverse insulated gate bipolar transistor structure and manufacturing method - Google Patents

Stepped groove transverse insulated gate bipolar transistor structure and manufacturing method Download PDF

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CN113921607B
CN113921607B CN202111513776.XA CN202111513776A CN113921607B CN 113921607 B CN113921607 B CN 113921607B CN 202111513776 A CN202111513776 A CN 202111513776A CN 113921607 B CN113921607 B CN 113921607B
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subsection
region
shallow trench
bipolar transistor
insulated gate
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CN113921607A (en
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叶家明
葛成海
李庆民
林滔天
祝进专
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Jingxincheng Beijing Technology Co Ltd
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Jingxincheng Beijing Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]

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  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention discloses a structure and a manufacturing method of a stepped groove transverse insulated gate bipolar transistor, and the transverse insulated gate bipolar transistor at least comprises the following components: a substrate; a drift region disposed on the substrate; the first well region is arranged in parallel with the drift region; the stepped shallow trench isolation structure is arranged in the drift region and at least comprises a first subsection and a second subsection, the first subsection is arranged on the second subsection, and the width of the first subsection is larger than that of the second subsection; a first doped region disposed on the drift region; the second doped region is arranged on the first well region; the drain electrode is arranged on the first doped region; the source electrode is arranged on the second doping area; and the grid is positioned on the stepped shallow trench isolation structure and the first well region. The stepped groove transverse insulated gate bipolar transistor structure and the manufacturing method can improve the performance of the transistor.

Description

Stepped groove transverse insulated gate bipolar transistor structure and manufacturing method
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a stepped trench lateral insulated gate bipolar transistor structure and a manufacturing method thereof.
Background
In recent years, due to the gradual popularization of 5G communication technology, the demand of power semiconductor devices is increasing. Insulated Gate Bipolar Transistor (IGBT) is a commonly used power device, and has been widely noticed by people because its manufacturing process is simple and easy to implement. Among them, the Lateral Insulated Gate Bipolar Transistor (LIGBT) has the advantages of Gate voltage control, large current density, small conduction voltage drop, and the like, and is widely applied in the fields of new energy and various electronic consumption. However, when the emitter voltage is too large, a PN junction is turned on to generate a voltage jump phenomenon, and thus, it is an important research to provide a LIGBT that is resistant to high voltage and has low driving power consumption.
Disclosure of Invention
The invention aims to provide a stepped trench lateral insulated gate bipolar transistor structure and a manufacturing method thereof.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the invention provides a step groove transverse insulated gate bipolar transistor structure, which at least comprises:
substrate:
a drift region disposed on the substrate;
the first well region is arranged in parallel with the drift region;
the stepped shallow trench isolation structure is arranged in the drift region and at least comprises a first subsection and a second subsection, the first subsection is arranged on the second subsection, and the width of the first subsection is larger than that of the second subsection;
a first doped region disposed on the drift region;
the second doped region is arranged on the first well region;
the drain electrode is arranged on the first doped region;
the source electrode is arranged on the second doping area; and
and the gate electrode is positioned on the stepped shallow trench isolation structure and the first well region.
In an embodiment of the invention, at least one corner is provided at the junction of the first and second sections.
In an embodiment of the invention, the top and the bottom of the stepped shallow trench isolation structure and the corner at the connection of the first subsection and the second subsection are configured to be circular arc-shaped.
In an embodiment of the invention, the width of the first sub-portion is 2 to 3 times of the width of the second sub-portion.
In an embodiment of the invention, the depth of the first section is one third to one half of the depth of the second section.
In an embodiment of the invention, a depth of the drift region is greater than a depth of the first well region.
In an embodiment of the invention, a depth of the first well region is the same as a depth of the stepped shallow trench isolation structure.
Another object of the present invention is to provide a method for manufacturing a step-trench lateral insulated gate bipolar transistor structure, including:
providing a substrate;
forming a step shallow trench isolation structure on the substrate, wherein the step shallow trench isolation structure at least comprises a first subsection and a second subsection, the first subsection is arranged on the second subsection, and the width of the first subsection is larger than that of the second subsection;
forming a drift region outside the stepped shallow trench isolation structure;
forming a first well region on one side of the drift region;
forming a first doped region on the drift region;
forming a second doped region on the first well region;
forming a drain electrode on the first doping area;
forming a source electrode on the second doping area; and
and forming a gate electrode on the stepped shallow trench isolation structure and the first well region.
In an embodiment of the present invention, a method for manufacturing the gate electrode includes:
removing an oxide layer on the substrate:
forming a gate oxide layer on the substrate:
forming a polysilicon layer on the gate oxide layer;
patterning the polycrystalline silicon layer, and etching the polycrystalline silicon layer and the grid oxide layer to form a grid structure; and
and forming a self-aligned silicide blocking layer on the grid structure.
The invention also provides a semiconductor integrated device which comprises a plurality of step groove transverse insulated gate bipolar transistors.
According to the step groove transverse insulated gate bipolar transistor structure and the manufacturing method thereof, the step shallow groove isolation structure is formed between the grid electrode and the drain electrode, and the grid electrode covers part of the step shallow groove isolation structure, so that the grid oxide layer can be prevented from being broken down, the withstand voltage of the groove transverse insulated gate bipolar transistor is improved, and the hot carrier effect is reduced. The corner of the shallow groove is arc-shaped, so that the breakdown phenomenon can be reduced, and the voltage resistance of the groove transverse insulated gate bipolar transistor can be improved. By changing the shape and the depth of the shallow trench structure, the trench lateral insulated gate bipolar transistor applied to different voltages is manufactured so as to be applied to different voltage environments. In summary, the invention provides a step-trench lateral insulated gate bipolar transistor structure and a manufacturing method thereof, which can improve the performance of the trench lateral insulated gate bipolar transistor and improve the applicability of the trench lateral insulated gate bipolar transistor.
Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described advantages at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of an embodiment of a lateral insulated gate bipolar transistor.
FIG. 2 is a schematic diagram of an embodiment of an oxide layer and a nitride layer.
FIG. 3 is a schematic diagram of an embodiment of a patterned photoresist layer.
FIG. 4 is a schematic diagram of a shallow trench location in an embodiment.
FIG. 5 is a diagram illustrating a second etching position of the shallow trench in an embodiment.
FIG. 6 is a schematic diagram of a stepped shallow trench and a shallow trench in one embodiment.
FIG. 7 is a schematic diagram of a post-planarization STI structure in an embodiment.
FIG. 8 is a schematic view of an embodiment of a STI structure after removal of the nitride layer.
FIG. 9 is a schematic diagram of a well distribution according to an embodiment.
FIG. 10 is a diagram illustrating a gate oxide layer and a polysilicon layer in accordance with an embodiment.
FIG. 11 is a diagram illustrating a gate structure according to an embodiment.
FIG. 12 is a schematic view illustrating the distribution of the spacer dielectric layer in an embodiment.
Fig. 13 is a schematic view of a sidewall structure in an embodiment.
FIG. 14 is a schematic view of an embodiment of a doped region profile.
FIG. 15 is a diagram illustrating an exemplary salicide block distribution.
FIG. 16 is a schematic diagram of an embodiment of a lateral IGBT electrode layout.
FIG. 17 is a schematic diagram of an embodiment of a lateral insulated gate bipolar transistor.
FIG. 18 is a schematic diagram of an embodiment of a lateral insulated gate bipolar transistor.
Fig. 19 is a schematic view of a semiconductor integrated device in an embodiment.
Description of reference numerals:
10 a substrate; 101 a first deep well region; 102 a second deep well region; 103 a drift region; 104 a first well region; 105 a second well region; 106 an oxide layer; 107 a nitride layer; 108 a first patterned photoresist layer; 109 a second patterned photoresist layer; 110 step shallow trenches; 1101 a first recess; 1102 a second recess; 111 shallow trenches; 112 an insulating medium; 113 step shallow trench isolation structures; 1131 a first subsection; 1132 second subsection; 114 shallow trench isolation structures; 115 a gate oxide layer; 116 a polysilicon layer; 117 side wall dielectric layers; 118 a sidewall structure; 119 a gate structure; a first doped region 120; 1201 a first type doped region; 1202 a second type doped region; 121 a second doped region; 1211 a first type doped region; 1212 a second type doped region; 122 a third doped region; 123 self-aligned silicide blocking layers; 124 an insulating layer; 21 a drain electrode; 22 a grid electrode; 23 source electrode; a base electrode of 24; 25 are isolated.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The Lateral Insulated Gate Bipolar Transistor (LIGBT) provided by the invention has excellent performance and can be widely applied to various fields such as communication, traffic, energy, medicine, household appliances, aerospace and the like.
Referring to fig. 1, in an embodiment of the invention, a lateral igbt includes a substrate 10, a drift region 103 disposed on the substrate 10, and a first well region 104, wherein a step shallow trench isolation structure 113 is disposed between the drift region 103 and the first well region 104. The sti structures 113 may be designed in different shapes to improve the performance of the igbt.
Referring to fig. 2, in an embodiment of the invention, a substrate 10 is first provided, and the substrate 10 may be any material suitable for formation, such as a base plate like a silicon wafer, and the substrate may be a P-doped semiconductor substrate or an N-doped semiconductor substrate, in this embodiment, the substrate 10 is, for example, a P-doped semiconductor substrate.
Referring to fig. 2, in an embodiment of the invention, an oxide layer 106 is formed on the substrate 10, the oxide layer 106 is, for example, a dense silicon oxide, and the oxide layer 106 may be formed on the substrate 10 by, for example, a thermal oxidation method, an in-situ water vapor growth method, or a chemical vapor deposition method. In this embodiment, the substrate 10 is placed in a furnace tube at a temperature of, for example, 900 ℃ to 1150 ℃, oxygen is introduced, and the substrate 10 reacts with the oxygen at a high temperature to form the dense oxide layer 106. The thickness of the oxide layer 106 is, for example, 10 to 50nm, specifically, 30nm, 40nm, 45nm, or 50 nm.
Referring to fig. 2, in an embodiment of the invention, a nitride layer 107 is formed on the oxide layer 106, and the nitride layer 107 is, for example, silicon nitride or a mixture of silicon nitride and silicon oxide. The oxide layer 106 serves as a buffer layer to improve the stress between the substrate 10 and the nitride layer 107. In the present invention, the nitride layer 107 can be formed on the oxide layer 106 by, for example, LPCVD (Low Pressure Chemical Vapor Deposition). Specifically, for example, the substrate 10 with the oxide layer 106 is placed in a furnace filled with dichlorosilane and ammonia gas, and reacted at a pressure of, for example, 2 to 10T and a temperature of, for example, 700 to 800 ℃ to deposit the nitride layer 107. The thickness of the nitride layer 107 can be adjusted by controlling the heating time, and in some embodiments, the thickness of the nitride layer 107 is, for example, 50nm to 200nm, specifically, 60nm, 75nm, 80nm, 100nm, 150nm, 180nm, or 200 nm. The nitride layer 107 protects the substrate 10 from the Chemical Mechanical Polishing (CMP) process involved in the fabrication of the sti structures. The nitride layer 107 can be used as a mask during the formation of the shallow trench, and the substrate 10 at other positions is protected from damage during etching of the substrate 10.
Referring to fig. 3 to 5, in an embodiment of the invention, a photoresist layer may be formed on the nitride layer 107 by, for example, a spin coating method, and a photoresist pattern may be formed on the photoresist layer by exposure and development processes, and the photoresist pattern is used to locate the position of the shallow trench. After the substrate 10 is quantitatively etched, the photoresist layer is removed to form the stepped shallow trench 110 and the shallow trench 111.
Referring to fig. 6 and 16 to 18, the number of steps of the stepped shallow trench 110 is not limited in the present invention, and at least two steps, specifically, for example, 2 to 8 steps, of the stepped shallow trench 110 may be selected according to specific manufacturing requirements. The step shape of the stepped shallow trench 110 may be selected, for example, to be "T-shaped", "right-angled", or "inverted pyramid", and the width of one end near the nitride layer 107 may be larger than that of the other end. In the present embodiment, the stepped shallow trench 110 includes two steps as an example. In other embodiments, the number and shape of the stepped shallow trenches 110 can be flexibly selected.
Referring to fig. 3 to 6, in an embodiment of the invention, the shallow trenches 111 are located at two sides of the substrate 10, and the stepped shallow trench 110 is located between the two shallow trenches 111 and is disposed close to one of the shallow trenches 111. The shallow trench 111 is formed by one-step etching, and the stepped shallow trench 110 is formed by etching on the basis of the shallow trench 111. First, a first patterned photoresist layer 108 is formed on the nitride layer 107, and the first patterned photoresist layer 108 is used to define the position of the trench region. After the first patterned photoresist layer 108 is formed, the nitride layer 107, the oxide layer 106 and a portion of the substrate 10 under the lithographic pattern are quantitatively removed by, for example, dry etching using the first patterned photoresist layer 108 as a mask to obtain shallow trenches 111, wherein the shallow trenches 111 at the middle position are further etched to obtain the step shallow trenches 110. After the shallow trench 111 is formed, the first patterned photoresist layer 108 is removed, and a second patterned photoresist layer 109 is formed, i.e., the second patterned photoresist layer 109 covers the shallow trench 111 and a portion of the nitride layer 107, and a photoresist pattern is formed beside the middle shallow trench 111, as shown in fig. 5. Then, the second patterned photoresist layer 109 is used as a mask to quantitatively remove the nitride layer 107, the oxide layer 106 and a portion of the substrate 10 by, for example, dry etching, and the etching depth is shallower than the first etching depth, and the second patterned photoresist layer 109 is removed to form the stepped shallow trench 110. In the present embodiment, the stepped shallow trench 110 includes two recesses, i.e., a first recess 1101 and a second recess 1102. The groove formed by the second etching and the first etching part which is flush with the groove are defined as a first concave part 1101, the area which is etched for the first time and is positioned below the second etching is defined as a second concave part 1102, namely, the first concave part 1101 is arranged on the second concave part 1102, the width of the first concave part 1101 is larger than that of the second concave part 1102, and a corner exists at the joint of the first concave part 1101 and the second concave part 1102. In other embodiments, the step number and shape of the stepped shallow trench 110 may be controlled by the etching process.
Referring to fig. 6, in an embodiment of the invention, the depth of the second recess 1102 is set to be 300 to 700nm, for example, 400nm, 500nm or 600nm, and the width of the second recess 1102 is set to be 160 to 220nm, for example, 170nm, 190nm or 210 nm. The depth of the first recess 1101 is set to be, for example, one third to one half of the depth of the second recess 1102, specifically, 100 to 350nm, and the width of the first recess 1101 is, for example, 2 to 3 times the width of the second recess 1102, specifically, 320 to 440 nm. However, in some embodiments, the width of the first recess 1101 may be further increased, for example, 4 to 7 times the width of the second recess 1102, according to the higher requirement for the voltage of the lateral igbt. In this embodiment, all corners of the stepped shallow trench 110, including the top corner, the bottom corner, and the connection between the first recess and the second recess, and the bottom corner of the shallow trench 111 are all configured to be arc-shaped, so that on one hand, charges can be prevented from being accumulated at the sharp corner to cause excessive current and breakdown the transistor, and on the other hand, the corners are configured to be arc-shaped to disperse stress, improve compressive stress, and reduce the occurrence of the fractured condition at this location. By setting the width of the first recess 1101 to be greater than the width of the second recess 1102, a shallow trench isolation structure can be conveniently prepared, and the shallow trench isolation structure with the shape can be prepared, so that the voltage of the lateral insulated gate bipolar transistor can be improved, and the voltage endurance capability of the transistor can also be improved.
Referring to fig. 7, in one embodiment of the present invention, an insulating dielectric 112 is deposited in the stepped shallow trenches 110 and 111 and on top of the trenches, the insulating dielectric 112 being formed to cover the surface of the nitride layer 107. The present invention is not limited to the deposition manner of the insulating dielectric 112, and the insulating dielectric 112 can be formed by High Density Plasma CVD (HDP-CVD) or High Aspect Ratio CVD (HARP-CVD), for example. After the insulating dielectric 112 is deposited, a high temperature (e.g., 800-1200 ℃) annealing process may be performed to increase the density and stress of the insulating dielectric 112. The insulating medium 112 is, for example, silicon oxide with high adaptability to a grinding tool, and in other embodiments, the insulating medium 112 may also be insulating material such as fluorosilicate glass.
Referring to fig. 7 to 8, in an embodiment of the invention, after the insulating medium 112 is completely prepared, a planarization process is performed on the insulating medium 112, for example, a Chemical Mechanical Polishing (CMP) process is used to planarize the insulating medium 112 and a portion of the nitride layer 107, so that the heights of the insulating medium 112 and the nitride layer 107 are consistent. The polished nitride layer 107 is then etched and removed, but the invention is not limited to the method for removing the nitride layer 107, for example, dry etching or wet etching is used. In this embodiment, for example, an acid solution is used for etching, specifically, phosphoric acid with a volume fraction of, for example, 85% to 88% is used for etching the nitride layer 107 at, for example, 150 to 165 ℃. The nitride layer 107 is removed by selecting a larger hot phosphoric acid as an etching solution for etching the nitride layer 107 and the oxide layer 106 to form a stepped shallow trench isolation structure 113 and a shallow trench isolation structure 114. After the nitride layer 107 is removed, a shallow trench step height is formed between the stepped shallow trench isolation structure 113 and the oxide layer 106 and between the shallow trench isolation structure 114 and the oxide layer 106.
Referring to fig. 6 to 8, in an embodiment of the invention, the stepped sti structure 113 is disposed in the stepped sti 110, and the sti structure 114 is disposed in the sti 111. And the shape of the stepped shallow trench isolation structure 113 is the same as the shape and size ratio of the stepped shallow trench 110, that is, the stepped shallow trench isolation structure 113 at least includes a first sub-portion 1131 and a second sub-portion 1132, and a plurality of corners may be disposed at the connection between the first sub-portion 1131 and the second sub-portion 1132. The width of the first sub-portion 1131 is greater than the width of the second sub-portion 1132, the depth of the first sub-portion 1131 is set to be, for example, one third to one half of the depth of the second sub-portion 1132, and the width of the first sub-portion 1131 is, for example, 2 to 3 times the width of the second sub-portion 1132. In other embodiments, the number and shape of the segments of the stepped shallow trench isolation structure 113 are set according to the number and shape of the steps of the first shallow trench 110. By setting the width of the first sub-portion 1131 to be greater than the width of the second sub-portion 1132, the voltage of the lateral insulated gate bipolar transistor can be increased when the lateral insulated gate bipolar transistor works, and the width of the stepped shallow trench isolation structure 113 near one end of the oxide layer 106 is larger, so that the gate oxide layer prepared in the later period can be prevented from being broken down, and the voltage endurance capability of the transistor can be improved.
Referring to fig. 9, in an embodiment of the invention, after the preparation of the shallow trench structure is completed, ion implantation is performed on the substrate 10 to form different well regions. Firstly, a doped region with a higher concentration than the substrate is implanted at the bottom of the substrate 10 with a high implantation energy, that is, a deep well region 101 is formed at the bottom of the substrate, and then a doped region with a higher concentration than the deep well region 101 is implanted at two ends of the deep well region 101 to form a second well region 105, wherein the second well region 105 is located at the outer side of the shallow trench isolation structure 114 and at the bottom of a part of the shallow trench isolation structure 114. The deep well region 101 and the second well region 105 may be doped with the same type, and may be configured as an N type or a P type. In this embodiment, the deep well region 101 and the second well region 105 are, for example, N-type deep wells, and the doping ions are phosphorus (P), arsenic (As), or the like. By arranging the second well region 105, the lateral insulated gate bipolar transistor can be used as an isolation region for isolating other devices, and meanwhile, the current capability of the device is improved.
Referring to fig. 9, in an embodiment of the invention, a second deep well region 102 is implanted on the first deep well region 101 and between the second deep well regions 105, and the types of the first deep well region 101 and the second deep well region 102 are different. In the present embodiment, the second deep well region 102 is, for example, a P-type deep well, and the doping ions are boron (B) or gallium (Ga). A lower energy implant is performed over the second deep well region 102 forming a drift region 103. The bottom of the drift region 103 is in contact with the second deep well region 102, and the drift region 103 is located between the shallow trench isolation structures 114 and in contact with one of the shallow trench isolation structures 114, and wraps the stepped shallow trench isolation structure 113 therein. In the present invention, the drift region 103 may be N-type or P-type, and in this embodiment, the drift region 103 is, for example, N-type, and the doping ions are phosphorus (P) or arsenic (As). The first deep well region 101 and the second deep well region 102 constitute a contact region for an emitter (i.e., drain) of a lateral insulated gate bipolar transistor.
Referring to fig. 9, in an embodiment of the invention, a lower energy implantation doping is performed between the drift region 103 and another shallow trench isolation structure 114 to form a first well region 104, and the first well region 104 is in contact with the another shallow trench isolation structure 114 and has a depth consistent with that of the shallow trench isolation structure 114, so as to effectively avoid interference between different well regions. The second deep well region 102 is disposed between the first well region 104 and the stepped shallow trench isolation structure 113 for isolation. In various embodiments, the first well region 104 may be configured as a P-type or an N-type, and in this embodiment, the first well region 104 is configured as a P-type, for example, and the doped ions are boron (B) or gallium (Ga). And the forward blocking voltage mainly drops on the drift region 103, and the depth of the drift region 103 is set to be deeper than that of the first well region 104, so that the withstand voltage value of the device is improved.
Referring to fig. 9 to 10, in an embodiment of the invention, after the well region is formed, the oxide layer 106 on the surface of the well region is removed, for example, by dry etching or wet etching. In this embodiment, a wet etching process is performed, for example, by using a hydrofluoric acid solution, and a portion of the shallow trench structure is removed at the same time. The height of the shallow trench structure is basically consistent with that of each well region. And then forming the gate oxide layer 115 on the surface of the well region and the shallow trench structure, the invention is not limited to the formation method of the gate oxide layer 115, and the gate oxide layer is formed by using a chemical vapor deposition or physical vapor deposition method, for example. In the present embodiment, the gate oxide layer 115 is formed by an In-situ steam Generation (ISSG) method, for example, wherein the gate oxide layer 115 is made of a material such as silicon oxide, and the thickness of the gate oxide layer 115 is set to be 3 to 10nm, for example, In other embodiments, the thickness of the gate oxide layer 115 may also be set according to actual requirements. The oxide layer 106 inevitably generates scratch in the shallow trench forming process, and the flatness and defect rate of the gate oxide layer 115 are ensured by resetting the gate oxide layer 115, so that the breakdown and leakage phenomena of the lateral insulated gate bipolar transistor are improved.
Referring to fig. 10 to 11, in an embodiment of the invention, a polysilicon layer 116 is deposited on the gate oxide layer 115, the polysilicon layer 116 may be P-type or N-type, and the doping type of the polysilicon layer 116 is different from that of the substrate 10. In the present embodiment, the polysilicon layer 116 is, for example, N-type, and the thickness of the polysilicon layer 116 is, for example, 300 to 400nm, in other embodiments, the thickness of the polysilicon layer 116 may be set according to actual requirements.
Referring to fig. 11, in an embodiment of the invention, a photoresist is formed on the polysilicon layer 116, and then the photoresist is exposed and developed to form a patterned photoresist layer (not shown). Polysilicon layer 116 is then etched, for example, by a dry etch process, a wet etch process, or a combination of a dry etch process and a wet etch process. In this embodiment, for example, the polysilicon layer 116 is sequentially anisotropically etched by using a dry etching process, and the gate oxide layer 115 may serve as an etch stop layer for the polysilicon layer 116. When the polysilicon layer 116 is etched to the gate oxide layer 115, a new photoresist needs to be formed, and then the photoresist is exposed and developed to expose the gate oxide layer 115 to be etched, and then the gate oxide layer 115 is etched by, for example, a dry etching process, a wet etching process, or a combination of the dry etching process and the wet etching process. In this embodiment, the gate oxide layer 115 is sequentially anisotropically etched using, for example, a dry etching process. In other embodiments, the polysilicon layer 116 and the gate oxide layer 115 may also be etched in one step, specifically, the photoresist layer is used as a mask to etch the polysilicon layer 116, and after the polysilicon layer 116 is etched, the gate oxide layer 115 is etched by changing etching gas. The etched polysilicon layer 116 and the gate oxide layer 115 may be defined as a gate structure 119, and the gate structure 119 covers a portion of the first well region 104, a portion of the stepped shallow trench isolation structure 113, and a portion of the drift region 103 and a portion of the second deep well region 102 between the first well region 104 and the stepped shallow trench isolation structure 113.
Referring to fig. 12 to 13, in an embodiment of the invention, after the gate structure 119 is formed, a sidewall dielectric layer 117 is formed on the polysilicon layer 116, the well regions and the shallow trench structure, and the material of the sidewall dielectric layer 117 is, for example, silicon oxide, silicon nitride or a stacked layer of silicon oxide and silicon nitride. After the sidewall dielectric layer 117 is formed, for example, etching processes such as photolithography may be used to remove the gate structure 119, the shallow trench isolation structure 114, a portion of the stepped shallow trench isolation structure 113, and a portion of the sidewall dielectric layer 117 on the first well region 104, and the sidewall dielectric layers 117 located at two sides of the gate structure 119 are remained. The reserved side wall dielectric layer 117 defines a side wall structure 118, the height of the side wall structure 118 is consistent with that of the gate structure 119, the width of the side wall structure 118 is gradually increased from the top to the bottom of the gate structure 119, and the insulating side wall structure 118 is arranged to prevent the prepared transverse insulated gate bipolar transistor from generating an electric leakage phenomenon. In this embodiment, the sidewall structure 118 is, for example, an arc shape, and in other embodiments, the sidewall structure 118 may also be a triangular shape or an L shape.
Referring to fig. 14, in an embodiment of the invention, after the formation of the sidewall structure 118, a first doped region 120 is disposed between the stepped shallow trench isolation structure 113 and the shallow trench isolation structure 114 at the top of the drift region 103, a second doped region 121 is disposed at the top region of the first well region 104, and a third doped region 122 is disposed at the top region of the second well region 105. The first doped region 120 includes a first type doped region 1201 and a second type doped region 1202, the first type doped region 1201 and the second type doped region 1202 may be P-type or N-type, and the doping types of the first type doped region 1201 and the second type doped region 1202 are different. In the present embodiment, the first-type doped region 1201 is, for example, a P-type, and the second-type doped region 1202 is, for example, an N-type. Likewise, the second doped region 121 includes a first-type doped region 1211 and a second-type doped region 1212. The third doped region 122 is disposed on top of the second well 105, and the doping type of the third doped region 122 may be P-type or N-type, in this embodiment, the third doped region 122 is disposed as N-type, for example.
Referring to fig. 15, in an embodiment of the invention, after the doped region is formed, a Self-Aligned silicide blocking layer (SAB) 123 is formed on the doped region, i.e., the Self-Aligned silicide blocking layer 123 covers the first doped region 120, the second doped region 121, the third doped region 122 and the top of the gate structure 119. The salicide block layer 123 is, for example, a metal silicide such as silicon cobalt (SiCo) to reduce contact resistance. In this embodiment, the method for forming the salicide block layer 123 may form a dielectric layer on the surface where the salicide block layer 123 needs to be formed, then etch and remove the dielectric layer in the region where the salicide block layer 123 needs to be formed to expose the region where the salicide block layer 123 is formed, then deposit a metal material, such as titanium, cobalt, or nickel, on the exposed region, react the metal material with silicon in the semiconductor substrate by a rapid annealing process to form a metal silicide, and finally remove the unreacted metal and the dielectric layer.
Referring to fig. 14 to 16, in an embodiment of the invention, after the salicide block layer 123 is formed, an insulating layer 124 is formed on the salicide block layer 123, the insulating layer 124 covers the entire surface of the substrate, and the insulating layer 124 is, for example, a silicon oxide layer to protect the lateral igbt. A plurality of vias are provided in the insulating layer 124 until the salicide block 123 is exposed, and metal lines, such as tungsten, copper, or silver, are provided in the vias to form electrodes. The electrodes include a drain 21, a gate 22, a source 23, a base 24, and an isolation 25, wherein the drain 21 is disposed on the first doped region 120 in connection with the salicide block 123 on the first doped region 120, and the drain 21 is located between the first type doped region 1201 and the second type doped region 1202. The gate 22 is disposed on the gate structure 119 and connected to the salicide block layer 123 on the gate structure 119. The source 23 is located on the second-type doped region 1212 of the second doped region 121 and connected to the salicide block layer 123 on the second-type doped region 1212. The base 24 is located on the first-type doped region 1211 of the second doped region 121 and connected to the salicide block layer 123 on the first-type doped region 1211 for grounding. The isolation 25 is disposed on the third doped region 122 at both ends and is connected to the salicide block layer 123 on the third doped region 122. By arranging the drain 21, the gate 22 and the source 23 to form a complete loop, the igbt operates, the base 24 can conduct current, the isolation 25 can apply a high voltage, and the second well region 105 serves as an isolation structure of the lateral igbt.
Referring to fig. 14-18, in one embodiment of the present invention, during operation of the lateral igbt, the gate 22 is applied with a forward voltage to form a channel, which provides a base current to the transistor to turn the transistor on. At this time, electrons flow from the source 23 to the drain 21, the current at the drain 21 is large, and the special structure of the stepped shallow trench isolation structure 113 can improve the electric field distribution, prevent the gate oxide layer from being broken down, so as to improve the withstand voltage of the device, and reduce the hot carrier effect, so as to improve the performance of the lateral insulated gate bipolar transistor. Meanwhile, when the first-type doped region 1201 of the first doped region 120 is applied with a voltage, since the drift region 103, the second deep well region 102 and the first well region 104 have resistances, the voltage of the first-type doped region 1201 is greater than the voltage of the drift region 103, and the voltage of the drift region 103 is greater than the voltage of the first-type doped region 1211 of the second doped region 121, so that the PNP amplification condition is satisfied, and the PNP amplification function is achieved.
Referring to fig. 19, in an embodiment of the invention, a semiconductor integrated device is provided, which includes a plurality of lateral insulated gate bipolar transistors according to the invention. The semiconductor integrated device provided by the embodiment of the invention comprises two lateral insulated gate bipolar transistors provided by the invention, and the two lateral insulated gate bipolar transistors are connected through the drain 21, that is, the two lateral insulated gate bipolar transistors share the same drain 21, and in terms of layout, the two lateral insulated gate bipolar transistors are symmetrical with respect to the middle drain 21. In the manufacturing process, two stepped shallow trench isolation structures 113 are respectively arranged on two sides of the drain 21 to improve the voltage endurance of the semiconductor integrated device, so as to be applied to different working environments. The manufacturing process of the semiconductor integrated device is consistent with that of a single transverse insulated gate bipolar transistor, the number of the transverse insulated gate bipolar transistors is different, and the manufacturing process of the semiconductor integrated device is not explained much. By arranging the integrated device sharing the drain electrode, the volume of the semiconductor integrated device can be reduced, the utilization efficiency of the substrate is improved, and the cost is saved.
The embodiments of the invention disclosed above are intended merely to aid in the explanation of the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims (7)

1. A lateral insulated gate bipolar transistor structure with a step trench, comprising:
a substrate;
a drift region disposed on the substrate;
the first well region is arranged side by side with the drift region, and the depth of the drift region is greater than that of the first well region;
the step shallow trench isolation structure is arranged in the drift region and at least comprises a first subsection and a second subsection, the first subsection is arranged on the second subsection, the width of the first subsection is larger than that of the second subsection, the width of the first subsection is 2-3 times of that of the second subsection, the depth of the first subsection is one third to one half of that of the second subsection, and the first subsection and the second subsection are in direct contact;
a first doped region disposed on the drift region;
the second doped region is arranged on the first well region;
the drain electrode is arranged on the first doped region;
the source electrode is arranged on the second doping area; and
and the grid is positioned on the stepped shallow trench isolation structure and the first well region.
2. The staircase trench lateral insulated gate bipolar transistor structure of claim 1 wherein at least one corner is provided at the junction of the first and second sections.
3. The staircase trench lateral insulated gate bipolar transistor structure of claim 2 wherein the corners of the top and bottom of the staircase shallow trench isolation structure and the junction of the first and second sections are rounded.
4. The staircase trench lateral insulated gate bipolar transistor structure of claim 1 wherein the depth of the first well region is the same as the depth of the staircase shallow trench isolation structure.
5. A method for manufacturing a step trench lateral insulated gate bipolar transistor is characterized by comprising the following steps:
providing a substrate;
forming a step shallow trench isolation structure on the substrate, wherein the step shallow trench isolation structure at least comprises a first subsection and a second subsection, the first subsection is arranged on the second subsection, the width of the first subsection is larger than that of the second subsection, the width of the first subsection is 2-3 times of that of the second subsection, the depth of the first subsection is one third to one half of that of the second subsection, and the first subsection and the second subsection are in direct contact;
forming a drift region outside the stepped shallow trench isolation structure so that the stepped shallow trench isolation structure is arranged in the drift region;
forming a first well region on one side of the drift region, wherein the depth of the drift region is greater than that of the first well region;
forming a first doped region on the drift region;
forming a second doped region on the first well region;
forming a drain electrode on the first doping area;
forming a source electrode on the second doping area; and
and forming a gate electrode on the stepped shallow trench isolation structure and the first well region.
6. The method for manufacturing a stepped trench lateral insulated gate bipolar transistor according to claim 5, wherein the method for manufacturing the gate electrode comprises the following steps:
removing an oxide layer on the substrate:
forming a gate oxide layer on the substrate:
forming a polysilicon layer on the gate oxide layer;
patterning the polycrystalline silicon layer, and etching the polycrystalline silicon layer and the grid oxide layer to form a grid structure; and
and forming a self-aligned silicide blocking layer on the grid structure.
7. A semiconductor integrated device comprising a plurality of the staircase trench lateral insulated gate bipolar transistor structures of claim 1.
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