CN101853854A - Groove power MOS component with improved type terminal structure and manufacturing method thereof - Google Patents
Groove power MOS component with improved type terminal structure and manufacturing method thereof Download PDFInfo
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Abstract
The invention adopts a big deep groove. The injection of the entire second conductive type foreign ions is firstly carried out under the precondition that a photoetching mask is not used, then a circle of second conductive type well region at the periphery of a component is etched off by the etching of the big deep groove, the selective injection of the second conductive type foreign ions is indirectly realized, the residual conductive polycrystalline silicon of the big deep groove, which is close to the side wall of one side of a cellular region, is utilized as the voltage endurance structure of a differential voltage protection region, a contact hole of a cut-off protection region is also manufactured in the big deep groove, and afterwards a high potential is formed by communicating a circle of floating metal connecting line and a drain electrode through a first conductive type region, thereby realizing the function of surface charge cut-off. In the invention, a potential line is converged at the right side of the big deep groove in a more centralized way, the convergence property is very good, the area of the entire terminal protection structure can be saved by reducing the distance from the cut-off protection region to the differential voltage protection region, and the performance of the component can also not be influenced.
Description
Technical field
The present invention relates to power MOS (Metal Oxide Semiconductor) device, particularly deep-groove power MOS component and the manufacture method thereof that realizes with 4 reticle is mainly used in 20V～70V low pressure and low power MOS device.
Background technology
Deep-groove power MOS component is to grow up on the basis of plane formula power MOS (Metal Oxide Semiconductor) device.Compare advantages such as it has, and conducting resistance is low, saturation pressure reduction, switching speed is fast, gully density is high, chip size is little with the plane formula power MOS (Metal Oxide Semiconductor) device; Adopt the plough groove type structure, eliminated parasitic JFET (technotron) effect that the plane formula power MOS (Metal Oxide Semiconductor) device exists.Deep-groove power MOS component has developed into the main flow of mesolow large-power MOS part at present.Day by day ripe along with the deep groove large power MOS device technology, market competition is growing more intense, and the manufacturing cost of a chips and profit all have been according to how many RMB of sharing money to calculate.So improve profit margin and become one of problem that those skilled in the art pay close attention to the most for how further reducing manufacturing cost.Improving integrated level and reducing the photoetching number of times is the method that effectively reduces cost the most.But the raising of integrated level is confined to the capacity of equipment of semiconductor manufacturing enterprise and technological ability and is difficult to realize, maybe can bring many negative issues to the devices switch electrical property.Therefore, the optimised devices structure is optimized the technology manufacturing process, is improving groove power MOS cost performance simultaneously, and the electrical property that improves device is the direction of this area research.
In the existing processes process, make a kind of deep-groove power MOS component, generally need use 5～7 reticle.With 6 versions is example, finishes according to following technological process manufacturing usually:
The first step provides the semiconductor epitaxial layers silicon chip with two relative interareas of first conduction type;
In second step, on first interarea, form first silicon oxide layer, silicon oxide layer on the spot;
In the 3rd step, optionally shelter and etching first silicon oxide layer definition active area and terminal protection district; (reticle 1)
The 4th step formed second silicon oxide layer on first interarea, optionally shelter and etching second silicon oxide layer, and remaining zone is as deep plough groove etched hard mask; (reticle 2)
The 5th step, utilize hard mask layer to carry out the deep plough groove etched of first interarea, second silicon oxide layer is removed in the intact back of etching;
In the 6th step, form the 3rd oxide layer, i.e. grid silicon oxide layer in first interarea and the growth of zanjon cell wall;
In the 7th step, form conductive polycrystalline silicon floor in the 3rd silicon oxide layer surface;
The 8th step, conductive polycrystalline silicon is carried out general etching, be formed on the conductive polycrystalline silicon in the groove;
In the 9th step, in having first interarea that a silicon oxide layer stops, carry out the second conductive type impurity ion and inject, and form the cellular array and by both second conduction type doped regions separately of ring by the boiler tube knot;
In the tenth step, utilization is sheltered, and carries out the first conductive type impurity ion selectivity and injects, and form the cellular array and end both first conduction type doped regions separately of ring by annealing process; (reticle 3)
The 11 step, dielectric layer deposit and optionally sheltering and etching, form the cellular array contact hole, guard ring contact hole and by the loop contacts hole.And after contact hole etching was intact, the second conductive type impurity ion that carries out contact hole injected and RTA (rapid thermal annealing), forms the second conduction type doped region; (reticle 4)
In the 12 step, form metal level in the dielectric layer surface, and optionally shelter and etching sheet metal; (reticle 5)
The 13 step, the passivation layer deposit, and optionally shelter and the etching passivation layer; (reticle 6, optional)
In the 14 step, thinning back side and metal layer on back deposit form drain electrode.
Disregard optional manufacture process of the 13 step, whole manufacturing process relates to 5 photoetching altogether.Generally speaking, manufacturing expense is that the number of times that is used in whole manufacturing process with its expensive mask aligner is closely-related.If can on the basis of existing 5 photoetching, reduce by 1 photoetching, and not increase other too many steps, just manufacturing cost can be reduced by 10%～15%, this numerical value will be a very fair margin of profit growth point for the semiconductor chip industry.
Publication number is the device architecture that the Chinese patent " a kind of deep groove large power MOS device and manufacture method thereof " of CN101211981A discloses a kind of 4 reticle.Used 4 photolithography plates are respectively: channeled layer photolithography plate 1, source region layer photolithography plate 2, contact hole layer photolithography plate 3, metal level photolithography plate 4.(is example to adopt two dividing groove) as shown in Figure 1; it is characterized in that: P-trap 6 is present in the entire device zone; dividing potential drop protection zone C and all adopt the groove-shaped conductive polycrystalline silicon structure of floating by protection zone D does not promptly link to each other with any electrode with definite current potential.The problem of its existence is: the dividing potential drop protection zone C of this device, employing be groove-shaped conductive polycrystalline silicon structure, the P-trap 6a between two groove 3a and the 3b is a floating state, the P-trap 6a current potential of floating is subjected to the influence of external environment easily.The MOS device is when the end ground connection of grid source; drain electrode 12 adds forward bias voltage; the voltage of MOS device is mainly shared near the groove 3a of cellular region A by the P-trap in the groove outside of a cellular structure of cellular region A outer most edge and dividing potential drop protection zone C; and C other groove and the P-trap dividing potential drop ability that can play in dividing potential drop protection zone is very little; will cause electric-field intensity distribution extremely inhomogeneous like this; the scope that really plays the dividing potential drop effect is very little, and most of dividing potential drop protection zone C dividing potential drop structural area is not fully utilized.And when improving the drain electrode forward bias voltage, the MOS device has reduced the voltage endurance capability of device easily in the regional area premature breakdown.And this structure adopts separate groove structure respectively owing to the dividing potential drop protection zone with by the protection zone, need take bigger chip area.
The content of invention
At the existing deep-groove power MOS component that 4 reticle realize and the above-mentioned shortcoming of manufacture method thereof utilized; the applicant has carried out improving research; a kind of power MOS (Metal Oxide Semiconductor) device with groove and manufacture method thereof of improved terminal structure are proposed; technology manufacturing process by 4 reticle is realized the deep-groove power MOS component structure; it has performance such as conducting featured resistance, puncture is withstand voltage, parasitic capacitance preferably, has saved the used area of terminal protection structure simultaneously.
Technical scheme of the present invention is as follows:
A kind of power MOS (Metal Oxide Semiconductor) device with groove of improved terminal structure, comprise and be positioned at the cellular region that the semiconductor substrate center is made up of cellular, and the terminal protection structure of cellular region periphery, the cellular in the described cellular region by being positioned at groove conductive polycrystalline silicon and unify; Described terminal protection structure comprises the protection zone of ending in the inboard dividing potential drop protection zone and the outside;
Described dividing potential drop protection zone and use same deep trench by the protection zone;
Sidewall protection structure is adopted in described dividing potential drop protection zone, and described sidewall protection structure is formed by described deep trench and the residual conductive polycrystalline silicon of sidewall thereof; Described deep trench is positioned at second conductive type layer, and its degree of depth extend into first conductive type epitaxial layer of second conductive type layer below; Described deep trench wall surface growth has the insulated gate oxide layer, and described deep trench has conductive polycrystalline silicon by on the sidewall of cellular region one side; Described deep trench is covered by dielectric, is coated with metal connecting line on the dielectric;
Described described contact hole is positioned at described deep trench by protection zone employing contact hole structure, and its degree of depth is passed the first conduction type doped region of deep trench below, extend into first conductive type epitaxial layer of first conduction type doped region below; Be filled with the metal connecting line of floating in the described contact hole;
Described deep trench extends to the street area outside the device always from the zone that the device outermost makes a circle.
The degree of depth of described deep trench is greater than the degree of depth of cellular region internal channel.
The metal connecting line of described dividing potential drop protection zone and the metal connecting line by the protection zone are same metal connecting line.
Extend in the zone of conductive polycrystalline silicon in the described cellular region groove between dividing potential drop protection zone and cellular region, and extending clearing end is a closed circular groove, and its width is greater than the width of cellular region internal channel; The gate electrode fairlead is opened in the described annular ditch groove, and metal connecting line links to each other with conductive polycrystalline silicon in the groove.
In the technique scheme, for N moldeed depth power MOS (Metal Oxide Semiconductor) device with groove, described first conduction type is the N type, and second conduction type is the P type; For P moldeed depth power MOS (Metal Oxide Semiconductor) device with groove, described first conduction type is the P type, and second conduction type is the N type.
A kind of manufacture method of power MOS (Metal Oxide Semiconductor) device with groove of improved terminal structure comprises following processing step:
The first step provides the semiconductor epitaxial layers silicon chip with two relative interareas of first conduction type;
In second step, on first interarea, form first silicon oxide layer, i.e. pad oxide;
In the 3rd step, carry out the second general conductive type impurity ion in first interarea and inject, and form second conduction type doped region, the i.e. well region by the boiler tube knot;
The 4th step formed second silicon oxide layer on first interarea, optionally shelter and etching second silicon oxide layer, and remaining zone is as deep plough groove etched hard mask;
The 5th step, utilize hard mask layer to carry out the deep plough groove etched of first interarea, second silicon oxide layer is removed in the intact back of etching;
In the 6th step, form the 3rd oxide layer, i.e. grid silicon oxide layer in first interarea and the growth of zanjon cell wall;
In the 7th step, form conductive polycrystalline silicon floor in the 3rd silicon oxide layer surface;
The 8th step, conductive polycrystalline silicon is carried out general etching, be formed on the conductive polycrystalline silicon in the groove;
The 9th step, utilize reticle optionally to shelter, the first conductive type impurity ion that carries out first interarea injects, and forms first conduction type doped region, the i.e. source area by annealing process again;
In the tenth step, the dielectric layer deposit is also optionally sheltered and etching, forms the contact hole of cellular array and ends the loop contacts hole;
In the 11 step, in dielectric layer surface and contact hole, fill metal level, and optionally shelter and etching sheet metal;
In the 12 step, thinning back side and metal layer on back deposit form drain electrode;
Further comprising the steps of between described the 11 step and the 12 step: the passivation layer deposit, optionally shelter and the etching passivation layer.
In the technique scheme, for the manufacture method of N moldeed depth power MOS (Metal Oxide Semiconductor) device with groove, described first conduction type is the N type, and second conduction type is the P type; For the manufacture method of P moldeed depth power MOS (Metal Oxide Semiconductor) device with groove, described first conduction type is the P type, and second conduction type is the N type.
Useful technique effect of the present invention is:
The present invention and publication number are that the Chinese patent of CN101211981A is compared, and difference is the dividing potential drop protection zone and used same big deep trench by the ring protection district, and its width encloses street area outside the device from device periphery one.The dividing potential drop protection zone is to utilize the conductive polycrystalline silicon that can remain in trenched side-wall in the sidewall of deep trench is grown insulated gate oxide layer and etching polysilicon process to realize the effect of dividing groove.Utilize this big deep trench, directly opening contact hole in groove by the ring protection district.On structure; dividing potential drop protection zone and the metal connecting line in the ring protection district are same metal connecting line; groove is same groove; like this with dividing potential drop protection zone and very compact by the ring protection district; by reducing the area of can minimizing whole terminal to a certain degree protecting structure by the distance of protection zone and dividing potential drop protection zone; to device withstand voltage, conducting resistance can be not influential simultaneously.
Description of drawings
Fig. 1 is the sectional view of the disclosed deep-groove power MOS component of CN101211981A.
Fig. 2 is the vertical view of deep-groove power MOS component of the present invention.
Fig. 3 is the sectional view of deep-groove power MOS component of the present invention, cuts open along X-X line among Fig. 3.
Fig. 4～8th, the schematic diagram of deep-groove power MOS component of the present invention each work step in manufacturing process.
Fig. 9 is the simulation result schematic diagram of the disclosed deep-groove power MOS component of CN101211981A.
Figure 10 is the simulation result schematic diagram of deep-groove power MOS component of the present invention.
Figure 11 is that deep-groove power MOS component of the present invention shortens the simulation result schematic diagram after protection zone and dividing potential drop protection zone distance.
Figure 12 is the BV simulation curve figure of the disclosed deep-groove power MOS component of CN101211981A.
Figure 13 is the BV simulation curve figure of deep-groove power MOS component of the present invention.
Figure 14 is that deep-groove power MOS component of the present invention shortens the BV simulation curve figure after protection zone and dividing potential drop protection zone distance.
In the above accompanying drawing: A, cellular region; B, gate electrode wire lead termination zone; C, dividing potential drop protection zone; D, by the protection zone; E, main knot; 1, N+ substrate; 2, N-epitaxial loayer; 3,3a, 3b, 3 ', 3 " grooves; 4, insulated gate oxide layer; 5,5 ', conductive polycrystalline silicon; 6,6a, P-well region; 7, N+ source area; 8, pad oxide; 9, first dielectric layer; 10, second dielectric layer; 11, potential lines (solid line), 12, drain terminal metal (drain electrode); 13, contact hole; 14, metal connecting line; 15, electric current line (solid line); 16, depletion layer boundaries (dotted line).
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described further.
Fig. 2, Fig. 3 are respectively the schematic diagrames of deep groove large power MOS device top plan view of the present invention and section.As shown in Figure 2, the central area of deep groove large power MOS device semiconductor substrate of the present invention is cellular region A; As shown in Figure 3, the cellular in the cellular region A by being positioned at groove conductive polycrystalline silicon 5 and unify.Cellular region A top is by 14 layers of covering of complete metal connecting line, 14 layers of metal connecting lines with each cellular in the horizontal direction with the vertical direction parallel connection, form cellular region, as source electrode; Below first dielectric layer 9 and second dielectric layer 10 integral body that the conductive polycrystalline silicon 5 in the groove connects into, and draw (see figure 2) by the conductive polycrystalline silicon in the groove of strip 5 at the edge of cellular region A, be connected with the gate electrode wire lead termination area B of the outer circle of cellular region A, form gate electrode.(annotate: the groove structure among Fig. 3 below the B zone is discontinuous, so all there is the B zone in not all cross section.) periphery of cellular region A is provided with terminal protection structure, the terminal protection structure of present embodiment is by the dividing potential drop protection zone C that is positioned at inner ring and be positioned at forming by protection zone D of outer ring.
As shown in Figure 3; dividing potential drop protection zone C and by protection zone D use same deep trench 3 '; deep trench 3 ' width extend to street area outside the device (zone that need cut when described street area is the wafer cutting, not shown) from the zone that the device outermost makes a circle always.Deep trench 3 ' the degree of depth be slightly larger than the degree of depth of cellular region A internal channel 3.
As shown in Figure 3, dividing potential drop protection zone C adopts sidewall protection structure, this sidewall protection structure by deep trench 3 ' and residual conductive polycrystalline silicon 5 of sidewall ' form; Deep trench 3 ' be positioned at 6 layers of P-traps, its degree of depth extend into the N-epitaxial loayer 2 of 6 layers of below of P-trap; The growth of deep trench 3 ' wall surface has insulated gate oxide layer 4, deep trench 3 ' lean on conductive polycrystalline silicon 5 is arranged on the sidewall of cellular region A one side '; Described deep trench 3 ' covered by first dielectric layer 9 and second dielectric layer 10, first dielectric layer 9 and second dielectric layer 10 are dielectric, are coated with metal connecting line 14 on the dielectric.
As shown in Figure 3, adopt the contact hole structure by protection zone D, contact hole 13 be positioned at described deep trench 3 ', its degree of depth is passed the N+ source area 7 of deep trench 3 ' below, extend into N-epitaxial loayer 2; Be filled with the metal connecting line of floating 14 in the contact hole 13; The metal connecting line 14 of dividing potential drop protection zone C and be same metal connecting line by the metal connecting line 14 of protection zone D.
As shown in Figure 3, extend in the zone of the conductive polycrystalline silicon 5 in the cellular region A groove between dividing potential drop protection zone C and cellular region S, and extending clearing end is a closed circular groove 3 ", its width is greater than the width of cellular region A internal channel 3; The gate electrode fairlead is opened in annular ditch groove 3 " in, " interior conductive polycrystalline silicon links to each other for metal connecting line 14 and annular ditch groove 3.
Under the same conditions, to conductive polycrystalline silicon 5, N+ source electrode 7 short circuit ground connection in the groove of the MOS device (patent CN101211981A) of existing structure and MOS device of the present invention, drain terminal metal (drain electrode) 12 adds forward voltage, obtains distribution schematic diagram (Fig. 9～Figure 11) and BV (puncture voltage) simulation curve figure (Figure 12～Figure 14) of potential lines on the MOS device.
As Fig. 9～shown in Figure 11, be positioned at the depletion layer that 16 of depletion layer boundaries (dotted line) on P-trap 6 and the N-epitaxial loayer 2 have constituted the reverse bias PN junction, dense cluster shape solid line in the depletion layer is a potential lines 11, the dense degree of potential lines 11 has been reacted electric field strength herein, is electric current line 15 perpendicular to the solid line of potential lines 11.Potential line distribution from Fig. 9; the problem that the MOS device of existing structure exists is: a) the most potential lines 11 in the depletion layer is concentrated convergence in the outer right wall of the dividing groove 3a of the corresponding close cellular region of dividing potential drop protection zone C (Fig. 1) and the insulating medium layer of top; and the outer wall corresponding to the dividing groove 3b on the left of float P trap 6a and the described P of the floating trap layer between adjacent two dividing groove 3a, 3b only is distributed with minority potential lines 11 in the C of dividing potential drop protection zone; therefore can cause whole dividing potential drop protection zone Electric Field Distribution extremely inhomogeneous, occur too early partial breakdown easily.B) existing structure P trap is through entire device; because the P trap is through the entire device zone; cause being wrapped in P well region the inside by the N+ source electrode of protection zone; so just do not realize ending normally protection zone and drain electrode by the N+ substrate; the function that the realization of N-epitaxial loayer directly is connected; sharp and drain electrode equipotential realizes the function that the device surface electric charge ends by the protection zone thereby just can't well embody, and promptly the protection zone of ending of existing structure is not truly an electric charge cut-off region.From the potential line distribution of Figure 10, what the potential lines 11 of MOS device of the present invention was more concentrated restrains on big deep trench right side, and convergence is very good, can disperse the electric field strength at main knot E place effectively and uniformly, improves voltage endurance capability.
Figure 10 is under the situation identical with the chip area that has the MOS device now, simulation result schematic diagram of the present invention.Figure 11 is at the simulation result schematic diagram that shortens on the basis of Figure 10 after protection zone and dividing potential drop protection zone distance.Contrast Figure 10 and Figure 11 are as can be known; use same deep trench owing to dividing potential drop of the present invention protection zone with by the protection zone; therefore include bigger idle area, thereby, can save the area of whole terminal protection structure by reducing the distance to the dividing potential drop protection zone by the protection zone.
As Figure 12～shown in Figure 14, the MOS device (patent CN101211981A) of existing structure and the puncture voltage of MOS device of the present invention are all more than 20V.Contrast Figure 13 and Figure 14 simultaneously as can be known, shorten after protection zone and dividing potential drop protection zone distance, can not have influence on the performance of device.
The foregoing description is described with N moldeed depth power MOS (Metal Oxide Semiconductor) device with groove.The present invention also can be used for P moldeed depth power MOS (Metal Oxide Semiconductor) device with groove, only need with wherein doping type or conduction type by the P type change the N type into, the N type changes the P type into and gets final product.
Principle to terminal protection structure of the present invention describes below:
The mechanism of action of guard ring structure is; (drain electrode adds forward voltage when device is in forward bias voltage following time; source electrode and grounded-grid); to there be an electric field longitudinally; electric field strength maximum point (be power line compact district) will be present in main knot E (in the cellular array; by a cellular of the outermost of center points toward edge, the P trap that guard ring district direction is pointed in its groove outside is the main E of knot with the formed PN junction of N-epitaxial loayer).The longitudinal electric field between drain-to-source, also there is transverse electric field simultaneously from chip periphery to center cellular array area.When increasing to the depletion layer that makes main knot E gradually, the value of main knot E reversed bias voltage extends to below the terminal protection ring; there is a very thin depletion layer in the guard ring groove near the meeting of cellular region direction; its built-in field is opposite with main knot E outside depletion layer built-in field direction, and therefore the power line at main knot E place can be stretched makes it smooth.Can weaken through main knot E zone electric field strength like this, reach the effect that improves puncture voltage.
The mechanism of action by ring structure is, adopt the contact hole structure by ring, be filled with metal connecting line in the contact hole, metal connecting line forms equipotential by contact hole and the first following conductive type epitaxial layer, promptly when drain terminal adds a high potential, should also be to be in high potential by the metal connecting line in ring zone, promptly the small leakage current (surface electronic, electric charge) that exists of device inside all can be cut off metal connecting line that the district suspends and absorbs and end to fall.
Shown in Fig. 4～8, it is as follows that the present invention makes the method step of above-mentioned deep-groove power MOS component:
The first step, being provided at grows on the N+ substrate 1 silicon chip of N-epitaxial loayer 2; (see figure 4)
Second step formed first silicon oxide layer on N-epitaxial loayer 2, promptly pad oxide 8, thickness from 50 dusts to 500 dusts; (see figure 4)
The 3rd step, carry out the second general conductive type impurity ion in N-epitaxial loayer 2 and inject, and form the second conduction type doped region by the boiler tube knot, promptly the P-well region 6; (see figure 4)
The 4th step formed second silicon oxide layer on N-epitaxial loayer 2, optionally shelter and etching second silicon oxide layer, and remaining zone is as deep plough groove etched hard mask;
The 5th step, utilize hard mask layer to carry out deep trench 3 etchings, second silicon oxide layer is removed in the intact back of etching; (see figure 5)
The 6th step formed the 3rd oxide layer in N-epitaxial loayer 2 and the growth of deep trench 3 walls, and promptly grid silicon oxide layer 4; (see figure 5)
In the 7th step, form conductive polycrystalline silicon floor in grid silicon oxide layer 4 surfaces;
The 8th step, conductive polycrystalline silicon is carried out general etching, be formed on the conductive polycrystalline silicon 6 in the groove; (see figure 5)
The 9th step, utilize reticle optionally to shelter, the N+ foreign ion that carries out in the N-epitaxial loayer 2 injects, and forms the first conduction type doped region by annealing process again, and promptly the N+ source area 7; (see figure 6)
In the tenth step, first dielectric layer 9 and 10 deposits of second dielectric layer are also optionally sheltered and etching, form the cellular array and end the contact hole 13 that encircles; (see figure 7)
In the 11 step, in second dielectric layer, 10 surfaces and contact hole 13, form metal level 14, and optionally shelter and etching sheet metal 14; (see figure 8)
In the 12 step, thinning back side and metal layer on back deposit form drain electrode 12; (see figure 8)
Between the 11 step and the 12 step, also comprise the passivation layer deposit, optionally shelter step with the etching passivation layer.
Equally, the foregoing description is described with the manufacture method of N moldeed depth power MOS (Metal Oxide Semiconductor) device with groove.The present invention also can be used for the manufacture method of P moldeed depth power MOS (Metal Oxide Semiconductor) device with groove, only need with wherein doping type or conduction type by the P type change the N type into, the N type changes the P type into and gets final product.
Above-described only is preferred implementation of the present invention, the invention is not restricted to above embodiment.Be appreciated that those skilled in the art under the prerequisite that does not break away from spirit of the present invention and design, can make other improvement and variation.
Claims (7)
1. the power MOS (Metal Oxide Semiconductor) device with groove of an improved terminal structure, comprise and be positioned at the cellular region that the semiconductor substrate center is made up of cellular, and the terminal protection structure of cellular region periphery, the cellular in the described cellular region by being positioned at groove conductive polycrystalline silicon and unify; Described terminal protection structure comprises the protection zone of ending in the inboard dividing potential drop protection zone and the outside, it is characterized in that:
Described dividing potential drop protection zone and use same deep trench by the protection zone;
Sidewall protection structure is adopted in described dividing potential drop protection zone, and described sidewall protection structure is formed by described deep trench and the residual conductive polycrystalline silicon of sidewall thereof; Described deep trench is positioned at second conductive type layer, and its degree of depth extend into first conductive type epitaxial layer of second conductive type layer below; Described deep trench wall surface growth has the insulated gate oxide layer, and described deep trench has conductive polycrystalline silicon by on the sidewall of cellular region one side; Described deep trench is covered by dielectric, is coated with metal connecting line on the dielectric;
Described described contact hole is positioned at described deep trench by protection zone employing contact hole structure, and its degree of depth is passed the first conduction type doped region of deep trench below, extend into first conductive type epitaxial layer of first conduction type doped region below; Be filled with the metal connecting line of floating in the described contact hole;
For N moldeed depth power MOS (Metal Oxide Semiconductor) device with groove, described first conduction type is the N type, and second conduction type is the P type; For P moldeed depth power MOS (Metal Oxide Semiconductor) device with groove, described first conduction type is the P type, and second conduction type is the N type.
2. according to the power MOS (Metal Oxide Semiconductor) device with groove of the described improved terminal structure of claim 1, it is characterized in that: described deep trench extends to the street area outside the device always from the zone that the device outermost makes a circle.
3. according to the power MOS (Metal Oxide Semiconductor) device with groove of the described improved terminal structure of claim 1, it is characterized in that: the degree of depth of described deep trench is greater than the degree of depth of cellular region internal channel.
4. according to the power MOS (Metal Oxide Semiconductor) device with groove of the described improved terminal structure of claim 1, it is characterized in that: the metal connecting line of described dividing potential drop protection zone and the metal connecting line by the protection zone are same metal connecting line.
5. according to the power MOS (Metal Oxide Semiconductor) device with groove of the described improved terminal structure of claim 1, it is characterized in that: extend in the zone of the conductive polycrystalline silicon in the described cellular region groove between dividing potential drop protection zone and cellular region, extending clearing end is a closed circular groove, and its width is greater than the width of cellular region internal channel; The gate electrode fairlead is opened in the described annular ditch groove, and metal connecting line links to each other with conductive polycrystalline silicon in the groove.
6. the manufacture method of the power MOS (Metal Oxide Semiconductor) device with groove of an improved terminal structure is characterized in that comprising following processing step:
The first step provides the semiconductor epitaxial layers silicon chip with two relative interareas of first conduction type;
In second step, on first interarea, form first silicon oxide layer, i.e. pad oxide;
In the 3rd step, carry out the second general conductive type impurity ion in first interarea and inject, and form second conduction type doped region, the i.e. well region by the boiler tube knot;
The 4th step formed second silicon oxide layer on first interarea, optionally shelter and etching second silicon oxide layer, and remaining zone is as deep plough groove etched hard mask;
The 5th step, utilize hard mask layer to carry out the deep plough groove etched of first interarea, second silicon oxide layer is removed in the intact back of etching;
In the 6th step, form the 3rd oxide layer, i.e. grid silicon oxide layer in first interarea and the growth of zanjon cell wall;
In the 7th step, form conductive polycrystalline silicon floor in the 3rd silicon oxide layer surface;
The 8th step, conductive polycrystalline silicon is carried out general etching, be formed on the conductive polycrystalline silicon in the groove;
The 9th step, utilize reticle optionally to shelter, the first conductive type impurity ion that carries out first interarea injects, and forms first conduction type doped region, the i.e. source area by annealing process again;
In the tenth step, the dielectric layer deposit is also optionally sheltered and etching, forms the contact hole of cellular array and ends the loop contacts hole;
In the 11 step, in dielectric layer surface and contact hole, fill metal level, and optionally shelter and etching sheet metal;
In the 12 step, thinning back side and metal layer on back deposit form drain electrode;
For the manufacture method of N moldeed depth power MOS (Metal Oxide Semiconductor) device with groove, described first conduction type is the N type, and second conduction type is the P type; For the manufacture method of P moldeed depth power MOS (Metal Oxide Semiconductor) device with groove, described first conduction type is the P type, and second conduction type is the N type.
7. according to the manufacture method of the power MOS (Metal Oxide Semiconductor) device with groove of the described improved terminal structure of claim 6, it is characterized in that: further comprising the steps of between described the 11 step and the 12 step: the passivation layer deposit, optionally shelter and the etching passivation layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101584562A CN101853854B (en) | 2010-03-12 | 2010-03-12 | Groove power MOS component with improved type terminal structure and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010101584562A CN101853854B (en) | 2010-03-12 | 2010-03-12 | Groove power MOS component with improved type terminal structure and manufacturing method thereof |
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| Publication Number | Publication Date |
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| CN101853854A true CN101853854A (en) | 2010-10-06 |
| CN101853854B CN101853854B (en) | 2012-11-21 |
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| CN2010101584562A Active CN101853854B (en) | 2010-03-12 | 2010-03-12 | Groove power MOS component with improved type terminal structure and manufacturing method thereof |
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| CN102751327A (en) * | 2011-04-21 | 2012-10-24 | 茂达电子股份有限公司 | Voltage-withstanding termination structure of power device |
| CN104810246A (en) * | 2014-01-29 | 2015-07-29 | 北大方正集团有限公司 | Power device and manufacture method thereof |
| CN105070747A (en) * | 2011-12-09 | 2015-11-18 | 英飞凌科技股份有限公司 | Anchoring structure and intermeshing structure |
| JP2018110165A (en) * | 2016-12-28 | 2018-07-12 | 富士電機株式会社 | Semiconductor device and manufacturing method for semiconductor device |
| CN109148280A (en) * | 2018-07-11 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | Improve the method for polysilicon step side metal residual |
| CN110085659A (en) * | 2014-05-14 | 2019-08-02 | 英飞凌科技奥地利有限公司 | Edge region has the semiconductor devices of field dielectric |
| CN111725300A (en) * | 2020-07-16 | 2020-09-29 | 深圳市瑞之辰科技有限公司 | Terminal structure of MOSFET device and preparation method and application thereof |
| CN112289684A (en) * | 2020-10-28 | 2021-01-29 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of power device and device |
| CN113571497A (en) * | 2021-07-16 | 2021-10-29 | 上海华虹挚芯电子科技有限公司 | IGBT device structure and process method |
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| CN109148280A (en) * | 2018-07-11 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | Improve the method for polysilicon step side metal residual |
| CN111725300A (en) * | 2020-07-16 | 2020-09-29 | 深圳市瑞之辰科技有限公司 | Terminal structure of MOSFET device and preparation method and application thereof |
| CN112289684A (en) * | 2020-10-28 | 2021-01-29 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of power device and device |
| CN112289684B (en) * | 2020-10-28 | 2023-06-30 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of power device and device |
| CN113571497A (en) * | 2021-07-16 | 2021-10-29 | 上海华虹挚芯电子科技有限公司 | IGBT device structure and process method |
| CN117116996A (en) * | 2023-10-24 | 2023-11-24 | 合肥海图微电子有限公司 | Power device and manufacturing method thereof |
| CN117116996B (en) * | 2023-10-24 | 2024-05-14 | 合肥海图微电子有限公司 | Power device and manufacturing method thereof |
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