CN111477733A - Chip packaging method - Google Patents
Chip packaging method Download PDFInfo
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- CN111477733A CN111477733A CN202010340131.XA CN202010340131A CN111477733A CN 111477733 A CN111477733 A CN 111477733A CN 202010340131 A CN202010340131 A CN 202010340131A CN 111477733 A CN111477733 A CN 111477733A
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- substrate
- dam
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 64
- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 184
- 238000004519 manufacturing process Methods 0.000 claims abstract description 19
- 238000005520 cutting process Methods 0.000 claims abstract description 15
- 239000000919 ceramic Substances 0.000 claims description 23
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 229920005989 resin Polymers 0.000 claims description 15
- 239000011347 resin Substances 0.000 claims description 15
- 239000011889 copper foil Substances 0.000 claims description 10
- 238000003466 welding Methods 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 239000004033 plastic Substances 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 239000011521 glass Substances 0.000 description 29
- 238000009713 electroplating Methods 0.000 description 6
- 238000004080 punching Methods 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000006698 induction Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 239000012779 reinforcing material Substances 0.000 description 2
- 238000004659 sterilization and disinfection Methods 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 238000004021 metal welding Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000000746 purification Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000001954 sterilising effect Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Dicing (AREA)
Abstract
The invention discloses a wafer packaging method, which comprises the following steps: manufacturing a plurality of independent circuits on the surface of a piece of packaging substrate, wherein the independent circuits are separated from each other at intervals, and fixedly mounting a wafer on the independent circuits on the upper surface of the packaging substrate; arranging dam holes corresponding to the independent circuits of the packaging substrate on the large piece of dam substrate; fixing a light-transmitting cover plate at the top of the box dam substrate, fixing the bottom surface of the box dam substrate on a packaging substrate, and positioning a chip fixedly mounted on the packaging substrate in a box dam hole of the box dam substrate; and cutting the packaging substrate and the dam substrate with the light-transmitting cover plate which are overlapped and fixed together to obtain a wafer packaging finished product. The wafer is fixedly mounted on the packaging substrate which is not fixed with the box dam, is not cut and is in a whole plate state, the light-transmitting cover plate is fixed on the box dam substrate which is not cut and is in a whole plate state, and the production efficiency of the wafer and the light-transmitting cover plate is high.
Description
[ technical field ]
The present invention relates to chip packaging, and more particularly to a chip packaging method.
[ background art ]
The ultraviolet light emitting diode (UV-L ED) has the advantages of energy conservation, environmental protection, long service life, small volume, controllable wavelength and the like, wherein the light emitting wavelength of the deep ultraviolet L ED is less than 300nm, and the deep ultraviolet light emitting diode (UV-L ED) can be applied to the fields of sterilization, disinfection, water purification, biochemical detection and the like.
The metal box dam on the three-dimensional ceramic substrate can be manufactured by a direct copper electroplating process, the height of the metal box dam is 400-800 mu m, multiple times of electroplating are needed, the process is complex, the cost is high, and the stress of the multiple times of electroplating enables the substrate to easily generate defects such as warping, tensile cracking and plate breaking. The single-piece manufactured and single-piece bonded box dam has the advantages of high assembly process difficulty, low production efficiency and low bonding precision of the box dam.
The invention with the application number of CN201610944502.9 discloses a method for preparing a dam ceramic substrate for ultraviolet L ED packaging, which comprises the following steps of (1) manufacturing a plurality of independent circuits on the surface of the ceramic substrate, wherein the independent circuits are separated from each other, forming a plurality of through holes on the dam substrate, the inner diameter of each through hole at the bottom end of each through hole is larger than the maximum width of the independent circuit, (2) gluing the bottom surface of the dam substrate to form a bonding layer, (3) clamping the bonding layer between the bottom surface of the dam substrate and the surface of the ceramic substrate, and (4) cutting the ceramic substrate and the dam substrate which are overlapped and fixed together after the bonding layer is solidified to obtain a finished product.
The ceramic substrate and the box dam substrate which are fixedly overlapped are cut to obtain the granular box dam ceramic substrate finished product for packaging the ultraviolet L ED, the production efficiency of the box dam ceramic substrate is high, the difficulty of subsequently fixing a wafer and mounting a light-transmitting cover plate is high, and the production efficiency of the ultraviolet L ED is low.
[ summary of the invention ]
The invention aims to provide a wafer packaging method with high production efficiency.
In order to solve the technical problem, the invention adopts the technical scheme that the wafer packaging method comprises the following steps:
101) manufacturing a plurality of independent circuits on the surface of a piece of packaging substrate, wherein the independent circuits are separated from each other at intervals, and fixedly mounting a wafer on the independent circuits on the upper surface of the packaging substrate;
102) arranging dam holes corresponding to the independent circuits of the packaging substrate on the large piece of dam substrate;
103) fixing a light-transmitting cover plate at the top of the box dam substrate, fixing the bottom surface of the box dam substrate on a packaging substrate, and positioning a chip fixedly mounted on the packaging substrate in a box dam hole of the box dam substrate;
104) and cutting the packaging substrate and the dam substrate with the light-transmitting cover plate which are overlapped and fixed together to obtain a wafer packaging finished product.
In the above-mentioned chip packaging method, in step 103), the transparent cover plate is fixed on the top of the dam substrate before the bottom surface of the dam substrate is fixed on the package substrate, or the transparent cover plate is fixed on the top of the dam substrate after the bottom surface of the dam substrate is fixed on the package substrate.
In the above-mentioned chip packaging method, in step 103), the dam substrate and the package substrate are fixed by bonding or welding, and the bottom surface of the transparent cover plate and the top of the dam substrate are fixed by bonding or welding.
In the above wafer packaging method, the sheet of transparent cover plate is fixed on the top surface of the sheet of dam substrate.
In the above wafer packaging method, the packaging substrate is a resin PCB or a ceramic PCB, the dam substrate is a resin copper clad laminate, a ceramic plate, a metal plate or a high temperature resistant plastic plate, and when the dam substrate is the copper clad laminate, in step 102), the cutting street cut in step 104) is etched on the copper foil of the copper clad laminate by coating a photosensitive material, exposing, developing and etching.
In the above wafer packaging method, the dam hole is a stepped hole with a large top and a small bottom, and the light-transmitting cover plate is embedded into the large hole of the dam stepped hole; the box dam substrate comprises an upper plate and a lower plate, small holes of the stepped holes are formed in the lower plate, and large holes of the stepped holes are formed in the upper plate; the upper plate and the lower plate are bonded.
The wafer packaging method of claim 6, wherein the upper plate and the lower plate are respectively single-sided copper-clad plates, the copper foil of the upper plate faces upwards, and the copper foil of the lower plate faces downwards.
In the above-described wafer packaging method, in step 102), the inner wall of the dam hole is plated with a metal layer.
The wafer is fixedly mounted on the packaging substrate which is not fixed with the box dam, is not cut and is in a whole plate state, the light-transmitting cover plate is fixed on the box dam substrate which is not cut and is in a whole plate state, and the production efficiency of the wafer and the light-transmitting cover plate is high.
[ description of the drawings ]
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
Fig. 1 is a front cross-sectional view of a package substrate according to an embodiment of the invention.
Fig. 2 is a top view of a package substrate according to an embodiment of the invention.
Fig. 3 is a partially enlarged cross-sectional view of a package substrate according to an embodiment of the invention.
Fig. 4 is a front sectional view of the dam substrate of embodiment 1 of the present invention.
Fig. 5 is a top view of the dam substrate of embodiment 1 of the present invention.
Fig. 6 is a partially enlarged sectional view in a front view of an embodiment 1 of the dam substrate of the present invention.
Fig. 7 is a schematic view of the inner wall of the hole of the dam, the top surface and the bottom surface of the substrate of the dam being plated with the metal layer according to embodiment 1 of the present invention.
FIG. 8 is a schematic view of a top surface of a box dam substrate secured to a sheet of glass cover plate in accordance with example 1 of the present invention.
Fig. 9 is a partially enlarged view of the combination of the substrate of the box dam and the glass cover plate according to example 1 of the present invention.
Fig. 10 is a schematic view illustrating a tin layer disposed on the bottom surface of the dam substrate in embodiment 1 of the present invention.
Fig. 11 is a cross-sectional view of a dam substrate and a glass cover plate assembly mounted on a top surface of a package substrate in accordance with example 1 of the present invention.
FIG. 12 is a schematic diagram of a plate-formed UV-L ED module cut into granular UV-L ED modules according to example 1 of the present invention.
Fig. 13 is a cross-sectional view of a finished package of a UV-L ED module according to embodiment 1 of the present invention.
Fig. 14 is a sectional view in a front view of an upper plate of embodiment 2 of the dam base plate of the present invention.
Fig. 15 is a plan view of the upper plate of embodiment 2 of the dam substrate of the present invention.
Fig. 16 is a front sectional view of the lower plate of embodiment 2 of the dam substrate of the present invention.
Fig. 17 is a plan view of the lower plate of embodiment 2 of the dam substrate of the present invention.
Fig. 18 is a front sectional view of the dam substrate of embodiment 2 of the present invention.
Fig. 19 is a partially enlarged sectional view in a front view of embodiment 2 of the dam substrate of the present invention.
Fig. 20 is a schematic view showing the inner walls of the dam hole, the top surface and the bottom surface of the dam substrate plated with the metal layers in example 2 of the present invention.
FIG. 21 is a schematic view of a top-mounted granular glass cover plate of a dam substrate in accordance with example 2 of the present invention.
FIG. 22 is an enlarged view of a portion of a glass cover plate of a dam substrate in accordance with example 2 of the present invention.
Fig. 23 is a schematic view illustrating a tin layer disposed on the bottom surface of the dam substrate in embodiment 2 of the present invention.
Fig. 24 is a cross-sectional view of a dam substrate and a glass cover plate assembly mounted on the top surface of a package substrate in accordance with example 2 of the present invention.
Fig. 25 is a cross-sectional view of a finished package of a UV-L ED module according to embodiment 2 of the present invention.
FIG. 26 is a process flow diagram of the wafer packaging method of the present invention.
[ detailed description of the invention ]
As shown in fig. 26, the chip packaging method of the present invention includes the following steps: manufacturing a plurality of independent circuits on the surface of a piece of packaging substrate, wherein the independent circuits are separated from each other at intervals, and fixedly mounting a wafer on the independent circuits on the upper surface of the packaging substrate; arranging dam holes corresponding to the independent circuits of the packaging substrate on the large piece of dam substrate; fixing a light-transmitting cover plate at the top of the box dam substrate, fixing the bottom surface of the box dam substrate on a packaging substrate, and positioning a chip fixedly mounted on the packaging substrate in a box dam hole of the box dam substrate; and cutting the packaging substrate and the dam substrate with the light-transmitting cover plate which are overlapped and fixed together to obtain a wafer packaging finished product.
The wafer packaging method of the embodiment of the invention is described by taking UV-L ED packaging as an example, and comprises the following steps:
firstly, a package substrate 10 is manufactured, as shown in fig. 1 to 3, the package substrate 10 may be a resin PCB or a ceramic PCB, in this embodiment, the package substrate 10 is a ceramic PCB, a core board of the package substrate 10 is a ceramic board 11, 4 positioning holes 13 are firstly formed at an edge of the rectangular package substrate 10, then a plurality of independent circuits 12 are manufactured on the package substrate 10 in a matrix form, the independent circuits 12 are separated from each other at intervals, and then a die bonding operation or a die bonding wire bonding operation is performed on the UV-L ED wafer 01 on each independent circuit 12 on the upper surface of the package substrate 10, so as to complete the manufacture of the package substrate 10.
Manufacturing the box dam substrate 20: the dam holes 23 corresponding to the independent circuits 12 of the packaging substrate 10 are formed in the large piece of dam substrate 20, and the dam substrate 20 can be a resin copper-clad plate, a ceramic plate, a metal plate or a high-temperature-resistant plastic plate.
The resin copper clad laminate comprises a copper foil 21 and a resin-containing substrate 22, wherein the resin-containing substrate 22 can be a substrate which is impregnated with resin on the basis of a reinforcing material (such as glass fiber cloth), can also be a substrate of pure resin, or can be a substrate which contains a small amount of reinforcing material in resin. The resin of the substrate 22 may be BT resin, modified epoxy resin or PI resin to endure the processing temperature of 260 ℃ to 320 ℃.
1) Production example 1 of the dam substrate 20 as shown in fig. 4 to 7:
101) the dam substrate 20 of the embodiment 1 adopts a double-sided copper-clad plate, the dam holes 23 are straight holes, and 4 positioning holes 24 are firstly formed in the edge of the rectangular dam substrate 20;
102) punching a box dam hole 23 by a die punching mode, and then carrying out metallization treatment on the inner wall of the box dam hole 23;
103) electroplating the box dam substrate 20 to coat a layer of metal 25 on the inner wall of the box dam hole 23 and the top surface and the bottom surface of the box dam substrate 20;
104) the top and bottom surfaces of the dam substrate 20 are coated with a photosensitive material, exposed, developed, and etched, and longitudinal and transverse dicing streets (not shown) that cut the dam substrate 20 are etched in advance.
2) Production example 2 of dam substrate 20 as shown in fig. 14 to 20:
201) the box dam hole 23 of the embodiment 2 is a stepped hole with a large upper part and a small lower part, the box dam substrate 20 adopts two single-sided copper-clad plates, the two single-sided copper-clad plates are overlapped up and down, the copper foil 21 of the upper plate 20A faces upwards, the copper foil 21 of the lower plate 20B faces downwards, and the edges of the two single-sided copper-clad plates which are rectangular in sheet are respectively provided with 4 positioning holes 24A and 24B; after the two single-sided copper-clad plates are overlapped up and down, the positioning hole 24A and the positioning hole 24B are combined into a positioning hole 24.
202) Punching a large hole 23A of a stepped hole in the upper plate 20A and a small hole 23B of the stepped hole in the lower plate by a die punching mode; the upper plate 20A and the lower plate 20B are bonded together by positioning through the positioning holes 24;
203) carrying out metallization treatment on the inner wall of the dam hole 23;
204) electroplating the box dam substrate 20 to coat a layer of metal 25 on the inner wall of the box dam hole 23 and the top surface and the bottom surface of the box dam substrate 20;
205) photosensitive material is coated on the top surface and the bottom surface of the box dam substrate 20, and the longitudinal and transverse cutting channels cut by the box dam substrate 20 are etched in advance through exposure, development and etching, so that the metal on the top surface and the bottom surface of the box dam substrate 20 is prevented from damaging a cutter during cutting.
3) Production of dam substrate 20 example 3:
301) the dam substrate 20 of the embodiment 3 adopts a ceramic plate, a connected ceramic dam is sintered by a sintering method, and positioning holes are set at the edges of the plate;
302) coating a layer of metal on the top surface, the bottom surface and the inner wall of the dam hole of the ceramic dam in a vacuum sputtering mode;
303) electroplating the box dam substrate to plate a layer of metal on the inner wall of the box dam hole and the top surface and the bottom surface of the box dam substrate;
304) the top and bottom surfaces of the dam substrate 20 are coated with photosensitive materials, exposed, developed and etched, and the longitudinal and transverse cutting lines cut by the dam substrate 20 are etched in advance.
4) Production of dam substrate 20 example 4:
the dam substrate 20 of example 4 is made of a high temperature resistant plastic plate, and a continuous dam is manufactured by injection molding, and the remaining steps are the same as the manufacturing steps of the ceramic dam substrate 20 of example 3.
Thirdly, fixing a glass cover plate 30 on the top of the box dam substrate 20:
1) example 1 for fixing the glass cover plate 30 to the dam substrate 20:
101) corresponding to the box dam substrate 20 of the embodiment 1, a piece of glass cover plate 30 can be fixed, and 4 positioning holes corresponding to the positioning holes of the box dam substrate are respectively arranged on the edge of the piece of rectangular glass cover plate 30 and used as positioning references when the two are fixed;
102) the contact part of the bottom surface of the glass cover plate 30 and the top surface of the base plate of the box dam is printed with a layer of weldable metal 32 by silk screen or coated with a layer of silver;
103) welding a gold-tin soldering lug 33 on the weldable metal welding layer on the bottom surface of the glass cover plate 30, placing the glass cover plate 30 pressed with the soldering lug 33 on the upper surface of the box dam substrate 20, and welding the glass cover plate 30 and the box dam substrate 20 by utilizing induction heating; steps 102) and 103) may be replaced by the bonding of step 104);
104) during bonding, after a bonding film is pasted on the top surface of the box dam substrate 20, the glass cover plate 30 is pressed on the bonding film, and bonding of the glass cover plate 30 and the box dam substrate 20 is achieved.
2) Example 2 in which the glass cover plate 30 is fixed to the dam substrate 20:
201) corresponding to the dam substrate 20 of example 2, only the granular glass cover plate 30 can be embedded in the large holes of the dam holes 23;
202) firstly, screen printing or coating weldable metal annular layers 32 which are arranged in a matrix mode on the bottom surface of a sheet of rectangular glass cover plate 30, wherein the shape of the weldable metal annular layers is the same as that of the dam steps; pressing a gold-tin soldering lug 33 on the surface of the solderable metal annular layer;
203) cutting the rectangular glass cover plate 30 into the granular glass cover plate 30, and embedding the granular glass cover plate 30 into the large holes of the box dam holes 23 of the box dam substrate 20 by using a manipulator;
204) the welding of the granular glass cover plate 30 and the box dam base plate 20 is realized by utilizing induction heating, and the welding of the glass cover plate 30 and the box dam base plate 20 is realized;
205) steps 202) to 204) may be replaced by an adhesion step to achieve adhesion of the glass cover plate 30 to the dam substrate 20.
Fourthly, fixing the dam substrate 20 finished in the second step or the third step on the packaging substrate 10:
step four can be performed after step three, or before step three; step four, after the step three, the suction disc of the manipulator is facilitated to suck the box dam substrate 20 with the packaged box dam hole, so that the operation is more convenient.
The box dam substrate 20 is positioned by the positioning hole 24 and the positioning hole 13 of the packaging substrate 10 and then is bonded or welded and fixed, if a welding mode is adopted, when the independent circuit 12 is manufactured on the box dam substrate 20, a circle of copper foil 14 corresponding to the bottom surface of the box dam is reserved on the periphery of the independent circuit 12.
If the bonding method is adopted, a film for replacing the tin layer 26 is pressed on the bottom surface of the dam substrate 20 when the dam substrate 20 is manufactured.
The dam substrate 20 is fixed on the package substrate 10 to obtain a whole UV-L ED module.
And fifthly, cutting the packaging substrate 10 and the box dam substrate 20 with the glass cover plate 30 which are overlapped and fixed together according to the criss-cross cutting channels 02 shown in the figure 12, and obtaining the packaging finished product of the UV-L ED module as shown in the figure 12.
Fig. 13 shows a finished UV-L ED module package of example 1, and fig. 25 shows a finished UV-L ED module package of example 2.
The method has the advantages that the whole UV-L ED module is cut into single pieces, the glass cover plate 30, the box dam substrate 20 and the ceramic substrate can be cut by different cutters, so that the efficiency is high, the quality is good, the glass cover plate 30, the box dam substrate 20 and the ceramic substrate are cut simultaneously, the cutting efficiency is not high due to the fact that the materials of the glass cover plate 30, the box dam substrate 20 and the ceramic substrate are different, and a single UV-L ED product is obtained after cutting.
The whole packaging method of the UV-L ED in the embodiment of the invention is processed in a whole-chip mode, the production efficiency is high, and the labor cost is low.
Claims (8)
1. A chip packaging method is characterized by comprising the following steps:
101) manufacturing a plurality of independent circuits on the surface of a piece of packaging substrate, wherein the independent circuits are separated from each other at intervals, and fixedly mounting a wafer on the independent circuits on the upper surface of the packaging substrate;
102) arranging dam holes corresponding to the independent circuits of the packaging substrate on the large piece of dam substrate;
103) fixing a light-transmitting cover plate at the top of the box dam substrate, fixing the bottom surface of the box dam substrate on a packaging substrate, and positioning a chip fixedly mounted on the packaging substrate in a box dam hole of the box dam substrate;
104) and cutting the packaging substrate and the dam substrate with the light-transmitting cover plate which are overlapped and fixed together to obtain a wafer packaging finished product.
2. The chip packaging method as claimed in claim 1, wherein in the step 103), the transparent cover plate is fixed on top of the dam substrate before the bottom surface of the dam substrate is fixed on the package substrate, or the transparent cover plate is fixed on top of the dam substrate after the bottom surface of the dam substrate is fixed on the package substrate.
3. The chip packaging method as claimed in claim 1, wherein in step 103), the dam substrate and the package substrate are fixed by bonding or welding, and the bottom surface of the transparent cover plate and the top of the dam substrate are fixed by bonding or welding.
4. The method of claim 1, wherein the light transmissive cover plate is attached to the top surface of the dam substrate.
5. The wafer packaging method of claim 1, wherein the packaging substrate is a resin PCB or a ceramic PCB, the dam substrate is a resin copper clad laminate, a ceramic plate, a metal plate or a high temperature resistant plastic plate, and when the dam substrate is the copper clad laminate, in step 102), the cutting streets cut in step 104) are etched on the copper foil of the copper clad laminate by coating a photosensitive material, exposing, developing and etching.
6. The wafer packaging method according to claim 1, wherein the dam hole is a stepped hole with a large top and a small bottom, and the light-transmitting cover plate is embedded into the large hole of the dam stepped hole; the box dam substrate comprises an upper plate and a lower plate, small holes of the stepped holes are formed in the lower plate, and large holes of the stepped holes are formed in the upper plate; the upper plate and the lower plate are bonded.
7. The wafer packaging method of claim 6, wherein the upper plate and the lower plate are respectively single-sided copper-clad plates, the copper foil of the upper plate faces upwards, and the copper foil of the lower plate faces downwards.
8. The method of claim 1, wherein in step 102), the inner wall of the dam hole is plated with a metal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202010340131.XA CN111477733A (en) | 2020-04-26 | 2020-04-26 | Chip packaging method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010340131.XA CN111477733A (en) | 2020-04-26 | 2020-04-26 | Chip packaging method |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112967937A (en) * | 2021-02-09 | 2021-06-15 | 池州昀冢电子科技有限公司 | Packaging structure and preparation method thereof |
| CN112967933A (en) * | 2021-02-09 | 2021-06-15 | 池州昀冢电子科技有限公司 | Packaging structure and manufacturing method thereof |
| CN113013041A (en) * | 2021-02-09 | 2021-06-22 | 池州昀冢电子科技有限公司 | Packaging structure and preparation method thereof |
| CN113054076A (en) * | 2021-03-10 | 2021-06-29 | 池州昀冢电子科技有限公司 | Glass circuit board and preparation method thereof, and packaging structure and preparation method thereof |
| CN113066731A (en) * | 2021-03-01 | 2021-07-02 | 池州昀冢电子科技有限公司 | Packaging structure and preparation method thereof |
| CN113451481A (en) * | 2021-06-28 | 2021-09-28 | 江西新正耀光学研究院有限公司 | Manufacturing method of deep ultraviolet light emitting element |
| CN113893361A (en) * | 2021-09-29 | 2022-01-07 | 宁波安芯美半导体有限公司 | UVC LED lamp and packaging method thereof |
| CN114242870A (en) * | 2021-12-22 | 2022-03-25 | 鸿利智汇集团股份有限公司 | Wafer support, wafer support plate and wafer packaging method |
| CN114577506A (en) * | 2020-11-30 | 2022-06-03 | 核工业理化工程研究院 | Sampling device and sampling method for vacuum coating sample |
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