CN1107336C - 多层电路基片及其制造方法 - Google Patents

多层电路基片及其制造方法 Download PDF

Info

Publication number
CN1107336C
CN1107336C CN96113395A CN96113395A CN1107336C CN 1107336 C CN1107336 C CN 1107336C CN 96113395 A CN96113395 A CN 96113395A CN 96113395 A CN96113395 A CN 96113395A CN 1107336 C CN1107336 C CN 1107336C
Authority
CN
China
Prior art keywords
layer
substrate
circuit substrate
layer circuit
metallic film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN96113395A
Other languages
English (en)
Other versions
CN1155158A (zh
Inventor
柳在喆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hanwha Aerospace Co Ltd
Original Assignee
Samsung Aerospace Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Aerospace Industries Ltd filed Critical Samsung Aerospace Industries Ltd
Publication of CN1155158A publication Critical patent/CN1155158A/zh
Application granted granted Critical
Publication of CN1107336C publication Critical patent/CN1107336C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1258—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by using a substrate provided with a shape pattern, e.g. grooves, banks, resist pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H05K1/095—Dispersed materials, e.g. conductive pastes or inks for polymer thick films, i.e. having a permanent organic polymeric binder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0568—Resist used for applying paste, ink or powder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/386—Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/44—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits
    • H05K3/445—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits having insulated holes or insulated via connections through the metal core
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/465—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer having channels for the next circuit layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Inks, Pencil-Leads, Or Crayons (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

多层电路基片及其制造方法：用光敏绝缘层涂敷基片的上表面，曝光和显影光敏绝缘层以形成具有预定图形和图形间隔的光敏绝缘层，在图形间隔处印导电浆料形成导电层，重复前面步骤，形成由光敏绝缘层和导电层构成的多层，用粘性绝缘层涂敷多层的最上层，通过热压在粘性绝缘层上形成金属薄膜，蚀刻以形成预定图形，并形成导电材料注入其中的通孔，穿通基片、导电层、光敏绝缘层和金属薄膜，将导电层与构图的金属薄膜电连接。

Description

多层电路基片及其制造方法
技术领域
本发明涉及多层电路基片及其制造方法，特别涉及多层电路基片及用导电浆料和金属薄膜制造多层电路基片的方法。
背景技术
单层和多层电路基片已广泛地用作半导体封装的电路基片。特别是，能集成许多器件的多层电路基片已被积极地研究以适应即使在小基片上也达到高集成度的趋势。
传统的多层电路基片是通过每层的淀积和蚀刻来制造的，所以制造工艺十分复杂。除此之外，基片材料限于能蚀刻的材料。
发明内容
为解决上述问题，本申请提出的方法中的电路基片是通过用在基片上印导电浆料(conductive ink)来代替蚀刻工艺而制造的。
但是，在通过印刷制造多层电路基片的方法中，涂敷在基片上的导电浆料层由于其粘性易于形成圆形。另外，导电浆料层由于浆料的大小不同导致它的不平性从而不能保证其平整度。
由此，为解决这些缺点，本发明的目的是提供多层电路基片及其制造方法，其使用导电浆料和金属薄膜，以利于引线焊接。
为达到上述目的，这里提供一种制造多层电路基片的方法，该方法包括下列步骤：用光敏绝缘层涂敷基片的上表面；曝光和显影光敏绝缘层，以形成有预定图形和图形间隔的光敏绝缘层；在图形间隔处印刷导电浆料形成导电层；重复前面步骤，形成每一层由有图形间隔的预定图形的光敏绝缘层和形成在图形间隔处的导电层构成的多层；用粘性绝缘层涂敷多层的最上层；通过热压工艺在粘性绝缘层上形成金属薄膜，并蚀刻金属薄膜形成金属薄膜的预定图形；以及形成其中注有导电材料的通孔，穿通基片、导电层、光敏绝缘层和金属薄膜，将导电层与金属薄膜图形电连接。
为达到上述目的，这里提供一种多层电路基片，该多层电路基片包含：基片；形成在所说基片上的多层，由有预定图形间隔的光敏绝缘层和由导电浆料在所说图形间隔处形成的导电层构成每一层；通过粘性绝缘材料粘着在所说多层的最上层的有预定图形的金属薄膜；有导电材料注入的孔，其穿通所说基片、多层、和金属薄膜以将所说导电层和金属薄膜电连接。
本发明的上述目的和优点通过以下参照附图对优选实施例的详细说明会变得更明显。附图中：
附图说明
图1A和1B是表示根据本发明的实施例制造多层电路基片的方法的简图；
图2是用图1的制造方法制造的多层电路基片的剖面图；
图3是表示根据本发明的另一实施例的制造多层电路基片的简图。
具体实施方式
下面参照图1A和1B详细说明本发明的多层电路基片的制造方法。
首先，制备由金属、陶瓷、或绝缘材料构成的基片10(步骤100)。这里基片10由具有极好热稳定性和热辐射性的导电金属(如合金42或铜合金)制成，在基片10上形成填充孔11(步骤110)，在基片10和填充孔11的表面涂敷绝缘材料12(步骤120)，在所涂敷的绝缘材料12的表面涂敷光敏绝缘层20(步骤130)。另一方面，当基片10由陶瓷或绝缘材料构成时，在基片10的上表面涂敷光敏绝缘层20，而不进行步骤120。
随后，在光敏绝缘层20的表面把具有预定图形的光掩模对准后，基片10用光26曝光并显影(步骤140)。然后，用显影液去除光敏绝缘层20的曝光部分，形成预定图形的光敏绝缘层20A(步骤150)。
然后，在步骤150的光敏绝缘层20A的图形间隔22处印导电浆料，并加热几分钟使其硬化，由此形成导电层30(步骤160)。
如上所述，通过步骤100到步骤160制备单层电路基片。这样，可以通过重复这些步骤来形成多层电路基片(步骤170)。即，在单层电路基片上涂敷光敏绝缘层(未示出)以使单层电路基片电绝缘。当在光敏绝缘层(未示出)的表面把具有预定图形的光掩模对准后，通过曝光和显影工艺形成具有预定图形和图形间隔(未示出)的光敏绝缘层20B。然后，在图形间隔处印导电浆料，形成导电层30A，由此制造两层电路基片。这样，如果重复这些工艺，可以在光敏绝缘层20A、20B、20C和20D的图形间隔处通过印刷导电浆料形成多个导电层30、30A、30B和30C。
其次，在具有光敏绝缘层20D的基片上涂敷粘性绝缘层40之后，热压如铜薄膜等金属薄膜50，使其粘结在粘性绝缘层40上(步骤180)。此时，作为广泛用于电路基片的金属薄膜50具有很好的平整度，这样元器件即芯片可容易地安装在其上。
然后，通过蚀刻金属薄膜50形成预定图形的金属薄膜50A，然后在金属薄膜50A的间隔处填充绝缘材料60(步骤190)。
此后，形成通孔70以穿通基片10、填充孔11(参见步骤110)、导电层30、30A、30B和30C、光敏绝缘层20A、20B、20C和20D、粘性绝缘层40和金属薄膜50A(步骤200)。然后，把导电浆料70A注入通孔70，由此完成多层电路基片。这样，有导电浆料注入其中的孔70与形成在每层绝缘材料的图形间隔与金属薄膜50A之间的导电层30、30A、30B和30C电连接。此时，如果基片10由金属构成，则形成比通孔70大100到200μm的填充孔11。这样，可保证绝缘材料12足够厚，以便在形成通孔70时可以实现电绝缘。
图2是表示用图1A或1B的方法制造的多层电路基片的实施例的剖面图。与图1A和1B中相同的数字表示与图1A和1B中相同的部件。
这种多层电路基片包括：基片10；具有形成在基片10上的间隔22(图1A)的多层光敏绝缘层20A、20B、20C和20D；形成在图形间隔22处的导电浆料层30、30A、30B和30C，通过粘性绝缘层40粘着在绝缘层20D和导电浆料层30C上的预定图形的金属薄膜50A，和将导电层30、30A、30B和30C与金属薄膜50A电连接的通孔70。
不考虑导电性，可用各种材料如金属、陶瓷或绝缘材料作基片10。最好是用金属材料(如合金42，铜合金等)作基片10。这些金属材料具有极好的热稳定性和散热性。可以选择各种金属材料。如果导电金属用作基片10，那么在基片10上形成填充孔11，并在基片10的表面和填充孔中涂敷绝缘材料12。
每一预定图形的光敏绝缘层20A、20B、20C和20D都是具有200℃或以上玻璃相变温度(Tg)的光致抗蚀层。
导电浆料由细金属粉末(如Cu-Pb-Sn，Ag-Pb-Sn等)、如酸酐系列化合物(如六氟异丙基-苯二酸氢酸酐，英文为hexafluoroisopropyl-diphthalicanhydride等)等聚合反应材料、和溶剂(如甲基乙基酮，英文为pmethyl ethylketone，丙酮等)组成。可用由Toranaga Co.(美国)研制的Ormet 2005R作导电浆料。
金属薄膜50A，在其上安装如芯片等部件的部分有极好的平整度。
当基片10由金属构成时，将绝缘材料12填充进形成在基片10上的通孔70中。
下面参照图3说明本发明制造多层电路基片方法的另一实施例，与前面图中相同的标号表示与前面图中相同的部件。
根据该实施例，至少在一个光敏绝缘层90上不形成如图1A中其中印有导电浆料的图形间隔22(参见步骤290)。即，光敏绝缘层90是分界绝缘层。其他步骤与图1A和1B的步骤相同。
即使光敏绝缘层90作为分界绝缘层，通孔70也可以电连接导电浆料30、30A、和30B与图形化的金属薄膜50A。
如上所述，根据本发明用导电浆料制备的多层电路基片结构简单，由此可增加生产率。另外，由于基片并不限于金属基片，材料选择很广泛，这样便可降低生产成本。特别是，由于能确保在最上部分的金属薄膜的平整度，所以很容易进行引线焊接。

Claims (18)

1、一种制造多层电路基片的方法，包括下列步骤：
用光敏绝缘层涂敷一基片的上表面；
曝光和显影所说光敏绝缘层，以形成具有预定图形和图形间隔的光敏绝缘层；
其特征在于，该方法还包括如下步骤：
通过在所说图形间隔处印刷导电浆料形成导电层；
通过重复所说前面的步骤，形成每一层皆由有图形间隔的预定图形的光敏绝缘层和形成在所说图形间隔处的导电层构成的多层；
用粘性绝缘层涂敷多层的最上层，通过热压在所说粘性绝缘层上形成一金属薄膜，蚀刻所说金属薄膜以形成金属薄膜的预定图形；和
形成导电材料注入其中的通孔，穿通所说基片、导电层、光敏绝缘层和金属薄膜、将所说导电层与所说图形化的金属薄膜电连接。
2、如权利要求1所述的多层电路基片的制造方法，其中，导电浆料含细金属粉末、聚合反应材料和溶剂。
3、如权利要求2所述的多层电路基片的制造方法，其中，细金属粉末选自由Cu-Pb-Sn和Ag-Pb-Sn组成的组中，聚合反应材料是一种酸肝系列化合物，溶剂选自由甲基乙基酮和丙酮组成的组中。
4、如权利要求3所述的多层电路基片的制造方法，其中聚合反应材料是六氟异丙基-苯二酸氢酸酐(hexafluoroisopropyl-diphthalic anhydride)。
5、如权利要求1所述的多层电路基片的制造方法，其中，至少一个所说光敏绝缘层是分界绝缘层，该分界绝缘层中没有用来在其中印刷导电浆料的图形间隔。
6、如权利要求1所述的多层电路基片的制造方法，其中，该基片由陶瓷构成。
7、如权利要求1所述的多层电路基片的制造方法，其中，该基片由选自铜合金和合金42组成的组中的金属形成。
8、如权利要求7所述的多层电路基片的制造方法，还包含一步骤，即在第一光敏绝缘层涂敷步骤之前，在欲形成所说基片的所说通孔的部分上形成填充孔，并用绝缘材料涂敷基片表面和所说填充孔内部。
9、如权利要求8所述的多层电路基片的制造方法，其中，所说填充孔的直径大于所说通孔的直径，以使注入所说通孔的所说导电材料通过填入所说填充孔中的绝缘材料与所说基片电绝缘。
10、一种多层电路基片包含：
基片；
其特征在于，该多层电路基片还包括形成在所说基片上且每一层皆由有预定图形间隔的光敏绝缘层和用导电桨料形成在所说图形间隔处的导电层构成的多层；
通过粘性绝缘材料粘着在所说多层的最上层上的预定图形的金属薄膜；
导电材料注入其中的孔，穿通所说基片、多层和金属薄膜，电连接所说导电层和金属薄膜。
11、如权利要求10所述的多层电路基片，其中，导电浆料含细金属粉末、聚合反应材料和溶剂。
12、如权利要求11所述的多层电路基片，其屯细金属粉末选自由Cu-Pb-Sn和Ag-Pb-Sn组成的组中，聚合反应材料是一种酸酐系列化合物，溶剂选自由甲基乙基酮和丙酮组成的组中。
13、如权利要求12所述的多层电路基片，其中，聚合反应材料是六氟异丙基-苯二酸氢酸酐(hexafluoroisopropyl-diphthalic anhydride)。
14，如权利要求10所述的多层电路基片，其中，所说基片由陶瓷构成。
15、如权利要求10所述的多层电路基片，其中，所说基片由选自铜合金和合金42组成的组中的金属形成。
16、如权利要求15所述的多层电路基片，其中，在欲形成所说基片的所说通孔的部分上形成填充孔，并用绝缘材料涂敷所说基片表面和所说填充孔内部。
17、如权利要求16所述的多层电路基片，其中，所说填充孔的直径大于所说通孔的直径，以使注入所说通孔的所说导电材料通过填入所说填充孔中的绝缘材料来与所说基片电绝缘。
18、如权利要求10所述的多层电路基片，其中，所说金属薄膜由铜制成。
CN96113395A 1995-09-12 1996-09-12 多层电路基片及其制造方法 Expired - Fee Related CN1107336C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR29688/95 1995-09-12
KR1019950029688A KR0155877B1 (ko) 1995-09-12 1995-09-12 다층 회로기판 및 그 제조방법
KR29688/1995 1995-09-12

Publications (2)

Publication Number Publication Date
CN1155158A CN1155158A (zh) 1997-07-23
CN1107336C true CN1107336C (zh) 2003-04-30

Family

ID=19426526

Family Applications (1)

Application Number Title Priority Date Filing Date
CN96113395A Expired - Fee Related CN1107336C (zh) 1995-09-12 1996-09-12 多层电路基片及其制造方法

Country Status (6)

Country Link
US (1) US5747222A (zh)
JP (1) JP3765627B2 (zh)
KR (1) KR0155877B1 (zh)
CN (1) CN1107336C (zh)
DE (1) DE19636735B4 (zh)
TW (1) TW304323B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110739267A (zh) * 2019-09-12 2020-01-31 西北工业大学 基于印刷与光刻结合方式的高精度柔性微电路加工方法

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2836616B2 (ja) * 1997-03-05 1998-12-14 日本電気株式会社 導体配線パターンの形成方法
US6021050A (en) * 1998-12-02 2000-02-01 Bourns, Inc. Printed circuit boards with integrated passive components and method for making same
US6518516B2 (en) 2000-04-25 2003-02-11 International Business Machines Corporation Multilayered laminate
US6407341B1 (en) 2000-04-25 2002-06-18 International Business Machines Corporation Conductive substructures of a multilayered laminate
CN100350820C (zh) * 2000-06-30 2007-11-21 E·I·内穆尔杜邦公司 厚膜电路形成图形的方法
KR100511085B1 (ko) * 2001-08-10 2005-08-30 (주)알티즌하이텍 인쇄 형판 제작 시스템 및 그 제조방법
US20060159838A1 (en) * 2005-01-14 2006-07-20 Cabot Corporation Controlling ink migration during the formation of printable electronic features
US20030108664A1 (en) * 2001-10-05 2003-06-12 Kodas Toivo T. Methods and compositions for the formation of recessed electrical features on a substrate
KR100483609B1 (ko) * 2002-07-27 2005-04-15 삼성전기주식회사 노이즈 차폐형 적층 기판의 제조방법
GB0324561D0 (en) * 2003-10-22 2003-11-26 Koninkl Philips Electronics Nv A method of producing a conductive layer on a substrate
CN1744293B (zh) * 2004-09-03 2011-06-08 台湾薄膜电晶体液晶显示器产业协会 薄膜晶体管的制作方法
US8167393B2 (en) 2005-01-14 2012-05-01 Cabot Corporation Printable electronic features on non-uniform substrate and processes for making same
CA2594806C (en) * 2005-01-14 2015-06-02 Cabot Corporation Security features, their use, and processes for making them
US8334464B2 (en) 2005-01-14 2012-12-18 Cabot Corporation Optimized multi-layer printing of electronics and displays
US7824466B2 (en) 2005-01-14 2010-11-02 Cabot Corporation Production of metal nanoparticles
US7749299B2 (en) * 2005-01-14 2010-07-06 Cabot Corporation Production of metal nanoparticles
US8383014B2 (en) 2010-06-15 2013-02-26 Cabot Corporation Metal nanoparticle compositions
US20060163744A1 (en) * 2005-01-14 2006-07-27 Cabot Corporation Printable electrical conductors
WO2006076615A1 (en) * 2005-01-14 2006-07-20 Cabot Corporation Ink-jet printing of compositionally no-uniform features
US7662663B2 (en) * 2007-03-28 2010-02-16 Eastman Kodak Company OLED patterning method
US7674712B2 (en) * 2007-10-22 2010-03-09 Cok Ronald S Patterning method for light-emitting devices
JP2011529416A (ja) * 2008-06-10 2011-12-08 ジョンソン コントロールズ テクノロジー カンパニー 装飾インモールドフィルム上の容量性スイッチセンサ
US8716867B2 (en) * 2010-05-12 2014-05-06 Taiwan Semiconductor Manufacturing Company, Ltd. Forming interconnect structures using pre-ink-printed sheets
CN102097300B (zh) * 2010-11-10 2013-03-20 日月光半导体制造股份有限公司 半导体基板的制造方法及半导体结构的制造方法
CN102625603A (zh) * 2011-01-13 2012-08-01 讯忆科技股份有限公司 多层电路板的线路层增层方法及其结构
KR102251775B1 (ko) 2014-07-18 2021-05-12 삼성전자주식회사 전극 구조체 및 이를 사용하는 접촉 감지 센서
WO2020236885A2 (en) 2019-05-21 2020-11-26 General Electric Company Energy conversion apparatus and control system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4665468A (en) * 1984-07-10 1987-05-12 Nec Corporation Module having a ceramic multi-layer substrate and a multi-layer circuit thereupon, and process for manufacturing the same
EP0624904A2 (en) * 1993-04-21 1994-11-17 Nec Corporation A multi-layer wiring board and a manufacturing method thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4221925A (en) * 1978-09-18 1980-09-09 Western Electric Company, Incorporated Printed circuit board
US5376403A (en) * 1990-02-09 1994-12-27 Capote; Miguel A. Electrically conductive compositions and methods for the preparation and use thereof
IE940943A1 (en) * 1993-12-09 1995-06-14 Methode Electronics Inc Printed plastic circuits and contacts and method for making¹same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4665468A (en) * 1984-07-10 1987-05-12 Nec Corporation Module having a ceramic multi-layer substrate and a multi-layer circuit thereupon, and process for manufacturing the same
EP0624904A2 (en) * 1993-04-21 1994-11-17 Nec Corporation A multi-layer wiring board and a manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110739267A (zh) * 2019-09-12 2020-01-31 西北工业大学 基于印刷与光刻结合方式的高精度柔性微电路加工方法

Also Published As

Publication number Publication date
JPH09130051A (ja) 1997-05-16
DE19636735B4 (de) 2005-12-29
JP3765627B2 (ja) 2006-04-12
TW304323B (zh) 1997-05-01
KR970019795A (ko) 1997-04-30
US5747222A (en) 1998-05-05
DE19636735A1 (de) 1997-03-13
KR0155877B1 (ko) 1998-12-15
CN1155158A (zh) 1997-07-23

Similar Documents

Publication Publication Date Title
CN1107336C (zh) 多层电路基片及其制造方法
US8277668B2 (en) Methods of preparing printed circuit boards and packaging substrates of integrated circuit
JP3382096B2 (ja) バイアを有する多層回路基板の製造方法、チップ・キャリアおよびチップ・キャリアの製造方法
CA2160501C (en) Laminar stackable circuit board structure and manufacture
US6098282A (en) Laminar stackable circuit board structure with capacitor
US5198693A (en) Aperture formation in aluminum circuit card for enhanced thermal dissipation
US5985760A (en) Method for manufacturing a high density electronic circuit assembly
TW548816B (en) Formation method of conductor pillar
WO1991014015A1 (en) Method and materials for forming multi-layer circuits by an additive process
CN1524293A (zh) 具有集成器件的微电子衬底
JPS63258055A (ja) 電子回路装置およびその製造方法
TWI333128B (en) A method of fabricating an electronic device using a conductive photolithographic film, and an electronic device having a patterned conductive photolithographic film
KR100275235B1 (ko) 프린트 회로기판 및 프린트 회로기판의 제조방법
EP0147566B1 (en) Method of forming contacts for flexible module carriers
US6651324B1 (en) Process for manufacture of printed circuit boards with thick copper power circuitry and thin copper signal circuitry on the same layer
US6427323B2 (en) Method for producing conductor interconnect with dendrites
EP0713358A2 (en) Circuit board
CN1201367A (zh) 多层印刷电路板及其制造方法
JPH0710029B2 (ja) 積層回路基板の製造方法
WO2023019684A1 (zh) 一种封装机构及其制备方法
CN202231960U (zh) 电子元件埋入式电路板
JP2003264361A (ja) 回路基板の製造方法
KR20020022477A (ko) 물리적 기상 증착법을 이용한 빌드업 다층 인쇄회로판제조방법
US6156414A (en) Carrier film and process for producing the same
US6074728A (en) Multi-layered circuit substrate

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20030430

Termination date: 20120912