CN110335871B - 阵列基板的制备方法、阵列基板及显示面板 - Google Patents

阵列基板的制备方法、阵列基板及显示面板 Download PDF

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CN110335871B
CN110335871B CN201910504742.0A CN201910504742A CN110335871B CN 110335871 B CN110335871 B CN 110335871B CN 201910504742 A CN201910504742 A CN 201910504742A CN 110335871 B CN110335871 B CN 110335871B
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mask
array substrate
metal layer
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卓恩宗
杨凤云
夏玉明
许哲豪
刘振
张合静
雍万飞
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HKC Co Ltd
Chuzhou HKC Optoelectronics Technology Co Ltd
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Abstract

本发明公开了一种阵列基板的制备方法,包括以下步骤:在衬底基板上依次形成栅极、栅极绝缘层、有源层、欧姆接触层和金属层后,在所述金属层上形成光刻掩膜,所述光刻掩膜在掩膜板的半曝光区的厚度范围为
Figure DDA0002090597430000011
蚀刻所述光刻掩膜覆盖范围外的所述金属层、所述欧姆接触层和所述有源层;利用灰化反应物对所述光刻掩膜进行预设时间的灰化处理,其中,所述灰化反应物包括氧气,所述预设时间的取值范围为70秒‑100秒;以及基于灰化处理后的光刻掩膜,依次蚀刻所述金属层、所述欧姆接触层和所述有源层,形成阵列基板的沟道区。本发明还公开了一种阵列基板以及显示面板。本发明提高了阵列基板的稳定性。

Description

阵列基板的制备方法、阵列基板及显示面板
技术领域
本发明涉及薄膜晶体管领域,尤其涉及一种阵列基板的制备方法、阵列基板以及显示面板。
背景技术
液晶显示器现已成为市场主流,其工作原理是液晶在电流的驱动下会发生偏转,使光线容易通过,从而显示图像。薄膜晶体管阵列基板包括金属层和非晶硅层(有源层),非晶硅(A-Si)是目前半导体行业应用最广泛的半导体层材料,A-Si材料与金属接触时因为有较大的势能差,难以形成欧姆接触,实际应用中,为了获得金属和半导体之间的欧姆接触,一般会在金属层和非晶硅层之间形成欧姆接触层,降低金属和半导体的接触阻抗,提高电流效率。
目前在四道光刻制程(4-Mask)制备薄膜晶体管阵列基板的过程中,在蚀刻沟道区(掩膜板半曝光区)对应的金属层时,容易形成氧化物残留,从而导致在后续蚀刻欧姆接触层时,进一步形成欧姆接触层残留,以致形成的阵列基板不稳定,会出现局部短路等问题,影响显示性能。
发明内容
本发明的主要目的在于提供一种阵列基板的制备方法、阵列基板以及显示面板,提高了阵列基板的稳定性。
为实现上述目的,本发明提供一种阵列基板的制备方法,所述阵列基板的制备方法包括以下步骤:
在衬底基板上依次形成栅极、栅极绝缘层、有源层、欧姆接触层和金属层后,在所述金属层上形成光刻掩膜,所述光刻掩膜在掩膜板的半曝光区的厚度范围为
Figure BDA0002090597410000011
蚀刻所述光刻掩膜覆盖范围外的所述金属层、所述欧姆接触层和所述有源层;
利用灰化反应物对所述光刻掩膜进行预设时间的灰化处理,其中,所述灰化反应物包括氧气,所述预设时间的取值范围为70秒-100秒;以及
基于灰化处理后的光刻掩膜,依次蚀刻所述金属层、所述欧姆接触层和所述有源层,形成阵列基板的沟道区。
可选地,所述灰化反应物包括六氟化硫,所述利用灰化反应物对所述光刻掩膜进行预设时间的灰化处理的步骤包括:
基于第一预设量的六氟化硫和第二预设量的氧气对所述光刻掩膜进行为时80秒-100秒的灰化处理,所述第一预设量和所述第二预设量之间的比值范围为1:1至3:1。
可选地,所述第一预设量的取值范围为10000sccm-24000sccm,所述第二预设量的取值范围为8000sccm-10000sccm。
可选地,所述基于第一预设量的六氟化硫和第二预设量的氧气对所述光刻掩膜进行为时80秒-100秒的灰化处理的步骤之前,还包括:
在所述金属层上形成的所述光刻掩膜在所述掩膜板的半曝光区的厚度范围为
Figure BDA0002090597410000021
可选地,所述利用灰化反应物对所述光刻掩膜进行预设时间的灰化处理的步骤包括:
利用氧气对所述光刻掩膜进行为时70秒-80秒的灰化处理。
可选地,所述利用氧气对所述光刻掩膜进行为时70秒-80秒的灰化处理的步骤之前,还包括:
在所述金属层上形成的所述光刻掩膜在所述掩膜板的半曝光区的厚度范围为
Figure BDA0002090597410000022
时。
可选地,所述利用灰化反应物对所述光刻掩膜进行预设时间的灰化处理的步骤之前,还包括:
在所述金属层上形成的所述光刻掩膜在所述掩膜板的半曝光区的厚度范围为
Figure BDA0002090597410000023
所述利用灰化反应物对所述光刻掩膜进行预设时间的灰化处理的步骤包括:
利用氧气对所述光刻掩膜进行为时84秒-95秒的灰化处理。
可选地,所述在所述金属层上形成光刻掩膜的步骤包括:
在所述金属层上涂抹光刻胶后,基于所述掩膜板和预设剂量的光剂量能量对所述光刻胶进行曝光,在所述金属层上形成所述光刻掩膜,并控制所述光刻掩膜在所述掩膜板的半曝光区内的均匀度达到预设均匀度,其中,所述预设均匀度的取值范围为20%-40%,所述预设剂量的取值范围为35MJ-45MJ。
为实现上述目的,本发明还提供一种阵列基板,所述阵列基板由上述阵列基板的制备方法形成。
为实现上述目的,本发明还提供一种显示面板,所述显示面板基于上述阵列基板制备形成。
本发明提供的阵列基板的制备方法、阵列基板以及显示面板,在衬底基板上依次形成栅极、栅极绝缘层、有源层、欧姆接触层和金属层后,在所述金属层上形成光刻掩膜,所述光刻掩膜在掩膜板的半曝光区的厚度范围为
Figure BDA0002090597410000031
蚀刻所述光刻掩膜覆盖范围外的所述金属层、所述欧姆接触层和所述有源层;利用灰化反应物对所述光刻掩膜进行预设时间的灰化处理,其中,所述灰化反应物包括氧气,所述预设时间的取值范围为70秒-100秒;以及基于灰化处理后的光刻掩膜,依次蚀刻所述金属层、所述欧姆接触层和所述有源层,形成阵列基板的沟道区。这样,解决了在蚀刻沟道区对应范围内的金属层时因容易形成氧化物残留,而导致在后续蚀刻欧姆接触层时进一步形成欧姆接触层残留的问题,从而得到制备良好的欧姆接触层,避免最终形成的阵列基板会出现局部短路,影响显示性能的现象,从而提高了阵列基板的稳定性。
附图说明
图1为本发明阵列基板的制备方法的一实施例的流程示意图;
图2为本发明阵列基板的制备方法的另一实施例的流程示意图;
图3为本发明阵列基板的制备方法的又一实施例的流程示意图;
图4为本发明阵列基板的制备方法的一实施例的氧化物残留示例图;
图5为本发明阵列基板的制备方法的一实施例的欧姆接触层残留示例图;
图6为本发明阵列基板的制备方法的一实施例的曝光后形成光刻掩膜示例图;
图7为本发明阵列基板的制备方法的一实施例的灰化处理后的光刻掩膜示例图。
附图标号说明:
标号 名称 标号 名称
10 光刻掩膜 40 有源层
20 金属层 50 半曝光区域
21 金属层残留 60 曝光区域
30 欧姆接触层 70 掩膜板
31 欧姆接触层残留 80 非曝光区域
本发明目的的实现、功能特点及优点将结合实施例,参照附图做进一步说明。
具体实施方式
应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。
本发明提供一种阵列基板的制备方法,解决了在蚀刻沟道区对应范围内的金属层时因容易形成氧化物残留,而导致在后续蚀刻欧姆接触层时进一步形成欧姆接触层残留的问题,从而得到制备良好的欧姆接触层,避免最终形成的阵列基板会出现局部短路,影响显示性能的现象,从而提高了阵列基板的稳定性。
参照图1,在一实施例中,所述阵列基板的制备方法包括:
步骤S10、在衬底基板上依次形成栅极、栅极绝缘层、有源层、欧姆接触层和金属层后,在所述金属层上形成光刻掩膜,所述光刻掩膜在掩膜板的半曝光区的厚度范围为
Figure BDA0002090597410000041
本实施例中,薄膜晶体管阵列基板中设置于有源层(非晶硅层,A-Si)和金属层之间的欧姆接触层(掺杂型非晶硅层,N+A-Si)可以是N型欧姆接触层,也可以是P型欧姆接触层。
参照图4,在阵列基板通过4-Mask制程(四步光刻制程)制备的过程中,在依次蚀刻掩膜板半曝光区域50内的金属层20、欧姆接触层30和有源层40形成阵列基板的沟道区时,蚀刻金属层时,金属层中的金属材质容易和氧气反应,在欧姆接触层30表面形成氧化物残留21(此时处于沟道区对应范围内的欧姆接触层未开始蚀刻)。参照图5,以至于在后续继续蚀刻欧姆接触层30和有源层40时,在氧化物残留对应的覆盖位置形成欧姆接触层残留31,进一步影响欧姆接触层残留31对应的覆盖位置所覆盖的有源层的蚀刻,使得最终形成的有源层在沟道区对应的沟道横截宽度对应的有源层表面不平整,以致形成的阵列基板不稳定,会出现局部短路等问题,影响显示性能。
在制造薄膜晶体管阵列基板时,预先形成衬底基板和栅极,并采用化学气相法在衬底基板上沉积形成覆盖栅极的栅极绝缘层,然后在栅极绝缘层上依次沉积形成有源层、欧姆接触层和金属层。
需要说明的是,所述金属层的材质可以是锰、钼、钛、铝和铜中的一种或多种的堆栈组合;所述有源层可以是A-Si材质;所述栅极绝缘层的材质可以是氧化硅和/或氮化硅;所述栅极可以是钼、钛、铝和铜中的一种或多种的堆栈组合;所述衬底基板可以是玻璃基板。
参照图6,在欧姆接触层30上沉积形成金属层20后,在金属层上涂抹光刻胶。通过掩膜板70对所述光刻胶进行曝光,具体地,对与掩膜板曝光区域60对应的光刻胶进行完全曝光,对与掩膜板半曝光区域50对应的光刻胶进行部分曝光,而掩膜板非曝光区域80对应的光刻胶则基本不受光照影响。然后基于O2对曝光后的光刻胶进行干蚀刻,以蚀刻掉已受光照影响的光刻胶,参照图5,形成设于金属层20上的光刻掩膜10,其中,在蚀刻与掩膜板半曝光区域50对应的光刻胶后,形成光刻掩膜10在掩膜板半曝光区域50的厚度Δhd为预设厚度,所述预设厚度的厚度范围为
Figure BDA0002090597410000051
(0.2um-0.6um),所述预设厚度可选为
Figure BDA0002090597410000052
或者
Figure BDA0002090597410000053
Figure BDA0002090597410000054
需要说明的是,所述掩膜板可以是单缝隙掩膜板,也可以是双缝隙掩膜板。
需要说明的是,最终形成的阵列基板的沟道区与掩膜板半曝光区域对应。
可选地,在设置光刻曝光参数时,可以通过调配掩膜板半曝光区域的光剂量能量(Photo Dose Energy)的热值,实现对光刻掩膜形成后的在掩膜板半曝光区域的厚度值的调控。在所述金属层上涂抹光刻胶后,基于掩膜板和预设剂量的光剂量能量对所述光刻胶进行曝光,以在所述金属层上形成所述光刻掩膜,所述预设剂量的取值范围为35MJ-45MJ。比如,设置41.5MJ的光剂量能量,可对应调控出光刻掩膜在沟道区的预设厚度为
Figure BDA0002090597410000061
进一步地,所述光刻胶层的保留厚度大于或等于
Figure BDA0002090597410000062
时,所述光刻胶层的保留厚度每减少
Figure BDA0002090597410000063
时,所需剂量能量为1.5MJ。进一步地,所述光刻胶层的保留厚度小于
Figure BDA0002090597410000064
且大于或等于
Figure BDA0002090597410000065
时,所述光刻胶层的保留厚度每减少
Figure BDA0002090597410000066
时,所需剂量能量为2.5MJ。
同时,控制所述光刻掩膜在沟道区范围内的均匀度达到预设均匀度,所述预设均匀度的取值范围为20%-40%。可选地,参见图6,在形成在沟道区的厚度范围为
Figure BDA0002090597410000067
的光刻掩膜时,以及形成与掩膜板非曝光区域80对应的光刻掩膜的岛状结构部分的层间厚度Δhd1的范围为
Figure BDA0002090597410000068
可选地,所述层间厚度Δhd1为
Figure BDA0002090597410000069
这样,通过形成光刻掩膜在掩膜板半曝光区域的厚度范围为
Figure BDA00020905974100000610
以及形成光刻掩膜在掩膜板半曝光区域外的岛状结构部分的层间厚度范围为
Figure BDA00020905974100000611
可以实现改善光刻掩膜的均匀度,以使光刻掩膜的均匀度达到20%-40%。
需要说的是,在涂抹光刻胶时,所形成的光刻胶层可能均匀性较差,以及在蚀刻曝光后的光刻胶层以形成光刻掩膜时,因蚀刻速率等因素的影响,也会造成光刻掩膜的膜厚的不均匀性。这样,通过形成在掩膜板半曝光区域的厚度达到预设厚度的光刻掩膜,避免在后续4-Mask制程中,因光刻掩膜的膜厚的不均匀性而对金属层和非晶硅层蚀刻时造成的影响,同时又能避免在后续对光刻掩膜进行灰化处理时,因光刻掩膜在掩膜板半曝光区域的厚度值过大而造成的灰化时间过长,而导致的掩膜板半曝光区域外的光刻掩膜损耗过大。
步骤S20、蚀刻所述光刻掩膜覆盖范围外的所述金属层、所述欧姆接触层和所述有源层。
在金属层上形成光刻掩膜后,基于所述光刻掩膜,依次蚀刻所述光刻掩膜覆盖范围外的金属层、欧姆接触层和有源层。具体地,基于所述光刻掩膜,通过湿蚀刻,蚀刻光刻掩膜覆盖范围外的金属层,然后对因金属层蚀刻后裸露出来的欧姆接触层和有源层依次进行干蚀刻。
具体地,可以是基于混合化合物对所述金属层进行湿蚀刻,所述混合化合物包括H3PO4磷酸、CH3COOH乙酸和HNO3硝酸;在对欧姆接触层和有源层进行第一次干蚀刻时,可以是基于第一混合气体对非晶硅层进行干蚀刻,所述第一混合气体包括SF6六氟化硫气体和Cl2氯气。
步骤S30、利用灰化反应物对所述光刻掩膜进行预设时间的灰化处理,其中,所述灰化反应物包括氧气,所述预设时间的取值范围为70秒-100秒。
可选地,灰化反应物包括氧气O2,氧气的反应剂量的取值范围为8000sccm-10000sccm,所述预设时间的取值范围为70秒-100秒。可选地,采用氧气进行灰化反应时,反应时间(预设时间)的取值范围可为84秒-95秒。即采用8000sccm-10000sccm的氧气对光刻掩膜进行为时84秒-95秒的灰化处理,参见图7,以去除沟道区对应范围内的光刻掩膜(对应为掩膜板半曝光区域50),使得在掩膜板半曝光区域50的金属层20的表面露出。
可选地,在采用8000sccm-10000sccm的氧气对光刻掩膜进行为时84秒-95秒的灰化处理时,预先形成的光刻掩膜在掩膜板的半曝光区的厚度范围为
Figure BDA0002090597410000071
这样,由于形成光刻掩膜在沟道区的层间厚度达到一定厚度,可以使得在灰化光刻掩膜时能消耗更多的氧气,从而使得整个阵列基板的制备环境中的氧气减少,便难以在金属层表面形成氧化物残留。
步骤S40、基于灰化处理后的光刻掩膜,依次蚀刻所述金属层、所述欧姆接触层和所述有源层,形成阵列基板的沟道区。
基于灰化处理后的光刻掩膜,对金属层、欧姆接触层和有源层进行第二次蚀刻。具体地,对所述光刻掩膜覆盖范围外的金属层进行湿蚀刻,其中,蚀刻沟道区对应范围内的金属层(即原掩膜板半曝光区对应的部分,此时掩膜板已移除),以形成金属层的源电极和漏电级,以及裸露出与沟道区范围对应的欧姆接触层。然后基于灰化处理后的光刻掩膜,以及湿蚀刻后的金属层,对所述金属层覆盖范围外的欧姆接触层和有源层进行干蚀刻,最终形成阵列基板的沟道区(掩膜板半曝光区对应的区域)。
具体地,可以是基于混合化合物对所述金属层进行湿蚀刻,所述混合化合物包括H3PO4、CH3COOH和HNO3;在对所述有源层进行第二次干蚀刻时,可以是基于第二混合气体对非晶硅层进行干蚀刻,所述第二混合气体包括SF6气体、Cl2和He气体。
在使所述金属层覆盖沟道区外的所述有源层后,剥离剩余的光刻掩膜,即可形成包括衬底基板、栅极、栅极绝缘层,以及图形化的欧姆接触层、有源层和金属层的薄膜晶体管阵列基板。
需要说明的是,在后续形成阵列基板的过程中,在所述阵列基板的栅极绝缘层上,形成覆盖包括欧姆接触层、有源层和所述金属层的图形的钝化层,以及形成通过钝化层的钝化过孔的像素层,即可形成薄膜晶体管阵列基板。
进一步地,基于形成的薄膜晶体管阵列基板,可用于制备显示面板。
在一实施例中,在衬底基板上依次形成栅极、栅极绝缘层、有源层、欧姆接触层和金属层后,在所述金属层上形成光刻掩膜,所述光刻掩膜在掩膜板的半曝光区的厚度范围为
Figure BDA0002090597410000081
蚀刻所述光刻掩膜覆盖范围外的所述金属层、所述欧姆接触层和所述有源层;利用灰化反应物对所述光刻掩膜进行预设时间的灰化处理,其中,所述灰化反应物包括氧气,所述预设时间的取值范围为70秒-100秒;以及基于灰化处理后的光刻掩膜,依次蚀刻所述金属层、所述欧姆接触层和所述有源层,形成阵列基板的沟道区。这样,解决了在蚀刻沟道区的金属层时因容易形成氧化物残留,而导致在后续蚀刻欧姆接触层时进一步形成欧姆接触层残留的问题,从而得到制备良好的欧姆接触层,避免最终形成的阵列基板会出现局部短路,影响显示性能的现象,从而提高了阵列基板的稳定性。
在另一实施例中,如图2所示,在上述图1所示的实施例基础上,所述阵列基板的制备方法还包括:
步骤S11、在衬底基板上依次形成栅极、栅极绝缘层、有源层、欧姆接触层和金属层后,在所述金属层上形成光刻掩膜,所述光刻掩膜在掩膜板的半曝光区的厚度范围为
Figure BDA0002090597410000082
步骤S31、基于第一预设量的六氟化硫和第二预设量的氧气对所述光刻掩膜进行为时80秒-100秒的灰化处理,所述第一预设量和所述第二预设量之间的比值范围为1:1至3:1。
本实施例中,形成在沟道区对应范围内的厚度范围为
Figure BDA0002090597410000083
的光刻掩膜,并基于该光刻掩膜蚀刻所述光刻掩膜覆盖范围外的所述金属层、所述欧姆接触层和所述有源层,然后,基于第一预设量的六氟化硫SF6和第二预设量的氧气O2对所述光刻掩膜进行为时80秒-100秒的灰化处理(预设时间取值为80秒-100秒),其中,所述第一预设量和所述第二预设量之间的比值范围为1:1至3:1(即SF6:O2=1至SF6:O2=3之间)。
可选地,所述第一预设量的取值范围为10000sccm-24000sccm,所述第二预设量的取值范围为8000sccm-10000sccm。即采用8000sccm-10000sccm的氧气和10000sccm-24000sccm的六氟化硫SF6对光刻掩膜进行为时80秒-100秒的灰化处理,以去除沟道区对应范围内的光刻掩膜,使得在沟道区对应范围内的金属层的表面露出。
这样,在灰化的过程中,六氟化硫SF6可以与多余的氧气进行反应,可以使得在灰化光刻掩膜时能消耗更多的氧气,从而使得整个阵列基板的制备环境中的氧气减少,便难以在金属层表面形成氧化物残留。
在又一实施例中,如图3所示,在上述图1至图2的实施例基础上,所述阵列基板的制备方法还包括:
步骤S12、在衬底基板上依次形成栅极、栅极绝缘层、有源层、欧姆接触层和金属层后,在所述金属层上形成光刻掩膜,所述光刻掩膜在掩膜板的半曝光区的厚度范围为
Figure BDA0002090597410000091
步骤S32、利用氧气对所述光刻掩膜进行为时70秒-80秒的灰化处理。
本实施例中,形成在沟道区对应范围内的厚度范围为
Figure BDA0002090597410000092
的光刻掩膜,并基于该光刻掩膜蚀刻所述光刻掩膜覆盖范围外的所述金属层、所述欧姆接触层和所述有源层,然后,利用氧气对所述光刻掩膜进行为时70秒-80秒的灰化处理,以去除沟道区对应范围内的所述光刻掩膜,其中,氧气的反应剂量的取值范围为8000sccm-10000sccm。即采用8000sccm-10000sccm的氧气对光刻掩膜进行为时70秒-80秒的灰化处理,以去除沟道区对应范围内的光刻掩膜,使得在沟道区对应范围内的金属层的表面露出。
这样,通过减少灰化过程中氧气的反应时间至70秒-80秒,可以使得整个阵列基板的制备环境中的氧气减少,便难以在金属层表面形成氧化物残留。
此外,本发明还提出一种阵列基板,所述阵列基板由上述阵列基板的制备方法形成。
此外,本发明还提供一种显示面板,所述显示面板基于上述阵列基板制备形成。
上述本发明实施例序号仅仅为了描述,不代表实施例的优劣。
通过以上的实施方式的描述,本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现,当然也可以通过硬件,但很多情况下前者是更佳的实施方式。基于这样的理解,本发明的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来,该计算机软件产品存储在如上所述的一个存储介质(如ROM/RAM、磁碟、光盘)中,包括若干指令用以使得一台终端设备(可以是电视机,手机,计算机,服务器,空调器,或者网络设备等)执行本发明各个实施例所述的方法。
以上仅为本发明的可选实施例,并非因此限制本发明的专利范围,凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换,或直接或间接运用在其他相关的技术领域,均同理包括在本发明的专利保护范围内。

Claims (5)

1.一种阵列基板的制备方法,其特征在于,所述阵列基板的制备方法包括以下步骤:
在衬底基板上依次形成栅极、栅极绝缘层、有源层、欧姆接触层和金属层后,在所述金属层上形成光刻掩膜,所述光刻掩膜在掩膜板的半曝光区的厚度范围为
Figure FDA0003245852580000011
蚀刻所述光刻掩膜覆盖范围外的所述金属层、所述欧姆接触层和所述有源层;
利用灰化反应物对所述光刻掩膜进行预设时间的灰化处理,其中,所述灰化反应物包括氧气和六氟化硫,基于第一预设量的六氟化硫和第二预设量的氧气对所述光刻掩膜进行为时80秒-100秒的灰化处理,所述第一预设量和所述第二预设量之间的比值范围为1.25:1至3:1,其中,所述第一预设量和所述第二预设量均为气体流量;以及
基于灰化处理后的光刻掩膜,依次蚀刻所述金属层、所述欧姆接触层和所述有源层,形成阵列基板的沟道区。
2.如权利要求1所述的阵列基板的制备方法,其特征在于,所述第一预设量的取值范围为10000sccm-24000sccm,所述第二预设量的取值范围为8000sccm-10000sccm。
3.如权利要求1-2中任一项所述的阵列基板的制备方法,其特征在于,所述在所述金属层上形成光刻掩膜的步骤包括:
在所述金属层上涂抹光刻胶后,基于所述掩膜板和预设剂量的光剂量能量对所述光刻胶进行曝光,在所述金属层上形成所述光刻掩膜,并控制所述光刻掩膜在所述掩膜板的半曝光区内的均匀度达到预设均匀度,其中,所述预设均匀度的取值范围为20%-40%,所述预设剂量的取值范围为35MJ-45MJ。
4.一种阵列基板,其特征在于,所述阵列基板由权利要求1至3中任一项所述的阵列基板的制备方法形成。
5.一种显示面板,其特征在于,所述显示面板包括权利要求4中所述的阵列基板。
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CN110335871B (zh) * 2019-06-11 2021-11-30 惠科股份有限公司 阵列基板的制备方法、阵列基板及显示面板
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103489873A (zh) * 2013-09-18 2014-01-01 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN107481934A (zh) * 2016-12-27 2017-12-15 武汉华星光电技术有限公司 一种薄膜晶体管的制作方法
CN109786335A (zh) * 2018-12-25 2019-05-21 惠科股份有限公司 阵列基板结构的制备方法、阵列基板及显示面板

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0145900B1 (ko) * 1995-02-11 1998-09-15 김광호 박막 트랜지스터 액정디스플레이 소자 및 그 제조방법
KR20040022770A (ko) * 2002-09-07 2004-03-18 엘지.필립스 엘시디 주식회사 액정표시소자의 제조방법
TW589663B (en) * 2003-05-12 2004-06-01 Au Optronics Corp Flat panel display and manufacturing method thereof
KR101294694B1 (ko) * 2007-12-04 2013-08-08 엘지디스플레이 주식회사 액정표시장치용 어레이 기판의 제조방법
KR102010393B1 (ko) * 2013-04-26 2019-08-14 엘지디스플레이 주식회사 횡전계형 액정표시장치용 어레이 기판 및 그 제조 방법
CN103887165B (zh) * 2014-03-07 2016-09-07 京东方科技集团股份有限公司 一种膜层的干法刻蚀方法
KR102248837B1 (ko) * 2015-01-02 2021-05-06 삼성디스플레이 주식회사 박막 트랜지스터 표시판의 제조 방법
CN104779256B (zh) * 2015-04-09 2018-08-24 深圳市华星光电技术有限公司 阵列基板及其制备方法、液晶面板
CN105161454B (zh) * 2015-07-10 2018-09-28 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置
CN108417583B (zh) * 2018-03-09 2021-10-29 惠科股份有限公司 一种阵列基板的制造方法和阵列基板
CN108447821B (zh) * 2018-03-09 2021-08-31 惠科股份有限公司 一种阵列基板的制造方法和阵列基板
US10971530B2 (en) * 2018-04-20 2021-04-06 Wuhan China Star Optoelectronics Technology Co., Ltd. Manufacturing method for a TFT array substrate and TFT array substrate
CN110335871B (zh) * 2019-06-11 2021-11-30 惠科股份有限公司 阵列基板的制备方法、阵列基板及显示面板

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103489873A (zh) * 2013-09-18 2014-01-01 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN107481934A (zh) * 2016-12-27 2017-12-15 武汉华星光电技术有限公司 一种薄膜晶体管的制作方法
CN109786335A (zh) * 2018-12-25 2019-05-21 惠科股份有限公司 阵列基板结构的制备方法、阵列基板及显示面板

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