CN110289257B - Bidirectional enhanced gate-controlled silicon controlled electrostatic protection device and manufacturing method thereof - Google Patents
Bidirectional enhanced gate-controlled silicon controlled electrostatic protection device and manufacturing method thereof Download PDFInfo
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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Abstract
The invention discloses a bidirectional enhanced gate-controlled silicon controlled electrostatic protection device which comprises a substrate P-Sub, wherein an NBL (N-bridge) region is arranged on the substrate P-Sub, and a first DN-Well region, a first P-EPI (P-EPI) region, a second DN-Well region, a second P-EPI region and a third DN-Well region are arranged on the NBL region; a first P-Well region is arranged in the first P-EPI region, and a first polysilicon gate is arranged in the first P-Well region; and a second P-Well region is arranged in the second P-EPI region, and a second polysilicon gate is arranged in the second P-Well region. According to the invention, the first polysilicon gate and the second polysilicon gate form an enhanced gate control structure, the enhanced gate control structure is adopted, so that the on-resistance of a bidirectional silicon controlled rectifier device can be reduced, the gain of a positive feedback loop of the silicon controlled rectifier is improved, the failure current is effectively improved, and the phenomena of soft failure and surface breakdown can not occur too early.
Description
Technical Field
The invention relates to the field of electrostatic protection, in particular to a bidirectional enhanced gate-controlled silicon controlled electrostatic protection device and a manufacturing method thereof.
Background
With the continuous progress of electronic technology and the continuous development of scientific level, the development trend of integrated circuits still follows the law of moore's law, i.e., the size of the device enters the nanometer level, the integration level is higher, and the like. Electrostatic discharge (ESD) is a major cause of integrated circuit chip failure, and is widely seen and closely related to people's lives. Accordingly, more and more people engaged in IC design are beginning to focus on ESD protection. According to related data, the data show that under the large environment of the integrated circuit micro-electronics field, the electronic product failure caused by the ESD phenomenon reaches more than half, and the economic loss caused by the ESD phenomenon reaches billions, and the data fully illustrate the importance and the necessity of electrostatic discharge protection. A high performance ESD protection device can improve the reliability, service life, etc. of electronic products. In the environment of a high-voltage electrode terminal pair, factors such as large current, high voltage, strong electromagnetic interference and the like cause great obstruction to ESD design, and the design of an ESD protection device needs small occupied area and strong ESD resistance capability, which is the biggest problem to be overcome by ESD designers at present.
A traditional bidirectional Silicon Controlled Rectifier (Dual Direction Silicon Controlled Rectifier) device is applied to forward and reverse symmetrical ESD protection in a high-voltage environment. When the device is in an on state, the holding voltage of the controlled silicon is lower due to the positive feedback mechanisms of the two BJTs, so that the device can bear high enough ESD pulse current stress. As a commonly used ESD protection device, the thyristor structure is regarded as an ESD protection device with the best robustness per unit area, and various improved thyristor electrostatic protection devices are widely used in various fields. However, the trigger of the thyristor depends on the avalanche breakdown voltage of the reverse biased PN junction of the trigger surface, so the trigger voltage of the structure is very high, and the problem of device latch-up is easily caused due to the low holding voltage during operation, and when the traditional thyristor is applied to a high-voltage extreme environment, the ESD resistance of the device is slightly insufficient. These three drawbacks will result in the internal core circuitry of the protected chip not being effectively protected. Therefore, in ESD design, when the thyristor structure is designed, it should be tried to increase the holding voltage of the structure and decrease the trigger voltage of the structure, and it is also necessary to ensure that the structure has a higher failure level.
The cross-sectional view and equivalent circuit of the conventional triac device structure are shown in fig. 1. Because the bidirectional triode thyristor is of a symmetrical structure, the working principle of the bidirectional triode thyristor in the forward direction and the reverse direction is the same. When the bidirectional controllable silicon works in the forward direction, when the voltage difference between the anode and the cathode does not reach the trigger voltage of the device, the bidirectional controllable silicon device is in a high-resistance state at the moment, when the voltage difference between the anode and the cathode reaches the trigger voltage of the bidirectional controllable silicon device, reverse bias PN junctions of N-Well and P-Well (close to the cathode) are subjected to avalanche breakdown, and carriers multiplied by avalanche pass through parasitic resistance R of the N-WellnA voltage drop is generated, and when the voltage drop reaches the turn-on voltage of the base-emitter junction of the parasitic PNP triode structure, the PNP will turn on, resulting in a parasitic resistance R across the P-Well (near the cathode)P2The magnitude of the current is rapidly increased, and the voltage drop generated by the current is enough to turn on the parasitic NPN2And the triode and a parasitic SCR path are gradually formed to discharge ESD current. When the bidirectional controllable silicon works reversely, when the voltage difference between the anode and the cathode does not reach the trigger voltage of the device, the bidirectional controllable silicon device is in a high-resistance state at the moment, when the voltage difference between the anode and the cathode reaches the trigger voltage of the device, reverse bias PN junctions of the N-Well and the P-Well (close to the anode) are subjected to avalanche breakdown, and carriers multiplied by avalanche flow through a parasitic resistor R of the N-WellnA voltage drop is generated, and when the voltage drop reaches the turn-on voltage of the base-emitter junction of the parasitic PNP triode structure, the PNP will turn on, thereby causing the parasitic resistance R passing through the P-Well (close to the anode)P1The magnitude of the current is rapidly increased, and the voltage drop generated by the current is reducedWill turn on the parasitic NPN1And the triode and a parasitic SCR path are gradually formed to discharge ESD current. At this time, the bidirectional thyristor device generates a negative resistance phenomenon, namely, the current is continuously increased, the voltage is reduced, and after the voltage is returned to the maintaining voltage, the whole device works in a low-resistance area. When the current is finally increased to cause the thermal failure of the bidirectional controllable silicon device, secondary breakdown occurs, and the structure of the bidirectional controllable silicon device is completely failed at the moment.
Disclosure of Invention
In order to solve the technical problems, the invention provides a bidirectional enhanced gate-controlled silicon controlled electrostatic protection device with a simple structure and strong ESD resistance, and a manufacturing method thereof.
The technical scheme for solving the problems is as follows: a bidirectional enhanced gate-controlled silicon controlled electrostatic protection device comprises a substrate P-Sub, wherein an NBL (N-doped nitride layer) region is arranged on the substrate P-Sub, and a first DN-Well region, a first P-EPI region, a second DN-Well region, a second P-EPI region and a third DN-Well region are sequentially arranged on the NBL region from left to right;
the first P-Well region is arranged in the first P-EPI region, and a first field oxide isolation region, a first P + injection region, a second field oxide isolation region, a first N + injection region and a first polysilicon gate are sequentially arranged in the first P-Well region from left to right;
an N-Well region is arranged in the second DN-Well region, and a third field oxide isolation region, a second N + injection region, a fourth field oxide isolation region, a third N + injection region and a fifth field oxide isolation region are sequentially arranged in the N-Well region from left to right;
a second P-Well region is arranged in the second P-EPI region, and a second polysilicon gate, a fourth N + injection region, a sixth field oxide isolation region, a second P + injection region and a seventh field oxide isolation region are sequentially arranged in the second P-Well region from left to right;
the first P + injection region, the first N + injection region and the first polysilicon gate are connected together and led out to serve as a cathode of the device; and the second polysilicon gate, the fourth N + injection region and the second P + injection region are connected together and led out to serve as an anode of the device.
Above-mentioned two-way enhancement mode grid-controlled silicon controlled rectifier electrostatic protection device, the left side in first field oxygen isolation region is connected with the left side edge in first DN-Well district, the right side in first field oxygen isolation region with the left side in first P + injection region is connected, the right side in first P + injection region with the left side in second field oxygen isolation region is connected, the right side in second field oxygen isolation region with the left side in first N + injection region is connected, the right side in first N + injection region with the left side of first polysilicon gate is connected, the right side and the first P-Well district right side edge parallel and level of first polysilicon gate.
Above-mentioned two-way enhancement mode grid-controlled silicon controlled rectifier electrostatic protection device, the left side of third field oxygen isolation region with the right side of first polycrystalline silicon gate is connected, the right side of third field oxygen isolation region with the left side in second N + injection region is connected, the right side in second N + injection region with the left side in fourth field oxygen isolation region is connected, the right side in fourth field oxygen isolation region with the left side in third N + injection region is connected, the right side in third N + injection region with the left side in fifth field oxygen isolation region is connected, the right side in fifth field oxygen isolation region is connected with second P-Well district left side edge.
Above-mentioned two-way enhancement mode grid-controlled silicon controlled rectifier electrostatic protection device, the left side of second polycrystalline silicon gate with second P-Well district left side edge parallel and level, the right side of second polycrystalline silicon gate with the left side in fourth N + injection district is connected, the right side in fourth N + injection district with the left side in sixth field oxygen isolation region is connected, the right side in sixth field oxygen isolation region with the left side in second P + injection district is connected, the right side in second P + injection district with the left side in seventh field oxygen isolation region is connected, the right side in seventh field oxygen isolation region with the right side edge in third DN-Well district is connected.
According to the bidirectional enhanced gate-controlled silicon electrostatic protection device, the first polysilicon gate in the first P-Well region and the second polysilicon gate in the second P-Well region form an enhanced gate-controlled structure, the enhanced gate-controlled structure generates a vertical downward electric field force at the anode of the device and a vertical upward electric field force at the cathode of the device, and the direction of the electric field force is always consistent with the current conduction direction, so that the movement of current carriers in the device is promoted, and the failure current of the device structure is improved.
According to the bidirectional enhanced gate-controlled silicon controlled electrostatic protection device, under a high-voltage environment, when high-voltage forward ESD current pulse stress comes to the anode of the device and the cathode of the device is at the ground potential, the first N + injection region, the first P-Well region and the N-Well region form a longitudinal NPN2The triode structure comprises a transverse PNP triode structure I formed by the first P-Well region, the N-Well region and the second P + injection region, and a base electrode and a longitudinal NPN of the transverse PNP triode structure I2The collectors of the triode structure are connected through the parasitic resistance of the N-Well region, and the longitudinal NPN2The base electrode of the triode structure is connected with the collector electrode of the transverse PNP triode structure I through the parasitic resistor of the first P-Well area, namely the transverse PNP triode structure I and the longitudinal NPN triode structure2The triode structure forms a thyristor structure.
In the bidirectional enhanced gate-controlled silicon controlled electrostatic protection device, under a high-voltage environment, when high-voltage reverse ESD current pulse stress comes to the anode of the device and the cathode of the device is at ground potential, the fourth N + injection region, the second P-Well region and the N-Well region form a longitudinal NPN1The triode structure comprises a transverse PNP triode structure II formed by a second P-Well region, an N-Well region and a first P + injection region, and a base electrode and a longitudinal NPN of the transverse PNP triode structure II1The collectors of the triode structure are connected through the parasitic resistance of the N-Well region, and the longitudinal NPN1The base electrode of the triode structure is connected with the collector electrode of the transverse PNP triode structure II through the parasitic resistance of the second P-Well area, namely the transverse PNP triode structure II and the longitudinal NPN triode structure1The triode structure forms a thyristor structure.
A manufacturing method of a bidirectional enhanced gate-controlled silicon controlled electrostatic protection device comprises the following steps:
the method comprises the following steps: forming an NBL region on the substrate P-Sub;
step two; a first DN-Well area, a first P-EPI area, a second DN-Well area, a second P-EPI area and a third DN-Well area are formed on the NBL area from left to right in sequence;
step three: forming first to seventh field oxide isolation regions by photolithography;
step four: forming a first P-Well region in the first P-EPI region, a second P-Well region in the second P-EPI region, and an N-Well region in the second DN-Well region by photolithography;
step five: forming a first polysilicon gate in the first P-Well region, and forming a second polysilicon gate in the second P-Well region;
step six: forming a first P + injection region in the first P-Well region and a second P + injection region in the second P-Well region by photoetching;
step seven: and forming a first N + injection region in the first P-Well region, forming a second N + injection region and a third N + injection region in the second DN-Well region, and forming a fourth N + injection region in the second P-Well region by photoetching.
The invention has the beneficial effects that:
1. according to the invention, the first polysilicon gate and the second polysilicon gate form an enhanced gate control structure, the enhanced gate control structure is adopted to reduce the on-resistance of the bidirectional silicon controlled rectifier, the gain of a positive feedback loop of the silicon controlled rectifier is improved, and the failure current is effectively improved, so that the bidirectional silicon controlled rectifier can bear high-strength ESD current pulse stress, the phenomena of soft failure and surface breakdown cannot occur in advance, the leakage current of the bidirectional silicon controlled rectifier is always kept at a lower order of magnitude, and the surface ESD path generated by the electric field effect can be blocked through a field oxide isolation region.
2. The invention adopts the enhanced gate control structure to ensure that ESD current stress of the bidirectional silicon controlled device is released in the low-resistance buried layer, thereby effectively improving the maintaining voltage of the device structure, preventing the device from generating latch-up effect and ensuring the signal integrity of the core circuit in the chip.
3. The manufacturing method of the invention has simple process and convenient operation. The manufactured bidirectional enhanced gate-controlled silicon electrostatic protection device structure does not violate layout design rules, and does not use layers except a standard BCD process, so that the bidirectional enhanced gate-controlled silicon electrostatic protection device structure can be applied to ESD protection design in a high-voltage environment, a core chip is effectively protected, a latch-up effect is prevented, and the ESD resistance of the chip is improved.
Drawings
Fig. 1 is a schematic diagram of a cross-sectional view and a parasitic structure of a conventional triac structure.
Fig. 2 is a circuit diagram of a bidirectional enhancement type gate controlled silicon electrostatic protection device structure in the embodiment of the invention.
Fig. 3 is a schematic diagram of a three-dimensional parasitic structure of a bidirectional enhancement type gate-controlled silicon controlled electrostatic protection device structure in the embodiment of the invention.
Fig. 4 is a schematic diagram of an equivalent circuit, i.e., an ESD current discharge path, of the bidirectional enhancement type gate controlled silicon electrostatic protection device structure for forward ESD protection in the embodiment of the present invention.
Fig. 5 is an equivalent circuit of the bidirectional enhancement type gate controlled silicon electrostatic protection device structure for reverse ESD protection, i.e. an ESD current discharge path, in the embodiment of the present invention.
Fig. 6 is a top view of the structure of the bidirectional enhancement type gated thyristor electrostatic protection device in the embodiment of the invention.
Detailed Description
The invention is further described below with reference to the figures and examples.
As shown in fig. 1-6, a bidirectional enhancement type gate controlled silicon electrostatic protection device comprises a substrate P-Sub101, wherein an NBL region 102 is arranged on the substrate P-Sub101, and a first DN-Well region 1041, a first P-EPI region 1031, a second DN-Well region 1042, a second P-EPI region 1032 and a third DN-Well region 1043 are sequentially arranged on the NBL region 102 from left to right; P-Sub is the P-type substrate region, NBL is the N-type buried layer region, DN-Well is the deep N-Well region, and P-EPI is the P-type epitaxial layer region.
A first P-Well region 105 is arranged in the first P-EPI region 1031, and a first field oxide isolation region 201, a first P + implantation region 108, a second field oxide isolation region 202, a first N + implantation region 109 and a first polysilicon gate 208 are sequentially arranged in the first P-Well region 105 from left to right;
the second DN-Well region 1042 is provided with an N-Well region 106, and the N-Well region 106 is provided with a third field oxide isolation region 203, a second N + injection region 110, a fourth field oxide isolation region 204, a third N + injection region 111 and a fifth field oxide isolation region 205 from left to right in sequence;
a second P-Well region 107 is arranged in the second P-EPI region 1032, and a second polysilicon gate 209, a fourth N + implantation region 112, a sixth field oxide isolation region 206, a second P + implantation region 113, and a seventh field oxide isolation region 207 are sequentially arranged in the second P-Well region 107 from left to right;
the first P + injection region 108 is connected with a first metal layer 210 of a metal layer 1 through a contact hole, the first N + injection region 109 is connected with a second metal layer 211 of the metal layer 1 through a contact hole, the first polysilicon gate 208 is connected with a third metal layer 212 of the metal layer 1 through a contact hole, a seventh metal layer 301 of the metal layer 2 is provided with a metal through hole 302, and the first metal layer 210 of the metal layer 1, the second metal layer 211 and the third metal layer 212 are connected with the seventh metal layer 301 of the metal layer 2 through the metal through hole 302 and used as a cathode of a device.
The second polysilicon gate 209 is connected with a fourth metal layer 213 of the metal layer 1 through a contact hole, the fourth N + injection region 112 is connected with a fifth metal layer 214 of the metal layer 1 through a contact hole, the second P + injection region 113 is connected with a sixth metal layer 215 of the metal layer 1 through a contact hole, a metal through hole 304 is arranged on an eighth metal layer 303 of the metal layer 2, the metal layer 1 is connected with the fourth metal layer 213, the fifth metal layer 214 and the sixth metal layer 215 are connected with the eighth metal layer 303 of the metal layer 2 through the metal through hole 304 and serve as an anode of the device.
The left side of the first field oxide isolation region 201 is connected with the left side edge of a first DN-Well region 1041, the right side of the first field oxide isolation region 201 is connected with the left side of a first P + injection region 108, the right side of the first P + injection region 108 is connected with the left side of a second field oxide isolation region 202, the right side of the second field oxide isolation region 202 is connected with the left side of a first N + injection region 109, the right side of the first N + injection region 109 is connected with the left side of a first polysilicon gate 208, and the right side of the first polysilicon gate 208 is flush with the right side edge of a first P-Well region 105.
The left side of the third field oxide isolation region 203 is connected to the right side of the first polysilicon gate 208, the right side of the third field oxide isolation region 203 is connected to the left side of the second N + implantation region 110, the right side of the second N + implantation region 110 is connected to the left side of the fourth field oxide isolation region 204, the right side of the fourth field oxide isolation region 204 is connected to the left side of the third N + implantation region 111, the right side of the third N + implantation region 111 is connected to the left side of the fifth field oxide isolation region 205, and the right side of the fifth field oxide isolation region 205 is connected to the left edge of the second P-Well region 107.
The left side of the second polysilicon gate 209 is flush with the left side edge of the second P-Well region 107, the right side of the second polysilicon gate 209 is connected with the left side of the fourth N + implantation region 112, the right side of the fourth N + implantation region 112 is connected with the left side of the sixth field oxide isolation region 206, the right side of the sixth field oxide isolation region 206 is connected with the left side of the second P + implantation region 113, the right side of the second P + implantation region 113 is connected with the left side of the seventh field oxide isolation region 207, and the right side of the seventh field oxide isolation region 207 is connected with the right side edge of the third DN-Well region.
The first polysilicon gate 208 in the first P-Well region 105 and the second polysilicon gate 209 in the second P-Well region 107 form an enhanced gate control structure, the enhanced gate control structure generates a vertical downward electric field force at the anode of the device and a vertical upward electric field force at the cathode of the device, and the direction of the electric field force is always consistent with the current conducting direction, so that the movement of carriers in the device is promoted, and the failure current of the device structure is improved. The NBL region 102 may increase a current path from an anode to a cathode of the device structure, improve a sustain voltage of the device, prevent the device from generating a latch-up effect, suppress a surface discharge path of the device structure, and effectively improve an ESD resistance of the device.
A manufacturing method of a bidirectional enhanced gate-controlled silicon controlled electrostatic protection device comprises the following steps:
the method comprises the following steps: forming an NBL region 102 on a substrate P-Sub 101;
step two; a first DN-Well region 1041, a first P-EPI region 1031, a second DN-Well region 1042, a second P-EPI region 1032 and a third DN-Well region 1043 are sequentially formed on the NBL region 102 from left to right.
And then forming a silicon dioxide film by thermal oxidation to relieve stress damage caused by silicon nitride formed in subsequent process steps. A layer of silicon nitride is deposited by means of a chemical vapor deposition (LPCVD) technique as a stop layer for CMP in a subsequent process step.
And uniformly coating photoresist on the wafer, and exposing and developing the photoresist, wherein the step is used for defining the shallow trench isolation. And then etching the silicon nitride, the silicon dioxide and the isolation shallow groove, removing the photoresist layer, depositing a layer of silicon dioxide by using chemical vapor deposition (LPCVD), then polishing by using chemical machinery until the silicon nitride thin film layer is reached, and removing the silicon nitride thin film layer by using hot phosphoric acid wet etching.
Step three: by photolithography, the first to seventh field oxide isolation regions 207 are formed. The method specifically comprises the following steps:
using a field oxide isolation (LOCOS) isolation technique, growing a silicon dioxide thin film layer as a buffer layer by using a thermal oxidation method, then depositing silicon nitride by using a chemical vapor deposition (LPCVD) technique, coating a photoresist on a wafer, and defining a first field oxide isolation region 201, a second field oxide isolation region 202, a third field oxide isolation region 203, a fourth field oxide isolation region 204, a fifth field oxide isolation region 205, a sixth field oxide isolation region 206, and a seventh field oxide isolation region 207 by using a photolithography technique. Then the reactive ions will etch away the silicon nitride on the first field oxide isolation region 201, the second field oxide isolation region 202, the third field oxide isolation region 203, the fourth field oxide isolation region 204, the fifth field oxide isolation region 205, the sixth field oxide isolation region 206, and the seventh field oxide isolation region 207, and then field implantation is performed to prevent the field from being turned on.
Step four: by photolithography, a first P-Well region 105 is formed in the first P-EPI region 1031, a second P-Well region 107 is formed in the second P-EPI region 1032, and an N-Well region is formed in the second DN-Well region 1042. The method specifically comprises the following steps:
photoresist is coated on the wafer for defining the first P-Well region 105 and the second P-Well region 107, then high-energy boron ions are implanted to form a local P-type region, and the photoresist is removed. And coating photoresist on the wafer for defining the N-Well area, then implanting high-energy phosphorus ions to form a local N-type area, and removing the photoresist layer.
And annealing the first P-Well region 105, the second P-Well region 107 and the N-Well region, repairing crystal damage of the silicon surface caused by ion implantation, activating implanted impurities, and eliminating further diffusion of the impurities by using an RTP (real time protocol) process.
Step five: a first polysilicon gate 208 is formed in the first P-Well region 105 and a second polysilicon gate 209 is formed in the second P-Well region 107. The method specifically comprises the following steps:
the growth of the sacrificial oxide layer serves to trap defects on the silicon surface. The gate oxide layer grows to be used as a gate insulating layer of the transistor, the first polysilicon gate 208 and the second polysilicon gate 209 are deposited by using chemical vapor deposition (LPCVD), photoresist is formed, polysilicon etching is carried out, the specific shape of polysilicon must be accurately obtained from the photoresist, and the photoresist layer is removed. And oxidizing the polysilicon to buffer and isolate the polysilicon and the silicon nitride formed in the subsequent step. And depositing a layer of silicon nitride by using chemical vapor deposition (LPCVD), etching the silicon nitride, leaving the isolation side wall, and accurately positioning the ion implantation of the source region and the drain region of the transistor.
Step six: by photolithography, a first P + implantation region 108 is formed in the first P-Well region 105, and a second P + implantation region 113 is formed in the second P-Well region 107. The method specifically comprises the following steps:
and photoresist is formed and used for controlling ion implantation, implanting shallow-depth and heavily-doped boron ions, forming a P + implantation region in the first P-Well region 105, removing a photoresist layer from a P + implantation region in the second P-Well region 107, and forming the first P + implantation region 108 and the second P + implantation region 113.
Step seven: by photolithography, a first N + implantation region 109 is formed in the first P-Well region 105, a second N + implantation region 110 and a third N + implantation region 111 are formed in the second DN-Well region 1042, and a fourth N + implantation region 112 is formed in the second P-Well region 107. The method specifically comprises the following steps:
and photoresist is formed and used for controlling ion implantation, and implanting shallow-depth and heavily-doped arsenic ions to form an N + implantation region in the first P-Well region 105, an N + implantation region in the N-Well region, an N + implantation region and an N + implantation region in the second P-Well region 107, and the photoresist layer is removed to form the first N + implantation region 109, the second N + implantation region 110, the third N + implantation region 111 and the fourth N + implantation region 112.
And annealing the first P + implantation region 108, the second P + implantation region 113, the first N + implantation region 109, the second N + implantation region 110, the third N + implantation region 111 and the fourth N + implantation region 112, and eliminating further migration of impurities in the implantation regions by using an RTP process.
The first polysilicon gate 208 in the first P-Well region 105 and the second polysilicon gate 209 in the second P-Well region 107 form an enhanced gate control structure, the first N + implant region 109 and the third field oxide isolation region 203 are isolated by the first polysilicon gate 208, and the first polysilicon gate 208 is connected to a cathode. The fifth field oxide isolation regions 205 and the fourth N + implant regions 112 are isolated by the second polysilicon gate 209, and the second polysilicon gate 209 is connected to the anode, as shown in fig. 2 and 3. Due to the existence of the enhanced gate control structure, the device structure can reduce the on-resistance of the bidirectional controllable silicon device, the gain of a positive feedback loop of the controllable silicon is improved, and the failure current is effectively improved. Therefore, the device can bear high-strength ESD current pulse stress without generating soft failure and surface breakdown phenomena in advance, the leakage current of the device is always kept at a lower order of magnitude, and a surface ESD path generated by an electric field effect can be blocked by the field oxide isolation region. And because the buried layer NBL structure is added, the ESD current stress of the bidirectional silicon controlled device can be released in the buried layer with low resistance by combining the enhanced gate control structure, the maintaining voltage of the device structure is effectively improved, the device is prevented from generating latch-up effect, and the signal integrity of a core circuit in the chip is ensured.
Under high voltage environment, when high voltage positive ESD current pulse stress comes to the anode of the device and the cathode is grounded, the first N + injection region 109, the first P-Well region 105 and the N-Well region will form a longitudinal NPN2The triode structure has paths in the equivalent circuit due to positive and negative symmetry, and the NPN tube hasTwo, so for distinction, subscript 2 is added; meanwhile, the first P-Well region 105, the N-Well region and the second P + injection region 113 form a lateral PNP triode structure I, and a base electrode and a longitudinal NPN of the lateral PNP triode structure I2Parasitic resistance R of collector of triode structure passing through N-Well regionnConnected in a vertical NPN2Parasitic resistance R of base of triode structure and collector of lateral PNP triode structure I through first P-Well region 105P2Connected, i.e. said lateral PNP triode structure I and said longitudinal NPN2The triode structure forms a thyristor structure.
Under high voltage environment, when high voltage reverse ESD current pulse stress comes to the anode of the device and the cathode is at ground potential, the fourth N + injection region 112, the second P-Well region 107 and the N-Well region will form a longitudinal NPN1The triode structure is formed by the second P-Well region 107, the N-Well region and the first P + injection region 108 to form a lateral PNP triode structure II, a base of the lateral PNP triode structure II and a longitudinal NPN1Parasitic resistance R of collector of triode structure passing through N-Well regionnConnected in a vertical NPN1Parasitic resistance R of base of triode structure and collector of lateral PNP triode structure II through second P-Well region 107P1Connected, i.e. said lateral PNP triode structure II and said longitudinal NPN1The triode structure forms a thyristor structure.
Based on the first polysilicon gate 208 in the first P-Well region 105 and the second polysilicon gate 209 in the second P-Well region 107, an enhanced gate control structure is formed, and based on a conventional triac structure, the enhanced gate control structure is added, when high-voltage forward ESD current pulse stress comes to the anode of the device and the cathode is at ground potential, the trigger voltage of the device is determined by the reverse avalanche breakdown voltage of the first P-Well region 105 and the N-Well region, and the magnitude of the avalanche breakdown voltage is determined by the distance between the first P-Well region 105 and the N-Well region. When high-voltage reverse ESD current pulse stress comes to the anode of the device and the cathode is at the ground potential, the trigger voltage of the device is determined by the reverse avalanche breakdown voltage of the second P-Well region 107 and the N-Well region, and the magnitude of the avalanche breakdown voltage is determined by the distance between the second P-Well region 107 and the N-Well region. Due to the existence of the enhancement-type gate control structure, when the device structure is turned on in the forward direction, the second polysilicon gate 209 located at the anode generates a vertically downward electric field force to promote the movement of carriers in the second P-Well region 107, and an electron channel generated under the second polysilicon gate 209 by the electric field effect is blocked by the fifth field oxide isolation region 205, so that a surface current path is suppressed. The first polysilicon gate 208 at the cathode generates a vertical upward electric field force that promotes the movement of carriers in the first P-Well region 105. When the device structure is reversely conducted, the first polysilicon gate 208 located at the cathode generates a vertically downward electric field force to promote the movement of carriers in the first P-Well region 105, and an electron channel generated under the first polysilicon gate 208 by the electric field effect is blocked by the third field oxide isolation region 203 to suppress a surface current path. The second polysilicon gate 209 at the anode generates a vertically upward electric field force that promotes carrier movement in the second P-Well region 107. And the direction of the electric field force is always consistent with the current discharge direction, and the aims of reducing the on-resistance and improving the failure current are fulfilled on the positive feedback loop of the silicon controlled rectifier. Due to the existence of the NBL region 102, ESD discharge paths of the device are all located in the buried layer NBL region 102, the formation of a surface passage of the device structure is inhibited, the possibility of surface thermal breakdown of the device is reduced, the current discharge distance from an anode to a cathode of the device structure is increased, the holding voltage is effectively improved, and the latch-up effect is prevented.
The invention provides a manufacturing method of a bidirectional enhanced gate-controlled silicon controlled electrostatic protection device structure, which is simple in process and convenient to operate. The manufactured bidirectional enhanced gate-controlled silicon electrostatic protection device structure does not violate layout design rules, and does not use layers except a standard BCD process, so that the bidirectional enhanced gate-controlled silicon electrostatic protection device structure can be applied to ESD protection design in a high-voltage environment, an inner core chip is effectively protected, a latch-up effect is prevented, and the ESD resistance of the chip is improved.
Claims (8)
1. The utility model provides a two-way enhancement mode grid-controlled silicon controlled rectifier electrostatic protection device which characterized in that: the substrate P-Sub is provided with an NBL region, and the NBL region is sequentially provided with a first DN-Well region, a first P-EPI region, a second DN-Well region, a second P-EPI region and a third DN-Well region from left to right;
the first P-Well region is arranged in the first P-EPI region, and a first field oxide isolation region, a first P + injection region, a second field oxide isolation region, a first N + injection region and a first polysilicon gate are sequentially arranged in the first P-Well region from left to right;
an N-Well region is arranged in the second DN-Well region, and a third field oxide isolation region, a second N + injection region, a fourth field oxide isolation region, a third N + injection region and a fifth field oxide isolation region are sequentially arranged in the N-Well region from left to right;
a second P-Well region is arranged in the second P-EPI region, and a second polysilicon gate, a fourth N + injection region, a sixth field oxide isolation region, a second P + injection region and a seventh field oxide isolation region are sequentially arranged in the second P-Well region from left to right;
the first P + injection region, the first N + injection region and the first polysilicon gate are connected together and led out to serve as a cathode of the device; and the second polysilicon gate, the fourth N + injection region and the second P + injection region are connected together and led out to serve as an anode of the device.
2. The bi-directional enhancement mode gated silicon controlled electrostatic protection device of claim 1, wherein: the left side of first field oxygen isolation region is connected with the left side edge in first DN-Well district, the right side of first field oxygen isolation region with the left side in first P + injection zone is connected, the right side in first P + injection zone with the left side of second field oxygen isolation region is connected, the right side of second field oxygen isolation region with the left side in first N + injection zone is connected, the right side in first N + injection zone with the left side of first polysilicon gate is connected, the right side and the first P-Well district right side edge parallel and level of first polysilicon gate.
3. The bi-directional enhancement mode gated silicon controlled electrostatic protection device of claim 2, wherein: the left side of third field oxygen isolation region with the right side of first polycrystalline silicon gate is connected, the right side of third field oxygen isolation region with the left side in second N + injection zone is connected, the right side in second N + injection zone with the left side in fourth field oxygen isolation region is connected, the right side of fourth field oxygen isolation region with the left side in third N + injection zone is connected, the right side in third N + injection zone with the left side in fifth field oxygen isolation region is connected, the right side in fifth field oxygen isolation region is connected with second P-Well district left side edge.
4. The bi-directional enhancement mode gated silicon controlled electrostatic protection device of claim 3, wherein: the left side of second polycrystalline silicon gate with second P-Well district left side edge parallel and level, the right side of second polycrystalline silicon gate with the left side in fourth N + injection zone is connected, the right side in fourth N + injection zone with the left side in sixth field oxygen isolation region is connected, the right side in sixth field oxygen isolation region with the left side in second P + injection zone is connected, the right side in second P + injection zone with the left side in seventh field oxygen isolation region is connected, the right side in seventh field oxygen isolation region with the right side edge in third DN-Well district is connected.
5. The bi-directional enhancement mode gated silicon controlled electrostatic protection device of claim 4, wherein: the first polysilicon gate in the first P-Well region and the second polysilicon gate in the second P-Well region form an enhanced gate control structure, the enhanced gate control structure generates a vertical downward electric field force at the anode of the device and a vertical upward electric field force at the cathode of the device, and the direction of the electric field force is always consistent with the current conduction direction, so that the movement of current carriers in the device is promoted, and the failure current of the device structure is improved.
6. The device of claim 5, wherein the device is a bi-directional enhancement mode gated thyristorCharacterized in that: under the high-voltage environment, when high-voltage positive ESD current pulse stress comes to the anode of the device and the cathode of the device is at the ground potential, the first N + injection region, the first P-Well region and the N-Well region form a longitudinal NPN2The triode structure comprises a transverse PNP triode structure I formed by the first P-Well region, the N-Well region and the second P + injection region, and a base electrode and a longitudinal NPN of the transverse PNP triode structure I2The collectors of the triode structure are connected through the parasitic resistance of the N-Well region, and the longitudinal NPN2The base electrode of the triode structure is connected with the collector electrode of the transverse PNP triode structure I through the parasitic resistor of the first P-Well area, namely the transverse PNP triode structure I and the longitudinal NPN triode structure2The triode structure forms a thyristor structure.
7. The bi-directional enhancement mode gated silicon controlled electrostatic protection device of claim 5, wherein: under a high-voltage environment, when high-voltage reverse ESD current pulse stress comes to the anode of the device and the cathode of the device is at the ground potential, the fourth N + injection region, the second P-Well region and the N-Well region form a longitudinal NPN1The triode structure comprises a transverse PNP triode structure II formed by a second P-Well region, an N-Well region and a first P + injection region, and a base electrode and a longitudinal NPN of the transverse PNP triode structure II1The collectors of the triode structure are connected through the parasitic resistance of the N-Well region, and the longitudinal NPN1The base electrode of the triode structure is connected with the collector electrode of the transverse PNP triode structure II through the parasitic resistance of the second P-Well area, namely the transverse PNP triode structure II and the longitudinal NPN triode structure1The triode structure forms a thyristor structure.
8. A method for fabricating the bi-directional enhancement type gated silicon controlled electrostatic protection device according to any one of claims 1 to 7, comprising the steps of:
the method comprises the following steps: forming an NBL region on the substrate P-Sub;
step two; a first DN-Well area, a first P-EPI area, a second DN-Well area, a second P-EPI area and a third DN-Well area are formed on the NBL area from left to right in sequence;
step three: forming first to seventh field oxide isolation regions by photolithography;
step four: forming a first P-Well region in the first P-EPI region, a second P-Well region in the second P-EPI region, and an N-Well region in the second DN-Well region by photolithography;
step five: forming a first polysilicon gate in the first P-Well region, and forming a second polysilicon gate in the second P-Well region;
step six: forming a first P + injection region in the first P-Well region and a second P + injection region in the second P-Well region by photoetching;
step seven: and forming a first N + injection region in the first P-Well region, forming a second N + injection region and a third N + injection region in the second DN-Well region, and forming a fourth N + injection region in the second P-Well region by photoetching.
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