CN207183270U - A kind of bidirectional thyristor electrostatic protection device of insertion without channel-type LDPMOS - Google Patents
A kind of bidirectional thyristor electrostatic protection device of insertion without channel-type LDPMOS Download PDFInfo
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- CN207183270U CN207183270U CN201721140240.7U CN201721140240U CN207183270U CN 207183270 U CN207183270 U CN 207183270U CN 201721140240 U CN201721140240 U CN 201721140240U CN 207183270 U CN207183270 U CN 207183270U
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- 230000002457 bidirectional effect Effects 0.000 title claims abstract description 12
- 238000003780 insertion Methods 0.000 title claims abstract description 7
- 230000037431 insertion Effects 0.000 title claims abstract description 7
- 238000002347 injection Methods 0.000 claims abstract description 84
- 239000007924 injection Substances 0.000 claims abstract description 84
- 230000005516 deep trap Effects 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims description 4
- 230000003068 static effect Effects 0.000 abstract description 9
- 230000005611 electricity Effects 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000001681 protective effect Effects 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 238000012423 maintenance Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 3
- VMXJCRHCUWKQCB-UHFFFAOYSA-N NPNP Chemical compound NPNP VMXJCRHCUWKQCB-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 210000001367 artery Anatomy 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000009024 positive feedback mechanism Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 210000003462 vein Anatomy 0.000 description 1
- 210000000707 wrist Anatomy 0.000 description 1
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- Semiconductor Integrated Circuits (AREA)
Abstract
The utility model discloses a kind of bidirectional thyristor electrostatic protection device of insertion without channel-type LDPMOS, including：P type substrate；The the first N-type deep trap and the second N-type deep trap being formed in P type substrate；The p-well being arranged in P type substrate；Positioned at eight doped regions of the first N-type deep trap, the second N-type deep trap and p-well：First N+ injection regions, the first P+ injection regions, the first Poly implanted layers, the 2nd P+ injection regions, 3rd P+ injection regions, the 2nd Poly implanted layers, the 4th P+ injection regions, the 2nd N+ injection regions, across the first N-type deep trap and p-well, the first Poly implanted layers are connected across on the first P+ injection regions but are not connected across on the 2nd P+ injection regions for 2nd P+ injection regions；Across the second N-type deep trap and p-well, the 2nd Poly implanted layers are connected across on the 4th P+ injection regions but are not connected across on the 3rd P+ injection regions for 3rd P+ injection regions.The utility model has the ability of two-way static electricity discharge by the embedded ability that can strengthen device static electricity discharge while device trigger voltage is reduced without channel-type LDPMOS.
Description
Technical field
It the utility model is related to Integrated circuit electrostatic protective device design field, more particularly to one kind can release positive electrostatic arteries and veins
Punching and negative electrostatic pulse, have that electrical characteristics are symmetrical, uniformly release, the bidirectional triode thyristor device of high-protection level.
Background technology
Static discharge（Electro-Static Discharge, ESD）It is that integrated circuit is being manufactured, encapsulate, tested, defeated
Inevitable phenomenon during fortune, assembling and use, ESD, which is destroyed, has disguise, latency, randomness and complexity etc.
Feature.Electrostatic has accounted for 30% in a variety of causes of ic failure, and serious prestige is constituted to the reliability of integrated circuit
The side of body, improve the ESD protective capacities of electronic product or IC chips, there is extremely important meaning to the reliability for improving them
Justice.The approach for carrying out electrostatic protection to integrated circuit has two：When the generation that control and minimizing electrostatic are produced and discharged, such as make
With electrostatic protective suit, antistatic wrist strap etc.；Second, designing electrostatic leakage device in chip periphery, path of releasing is provided for electrostatic.
Electrostatic leakage device in approach two avoids electric current during static discharge from flowing into IC internal circuits equivalent to " lightning rod " in chip
And cause to damage, it is a kind of safeguard measure most direct and common at present.
Silicon-controlled device（Silicon Controlled Rectifier, SCR）It is the conventional device of ESD protection in chip
Structure, but it is not the normal component in CMOS technology.It is compared with diode, triode, field-effect transistor, because of its own
Positive feedback mechanism and with current drain ability is strong, unit area is released small efficiency high, conducting resistance, strong robustness, protection
The advantages of rank is high, higher electrostatic protection grade can be reached with less chip area in semiconductor planar technique.Together
When, most power ports provide generating positive and negative voltage now, such as ± 12 arrive ± 15V, therefore we have selected with high robust
And the two-way BSCR that degree of protection is high（dual-directional SCR）.But high triggering is brought unavoidably from SCR device
The characteristics of voltage, low maintenance voltage easy breech lock.
LDMOS（Lateral Double Diffused Metal Oxide Semiconductor Field Effect
Transistor）Lateral double diffused metal-oxide field-effect transistor is to be proposed by Y.Tarui et al. for 1969 earliest,
It is on the basis of common MOSFET advantages are kept, and channel region is formed by horizontal double diffusion technique, and in drain electrode and raceway groove
Between introduce drift region.Drift region can use epitaxy technique, can also use ion implanting.The LDMOS and MOSFET of early stage
Difference mainly have at 2 points：1. a longer low concentration N- drift region is added between raceway groove and drain electrode.High resistant drift region
Presence improve breakdown voltage, and reduce parasitic capacitance Lou, between the two poles of the earth of source, be advantageous to improve frequency characteristic.Meanwhile
Cushioning effect is played in drift region between raceway groove and leakage, weakens LDMOS short-channel effect.2. the length of channel region is mainly by two
The junction depth of secondary diffusion controls, so channel length can be made very small without being limited by lithographic accuracy, thus can be right
Channel region is accurately controlled, and after the measure of increase furrow width, the electric current of device can also be made larger.LDMOS has
High-gain, high transconductance, frequency response are good, High Linear, control are simple, the safety operation area that switching speed is fast, big, without locking, heat
Stability is good, easily with CMOS circuits it is integrated the advantages that and be widely used, while to the research of LDMOS device,
More and more everybody attention is obtained.
As shown in figure 1, be a kind of typical embedded LDPMOS two-way SCR profiles, its equivalent circuit diagram such as Fig. 2 institutes
Show.The device can be used for the ESD protection of power integrated circuit on piece, because the embedded resistance to voltage devices of LDPMOS can be obviously improved
The voltage endurance capability and robustness of protective device, but when in the hyperbaric environment for being used in ± 12V, its trigger voltage is too high, when
When being used in ± 35V hyperbaric environments, its maintenance voltage is too low.Therefore, it is necessary in the two-way of this typical embedded LDPMOS
The optimization to its trigger voltage and maintenance voltage is carried out on the basis of SCR device.
The content of the invention
The utility model solves the problems, such as to be to provide a kind of bidirectional thyristor electrostatic protection of insertion without channel-type LDPMOS
Device, it is too low too high with trigger voltage to solve the problems, such as to be used in its maintenance voltage under high-pressure situations.
Technical scheme is as follows used by the utility model solves above-mentioned technical problem：One kind is embedded without channel-type LDPMOS
Bidirectional thyristor electrostatic protection device, including：P-type semiconductor substrate；The first N-type deep trap being formed in P type substrate, p-well,
Second N-type deep trap；From left to right there are the first N+ injection regions, the first P+ injection regions, the first Poly injections in first N-type deep trap successively
Layer, the 2nd P+ injection regions, the first Poly implanted layers are connected across between the first P+ areas and the 2nd P+ areas, the bridging of the first Poly implanted layers
It is not connected across on the first P+ injection regions but on the 2nd P+ injection regions, the 2nd P+ injection regions are across the first type N deep traps and the
One p-well；From left to right there are the 3rd P+ injection regions, the 2nd Poly implanted layers, the 4th P+ injection regions in second N-type deep trap successively, the
Two N+ are injected, and the 2nd Poly implanted layers are connected across between the 3rd P+ areas and the 4th P+ areas, and the 2nd Poly implanted layers are connected across the 4th P
It is not connected across on+injection region but on the 3rd P+ injection regions, the 3rd P+ injection regions are across the first p-well and the second N-type deep trap；Institute
State the first N+ injection regions, the first P+ injection regions and the first Poly implanted layers and connect negative electrode；The 2nd Poly implanted layers, the 4th P+ notes
Enter area and the 2nd N+ injection regions and connect anode.
Bidirectional thyristor electrostatic protection device of the present utility model can reduce device by embedded without channel-type LDPMOS
Strengthen the ability of device static electricity discharge, and the ability with two-way static electricity discharge while trigger voltage, standard technology can be used
With being integrated on protection circuit piece.The ESD electrostatic protection characteristic curves of its almost symmetry, available for the collection for transmitting positive and negative signal
Into circuit input and output pin；With high unit area electrostatic leakage ability, antistatic capacity is strong, can meet in high tabletting
Integrated static protective device reaches the requirement of optimal robustness in chip area as small as possible.
Brief description of the drawings
Fig. 1 is the two-way SCR electrostatic protection devices profile for existing embedded LDPMOS；
Fig. 2 is the equivalent circuit diagram of existing embedded LDPMOS two-way SCR electrostatic protection devices；
Fig. 3 is two-way SCR device profile of the utility model without channel-type LDPMOS；
Fig. 4 is two-way SCR device equivalent circuit diagram of the utility model without channel-type LDPMOS；
Fig. 5 is two-way SCR device domain schematic diagram of the utility model without channel-type LDPMOS.
Embodiment
With reference to embodiments, the utility model is further described.Following explanation be in a manner of enumerating, but
The scope of protection of the utility model is not limited thereto.
As shown in figure 3, bidirectional thyristor electrostatic protection device of a kind of insertion without channel-type LDPMOS of the present utility model,
The device includes 4 layers, and wherein bottom is P type substrate 100；The second layer is the He of the first N-type deep trap 201 being formed in P type substrate
Second N-type deep trap 202；Third layer is the p-well 300 being arranged in P type substrate；4th layer is positioned at the first N-type deep trap 201, the
Eight doped regions of two N-type deep traps 202 and p-well 200：In first N-type deep trap 201, the first N+ injection regions are from left to right followed successively by
401st, the first P+ injection regions 402, the first Poly implanted layers 701, the 2nd P+ injection regions 601, wherein, the 2nd P+ injection regions 601 are horizontal
Across the first N-type deep trap 201 and p-well 300, the first Poly implanted layers 701 are connected across between the first P+ areas 402 and the 2nd P+ areas 601,
First Poly implanted layers 701 are connected across on the first P+ injection regions 402 but are not connected across on the 2nd P+ injection regions 601；2nd N
In moldeed depth trap 202, be from left to right followed successively by the 3rd P+ injection regions 602, the 2nd Poly implanted layers 702, the 4th P+ injection regions 501,
2nd N+ injection regions 502；Wherein, the 3rd P+ injection regions 602 are across the second N-type deep trap 202 and p-well 300, the 2nd Poly implanted layers
702 are connected across between the 3rd P+ areas 602 and the 4th P+ areas 501, and the 2nd Poly implanted layers 702 are connected across the 4th P+ injection regions 501
It is upper not to be connected across on the 3rd P+ injection regions 602 still.
Standard technology can be used with being integrated on protection circuit piece in bidirectional triode thyristor device of the present utility model, particularly electricity
The chip that source domain is ± 12V is protected.Its equivalent circuit is as shown in Figure 4.By the first P+ injection regions 402, p-well 300, the first N-type
Deep trap 201 forms PNP transistor T21；By the first P+ injection regions 402, the 2nd P+ injection regions 601, the structure of the first N-type deep trap 201
Into PNP transistor T23；Wherein T21 and T23 is parallel relationship.By the 2nd N+ injection regions 502, the 2nd P+ injection regions 601 and
Three P+ injection regions 602, the first N-type deep trap 201 form NPN transistor T22.
When esd pulse is added in anode, the first N-type deep trap 201 and the 2nd P+ injection regions 601 are reverse-biased.If pulse voltage
Higher than the avalanche breakdown voltage of the knot, a large amount of avalanche currents are produced in device.Electric current flows to negative electrode through N trap dead resistances R22, when
The voltage at the dead resistance both ends is tied higher than the cb of T22 transistors（First N traps 201 and p-well 300 form the cb of T22 transistors
Knot）During forward conduction voltage, T22 is opened.The T22 of unlatching provides base current for transistor T21//T23.Even if hereafter do not have
Avalanche current produces, and T22 and T21//T23 constituted positive feedback loop, by NPN type crystal T22 and PNP transistor T21//
The SCR structure that T23 is formed is switched on, static electricity discharge.Similarly, when esd pulse occurs in negative electrode, or there is negative ESD electricity in anode
When pressing pulse, the second N-type deep trap 202 and the avalanche breakdown of the 3rd P+ injection regions 602 are then, brilliant by NPN type crystal T22 and positive-negative-positive
The SCR structure conducting static electricity discharge that body pipe T21//T23 is formed.
The utility model LDPMOS_BSCR as the electrostatic protection device in chip, with by protection kernel circuitry it is integrated when,
First N+ injection regions 401, the first P+ injection regions 402 and the first Poly implanted layers 701 are used as electrical anode, the 2nd Poly injections
The 702, the 4th P+ injection regions 501 of layer and the 2nd N+ injection regions 502 are used as electrical cathode, i.e., device profile map shown in Fig. 3.
Device as shown in Figure 3, from electrical anode to electrical cathode, SCR paths are that the first N+ injection regions 401 and the 2nd P+ are noted
Enter area 601, the first N-type deep trap 201, the P+ injection regions 601/602/501 of p-well the 300, second/the 3rd/the 4th and the second N-type deep trap
202nd, the NPNP SCR structures that the 2nd N+ injection regions 502 are formed.From electrical cathode to electrical anode, SCR paths are the 2nd N+
The P+ injection regions 602 of injection region 502 and the 4th, the second N-type deep trap 202, p-well 300, the 4th/the 3rd/the 2nd P+ injection regions 501/
602/601 and the NPNP SCR structures that form of the first N-type deep trap 201, the first N+ injection regions 401.
Electrical anode and electrically between include the P+ of first/second N-type deep trap 201/202 and the second/the 3rd injection and P
The NPN triode structure that trap 300 is formed；First/second P+ injection regions 402/601 and the first N-type deep trap 201, the 3rd/the 4th P+
Two PNP triode structures that the N-type deep trap 202 of injection region 602/501 and second is formed.
As shown in figure 4, PNP transistor T3 is by first/second P+ injection regions 402/601 and the structure of the first N-type deep trap 201
Into T23 and T21 is parallel relationship.PNP transistor T22 is noted by the P+ of first/second N-type deep trap 201/202 and the second/the 3rd
Enter and p-well 300 is formed.
As shown in figure 3, because the first Poly implanted layers 701 are connected across between the first P+ areas 402 and the 2nd P+ areas 601, the
One Poly implanted layers 701 are connected across on the first P+ injection regions 402 but are not connected across on the 2nd P+ injection regions 601；Second
Poly implanted layers 702 are connected across between the 3rd P+ areas 602 and the 4th P+ areas 501, and the 2nd Poly implanted layers 702 are connected across the 4th P+
It is not connected across on injection region 501 but on the 3rd P+ injection regions 602.Mp21 as shown in Figure 4 and Mp22 is caused to be formed
Raceway groove.So as to which Mp21 and Mp22 is not traditional LDPMOS, in device shown in the Fig. 3, negative electrode is flowed to from anode when there is electric current
When, Mp21 is no longer the LDPMOS of OFF state but is used as a big resistance.Now its equivalent circuit diagram is as shown in Figure 4.
As shown in figure 4, when there is electric current to flow to negative electrode from anode, the reverse biased junction of no two-way SCR devices of channel-type LDPMOS
Tied for T21//T23 cb, form the structure is the P+ of the first N-type deep trap 201/ the 2nd injections 601.As shown in Figure 1 is existing
In the two-way SCR devices of embedded LDPMOS, its reverse-biased cb knots for becoming T11//T13, form the structure is N-type deep trap/p-well,
Because the doping concentration of p-well is lower than P+ injection region, T11//T13 cb knots avalanche breakdown voltage can be higher than T21//T23 cb knots；
And because Mp21 and Mp22 can not form raceway groove, when there is electric current to flow to negative electrode from anode, Mp21 is no longer the LDPMOS of OFF state
But a big resistance is used as, equivalent circuit diagram now is as shown in figure 4, so insertion can make two-way without channel-type LDPMOS
SCR device effectively reduces trigger voltage.After the trigger, because T22 base stage is more much smaller than T12, T22 multiplication factor meeting
More than T12, path where T22 is let out flows through more current than path where T12, therefore, no two-way SCR devices of channel-type LDPMOS
Failure electric current can be more than the existing embedded two-way SCR devices of LDPMOS.To sum up, no two-way SCR devices of channel-type LDPMOS
Trigger voltage and failure electric current can all have certain optimization.
As shown in figure 5, the utility model uses interdigitated bidirectional thyristor electrostatic protection device domain, domain possesses as follows
Characteristic：Device is finger, and convenient device is the placement-and-routing in the case of finger more, anode press welding block and negative electrode pressure welding block layout
Above and below device, it is easy to electrostatic to improve device electrostatic protection grade to uniformly releasing on four sides.
The utility model uses interdigitated bidirectional thyristor electrostatic protection device domain, equally suitable to one-way SCR device
With the utility model layout design method is applied to other unidirectional device structures simultaneously（NMOS, BJT, diode）Domain set
Meter, the unit area electrostatic leakage efficiency of device is effectively improved, there is generality.
Preferred embodiment of the present utility model is the foregoing is only, is not limited to the utility model, for this area
For technical staff, the utility model can have various changes and change.All institutes within spirit of the present utility model and principle
Any modification, equivalent substitution and improvements of work etc., should be included within the scope of protection of the utility model.
Claims (1)
- A kind of 1. bidirectional thyristor electrostatic protection device of insertion without channel-type LDPMOS, it is characterised in that including：P-type semiconductor substrate；The first N-type deep trap being formed in P type substrate, p-well, the second N-type deep trap；From left to right there are the first N+ injection regions, the first P+ injection regions, the first Poly implanted layers, the 2nd P successively in first N-type deep trap + injection region, the first Poly implanted layers are connected across between the first P+ areas and the 2nd P+ areas, and the first Poly implanted layers are connected across the first P+ It is not connected across on injection region but on the 2nd P+ injection regions, the 2nd P+ injection regions are across the first type N deep traps and the first p-well；From left to right there are the 3rd P+ injection regions, the 2nd Poly implanted layers, the 4th P+ injection regions, the 2nd N in second N-type deep trap successively + injection, the 2nd Poly implanted layers are connected across between the 3rd P+ areas and the 4th P+ areas, and the 2nd Poly implanted layers are connected across the 4th P+ notes Enter in area but be not connected across on the 3rd P+ injection regions, the 3rd P+ injection regions are across the first p-well and the second N-type deep trap；First N+ injection regions, the first P+ injection regions and the first Poly implanted layers connect negative electrode；The 2nd Poly implanted layers, Four P+ injection regions and the 2nd N+ injection regions connect anode.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201721140240.7U CN207183270U (en) | 2017-09-07 | 2017-09-07 | A kind of bidirectional thyristor electrostatic protection device of insertion without channel-type LDPMOS |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201721140240.7U CN207183270U (en) | 2017-09-07 | 2017-09-07 | A kind of bidirectional thyristor electrostatic protection device of insertion without channel-type LDPMOS |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108807374A (en) * | 2018-07-03 | 2018-11-13 | 江南大学 | A kind of high-voltage bidirectional Transient Voltage Suppressor |
| CN110289257A (en) * | 2019-06-28 | 2019-09-27 | 湖南师范大学 | Two-way enhanced silicon-controlled electrostatic protection device of grid-control of one kind and preparation method thereof |
| US20220302104A1 (en) * | 2019-09-26 | 2022-09-22 | Csmc Technologies Fab2 Co., Ltd. | Bidirectional esd protection device and electronic apparatus |
-
2017
- 2017-09-07 CN CN201721140240.7U patent/CN207183270U/en not_active Withdrawn - After Issue
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108807374A (en) * | 2018-07-03 | 2018-11-13 | 江南大学 | A kind of high-voltage bidirectional Transient Voltage Suppressor |
| CN108807374B (en) * | 2018-07-03 | 2020-07-24 | 江南大学 | High-voltage bidirectional transient voltage suppressor |
| CN110289257A (en) * | 2019-06-28 | 2019-09-27 | 湖南师范大学 | Two-way enhanced silicon-controlled electrostatic protection device of grid-control of one kind and preparation method thereof |
| CN110289257B (en) * | 2019-06-28 | 2021-09-14 | 湖南师范大学 | Bidirectional enhanced gate-controlled silicon controlled electrostatic protection device and manufacturing method thereof |
| US20220302104A1 (en) * | 2019-09-26 | 2022-09-22 | Csmc Technologies Fab2 Co., Ltd. | Bidirectional esd protection device and electronic apparatus |
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