CN115274841A - Silicon controlled rectifier structure capable of adjusting high maintaining voltage and low trigger voltage - Google Patents
Silicon controlled rectifier structure capable of adjusting high maintaining voltage and low trigger voltage Download PDFInfo
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- CN115274841A CN115274841A CN202210669459.5A CN202210669459A CN115274841A CN 115274841 A CN115274841 A CN 115274841A CN 202210669459 A CN202210669459 A CN 202210669459A CN 115274841 A CN115274841 A CN 115274841A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 16
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 16
- 239000010703 silicon Substances 0.000 title claims abstract description 16
- 238000002347 injection Methods 0.000 claims abstract description 71
- 239000007924 injection Substances 0.000 claims abstract description 71
- 238000002955 isolation Methods 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 150000002500 ions Chemical class 0.000 claims description 75
- 238000005468 ion implantation Methods 0.000 claims description 54
- -1 boron ions Chemical class 0.000 claims description 12
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 82
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000001276 controlling effect Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/7404—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device
- H01L29/742—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device the device being a field effect transistor
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a silicon controlled rectifier structure with adjustable high maintaining voltage and low trigger voltage, which comprises a P-type substrate, wherein an N well and a P well which are adjacent to each other are formed on the P-type substrate; the N trap is provided with second shallow trench isolations and a second shallow trench isolations which are sequentially distributed at intervals, a first N-type ion injection layer is formed between the first shallow trench isolation and the second shallow trench isolation, and a first grid electrode, a first P-type ion injection layer and a second P-type ion injection layer are formed on one side of the second shallow trench isolation; the P well is provided with third shallow trench isolations and fourth shallow trench isolations which are sequentially distributed at intervals, a third P-type ion injection layer is formed between the third shallow trench isolations and the fourth shallow trench isolations, one part of the second N-type ion injection layer crosses the N well and the P well, and the other part of the second N-type ion injection layer is positioned in the P well; and a fifth shallow trench isolation is arranged between the second P-type ion injection layer and the second N-type ion injection layer. The invention can reduce the trigger voltage; the sustain voltage is increased; the trigger voltage is adjusted.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a silicon controlled rectifier structure with adjustable high maintaining voltage and low trigger voltage.
Background
With the continuous reduction of the manufacturing process, the thickness of a gate oxide layer of a transistor is thinner and thinner, and the breakdown voltage and the working voltage of the gate oxide are reduced continuously. In addition, the rate of the drop of the chip working voltage is lower compared with the rate of the drop of the transistor gate oxide breakdown voltage and the source-drain breakdown voltage. Therefore, when performing ESD (low capacitance static) design, a 10% safety margin must be considered, resulting in a narrower ESD design window and very limited ESD options. A Silicon Controlled Rectifier (SCR) is an ESD protection device with the highest robustness per unit area, and can be regarded as a positive feedback loop formed by two parasitic transistors PNP and NPN. The IV (current-voltage) characteristic of the transistor shows a very obvious hysteresis characteristic, and the holding voltage is very low, which is very easy to cause latch-up.
GGNMOS (grounded NMOS tube) is triggered by N ion injection and junction breakdown voltage of a P trap, and has relatively low trigger voltage, and researches show that the trigger voltage can be effectively reduced by embedding the GGNMOS into SCR, and the novel structure is named as a low trigger voltage silicon controlled rectifier (NLVTSCR) containing the GGNMOS. The GGNMOS speeds up the SCR triggering process, but the holding voltage of the LVTSCR is still low due to the strong hysteresis of the SCR, which faces a higher risk of latch-up. Similarly, a low trigger voltage silicon controlled rectifier (PLVTSCR) with PMOS has been developed by embedding GDPMOS (Gate-to-Drain PMOS) in the SCR structure. The cross-over region in the SCR provides an ESD shunt path, which can reduce the ESD current of the parasitic SCR path in the body, thereby improving the holding voltage of MLSCR (lateral silicon controlled rectifier), but the trigger voltage of MLSCR may be higher than the breakdown voltage of gate oxide under low voltage operation, and is still insufficient to protect the internal circuit from failure.
To solve the above problems, a new type of scr structure with high holding voltage and low trigger voltage is needed.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a scr structure with adjustable high holding voltage and low trigger voltage, which is used to solve the problem that the current-voltage characteristics of the scr in the prior art exhibit obvious hysteresis characteristics, the holding voltage is often very low, and latch-up is very easily caused.
To achieve the above and other related objects, the present invention provides a scr structure with adjustable high holding voltage and low trigger voltage, comprising:
the semiconductor device comprises a P-type substrate, wherein an N well and a P well which are adjacent to each other are formed on the P-type substrate;
the N well is provided with first shallow trench isolation and second shallow trench isolation which are sequentially distributed at intervals, a first N-type ion injection layer is formed between the first shallow trench isolation and the second shallow trench isolation, a first grid electrode, a first P-type ion injection layer and a second P-type ion injection layer are formed on one side, far away from the first N-type ion injection layer, of the second shallow trench isolation, the first P-type ion injection layer and the second P-type ion injection layer are respectively arranged on two sides of the first grid electrode, one part of the second P-type ion injection layer stretches across the junction of the N well and the P well, and the other part of the second P-type ion injection layer is located in the N well;
the first N-type ion injection layer, the first P-type ion injection layer and the first grid electrode are provided with a first connecting structure for connecting the first N-type ion injection layer, the first P-type ion injection layer and the first grid electrode, and the first connecting structure is used for leading out an anode;
the P trap is provided with third shallow trench isolation and fourth shallow trench isolation which are sequentially distributed at intervals, a third P-type ion injection layer is formed between the third shallow trench isolation and the fourth shallow trench isolation, a second grid electrode, a second N-type ion injection layer and a third N-type ion injection layer are formed on one side, far away from the third P-type ion injection layer, of the third shallow trench isolation, the second N-type ion injection layer and the third N-type ion injection layer are respectively arranged on two sides of the second grid electrode, one part of the second N-type ion injection layer stretches across the junction of the N trap and the P trap, and the other part of the second N-type ion injection layer is located in the P trap;
a fifth shallow trench isolation is arranged between the second P-type ion implantation layer and the second N-type ion implantation layer;
and a second connecting structure for connecting the second grid electrode, the third N-type ion injection layer and the third P-type ion injection layer is arranged on the second grid electrode, the third N-type ion injection layer and the third P-type ion injection layer and used for leading out a cathode.
Preferably, the P-type substrate is a silicon substrate.
Preferably, the second P-type ion implantation layer and the second N-type ion implantation layer have equal areas on the N-well and the P-well.
Preferably, the second P-type ion implantation layer and the second N-type ion implantation layer are symmetrical L-shaped structures.
Preferably, the ions doped in the N trap are boron ions.
Preferably, the ions doped in the P-well are phosphorous ions.
Preferably, ions doped in the first N-type ion implantation layer, the second N-type ion implantation layer and the third N-type ion implantation layer are arsenic ions.
Preferably, the ions doped in the first P-type ion implantation layer, the second P-type ion implantation layer and the third P-type ion implantation layer are all boron ions.
Preferably, the material of the gate is doped polysilicon.
As described above, the scr structure with adjustable high sustain voltage and low trigger voltage according to the present invention has the following advantages:
the silicon controlled rectifier structure with the adjustable holding voltage can reduce the trigger voltage through two trigger points of GGNMOS or GDPMOS; after the GGNMOS and the GDPMOS are conducted, the GGNMOS and the GDPMOS can be used as a current release path to shunt ESD current, so that the ESD current in an SCR body is reduced, and the holding voltage is improved; the trigger voltage can be adjusted by adjusting the structure of GGNMOS or GDPMOS; meanwhile, the GGNMOS and GDPMOS structures can be changed respectively or simultaneously to set the surface shunt magnitude, so that the purpose of regulating and controlling the holding voltage is achieved.
Drawings
FIG. 1 is a schematic diagram of a three-dimensional structure of a SCR according to the present invention;
FIG. 2 is a cross-sectional view of a silicon controlled rectifier A with a low capacitance electrostatic current path according to the present invention;
FIG. 3 is a cross-sectional view of a silicon controlled rectifier structure B and a low-capacitance electrostatic current path according to the present invention.
Reference numerals:
p-type substrate-01
N well-02
P-well-03
First shallow trench isolation-04
Second shallow trench isolation-05
First grid-06
Third shallow trench isolation-07
Fourth shallow trench isolation-08
First N-type ion implantation layer-09
First P-type ion implantation layer-10
Second P-type ion implantation layer-11
Second N-type ion implantation layer-12
Grid-13
Third N-type ion-implanted layer-14
Third P-type ion implantation layer-15
First connecting Structure-16
Second connecting Structure-17
Fifth shallow trench isolation-18
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Referring to fig. 1, the present invention provides a silicon controlled rectifier structure with adjustable high sustain voltage and low trigger voltage, comprising:
an N well 02 and a P well 03 which are adjacent to each other are formed on a P-type substrate 01 and a P-type substrate-01;
in the embodiment of the invention, the P-type substrate 01 is a silicon substrate, and the N-well 02 and the P-well 03 can be formed on the silicon substrate by ion implantation, then a groove for forming Shallow Trench Isolation (STI) is formed on the substrate by photolithography and etching, and then a shallow trench isolation structure is formed in the groove by depositing an insulating material and grinding.
The N well 02 is provided with first shallow trench isolations 04 and second shallow trench isolations 05 which are sequentially distributed at intervals, the shallow trench isolations are usually made of insulating materials such as silicon dioxide, a first N-type ion injection layer 09 is formed between the first shallow trench isolations 04 and the second shallow trench isolations 05, a first grid 06, a first P-type ion injection layer 10 and a second P-type ion injection layer 11 are formed on one side of the second shallow trench isolations 05 far away from the first N-type ion injection layer 09, the first P-type ion injection layer and the second P-type ion injection layer are respectively arranged on two sides of the first grid 06, one part of the second P-type ion injection layer 11 crosses the junction of the N well 02 and the P well 03, and the other part of the second P-type ion injection layer 11 is positioned on the N well 02;
the first N-type ion implantation layer 09, the first P-type ion implantation layer 10 and the first grid electrode 06 are provided with a first connecting structure 16 for connecting the first N-type ion implantation layer, the first P-type ion implantation layer and the first grid electrode, and the first connecting structure is used for leading out an anode;
in the embodiment of the present invention, after the device fabrication is completed in the front-end process, the interconnection between the devices is performed in the back-end process to form the first connection structure 16. Specifically, a layer of interlayer dielectric layer can be formed on the device after ion implantation is completed through chemical vapor deposition, the material of the interlayer dielectric layer can adopt silicon dioxide, then the interlayer dielectric layer is etched to form a contact hole communicated with the first N-type ion implantation layer 09, the first P-type ion implantation layer 10 and the first grid 06, then the contact hole is filled with a conductive material, the filling material adopts tungsten (W), and the interconnection adopts Al.
A third shallow trench isolation 07 and a fourth shallow trench isolation 08 which are sequentially distributed at intervals are arranged on the P-well 03, a third P-type ion injection layer 15 is formed between the third shallow trench isolation 07 and the fourth shallow trench isolation 08, a second grid 13, a second N-type ion injection layer 12 and a third N-type ion injection layer 14 which are respectively arranged on two sides of the second grid 13 are formed on one side, far away from the third P-type ion injection layer 15, of the third shallow trench isolation 07, one part of the second N-type ion injection layer 12 stretches across the junction of the N-well 02 and the P-well 03, and the other part of the second N-type ion injection layer 12 is located on the P-well 03;
a fifth shallow trench isolation 18 is arranged between the second P-type ion implantation layer 11 and the second N-type ion implantation layer 12;
in the embodiment of the present invention, the areas of the second P-type ion implantation layer 11 and the second N-type ion implantation layer 12 on the N-well 02 and the P-well 03 are equal.
In the embodiment of the present invention, the second P-type ion implantation layer 11 and the second N-type ion implantation layer 12 are symmetrical L-shaped structures.
A second connecting structure 17 for connecting the second grid electrode 13, the third N-type ion implantation layer 14 and the third P-type ion implantation layer 15 is arranged on the second grid electrode 13, the third N-type ion implantation layer 14 and the third P-type ion implantation layer 15 and is used for leading out a cathode;
in the embodiment of the present invention, after the front-end process completes the device fabrication, the interconnection between the devices is performed through the back-end process to form the second connection structure 17. Specifically, an interlayer dielectric layer may be formed by chemical vapor deposition on the device after ion implantation is completed, the interlayer dielectric layer may be made of silicon dioxide, then the interlayer dielectric layer is etched to form contact holes communicated with the second gate 13, the third N-type ion implantation layer 14 and the third P-type ion implantation layer 15, then the contact holes are filled with a conductive material, the filling material is tungsten (W), and the interconnection is made of Al.
Referring to fig. 2, in an embodiment of the present invention, the structure at the a-plane forms a structure similar to the conventional PLVTSCR structure and ESD current path.
Referring to fig. 3, in the embodiment of the present invention, the structure at the B-plane is formed similar to the conventional NLVTSCR structure and ESD current path.
That is to say, in the embodiment of the present invention, a GGNMOS is introduced into an SCR structure, and an LVTSCR including the GGNMOS is designed; GDPMOS is introduced into the traditional SCR structure, and LVTSCR containing the GDPMOS is designed; the GGNMOS and the GDPMOS are embedded into the LVTSCR, and a source electrode region of the GDPMOS and a drain electrode region of the GGNMOS respectively cross a boundary of Nwell and Pwell in half to design the LVTSCR structure.
In an embodiment of the present invention, the ions doped in the N-well 02 are boron ions.
In the embodiment of the present invention, the ions doped in the P-well 03 are phosphorus ions.
In the embodiment of the present invention, the ions doped in the first N-type ion implantation layer 09, the second N-type ion implantation layer 12 and the third N-type ion implantation layer 14 are arsenic ions.
In the embodiment of the present invention, the ions doped in the first P-type ion implantation layer 10, the second P-type ion implantation layer 11, and the third P-type ion implantation layer 15 are all boron ions.
In the embodiment of the invention, the material of the gate is doped polysilicon.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
In summary, the scr structure of the invention can reduce the trigger voltage through two trigger points, i.e. GGNMOS or GDPMOS; after the GGNMOS and the GDPMOS are conducted, the GGNMOS and the GDPMOS can be used as a current release path to shunt ESD current, so that the ESD current in an SCR body is reduced, and the holding voltage is improved; the trigger voltage can be adjusted by adjusting the structure of the GGNMOS or the GDPMOS; meanwhile, the GGNMOS and GDPMOS structures can be changed respectively or simultaneously to set the surface shunt magnitude, so that the purpose of regulating and controlling the holding voltage is achieved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Those skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (9)
1. A SCR structure with adjustable high holding voltage and low trigger voltage is characterized by comprising:
the semiconductor device comprises a P-type substrate, wherein an N well and a P well which are adjacent to each other are formed on the P-type substrate;
the N well is provided with first shallow trench isolations and second shallow trench isolations which are sequentially distributed at intervals, a first N-type ion injection layer is formed between the first shallow trench isolations and the second shallow trench isolations, one side of the second shallow trench isolations, which is far away from the first N-type ion injection layer, is provided with a first grid electrode, and a first P-type ion injection layer and a second P-type ion injection layer which are respectively arranged at two sides of the first grid electrode, one part of the second P-type ion injection layer crosses over the junction of the N well and the P well, and the other part of the second P-type ion injection layer is positioned in the N well;
the first N-type ion injection layer, the first P-type ion injection layer and the first grid electrode are provided with a first connecting structure for connecting the first N-type ion injection layer, the first P-type ion injection layer and the first grid electrode, and the first connecting structure is used for leading out an anode;
the P trap is provided with third shallow trench isolation and fourth shallow trench isolation which are sequentially distributed at intervals, a third P-type ion injection layer is formed between the third shallow trench isolation and the fourth shallow trench isolation, a second grid electrode, a second N-type ion injection layer and a third N-type ion injection layer are formed on one side, far away from the third P-type ion injection layer, of the third shallow trench isolation, the second N-type ion injection layer and the third N-type ion injection layer are respectively arranged on two sides of the second grid electrode, one part of the second N-type ion injection layer stretches across the junction of the N trap and the P trap, and the other part of the second N-type ion injection layer is located in the P trap;
a fifth shallow trench isolation is arranged between the second P-type ion implantation layer and the second N-type ion implantation layer;
and a second connecting structure for connecting the second grid electrode, the third N-type ion injection layer and the third P-type ion injection layer is arranged on the second grid electrode, the third N-type ion injection layer and the third P-type ion injection layer and is used for leading out a cathode.
2. The scr structure of claim 1, wherein: the P-type substrate is a silicon substrate.
3. The scr structure of claim 1, wherein: the second P-type ion injection layer and the second N-type ion injection layer are located on the N well and the P well and have the same area.
4. The SCR structure of claim 1, wherein: the second P-type ion implantation layer and the second N-type ion implantation layer are of symmetrical L-shaped structures.
5. The scr structure of claim 1, wherein: and the ions doped in the N trap are boron ions.
6. The scr structure of claim 1, wherein: and the ions doped in the P trap are phosphorus ions.
7. The scr structure of claim 1, wherein: and the ions doped in the first N-type ion implantation layer, the second N-type ion implantation layer and the third N-type ion implantation layer are arsenic ions.
8. The scr structure of claim 1, wherein: and ions doped in the first P-type ion implantation layer, the second P-type ion implantation layer and the third P-type ion implantation layer are boron ions.
9. The scr structure of claim 1, wherein: the first grid electrode and the second grid electrode are made of doped polysilicon.
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| CN202210669459.5A CN115274841A (en) | 2022-06-14 | 2022-06-14 | Silicon controlled rectifier structure capable of adjusting high maintaining voltage and low trigger voltage |
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| CN202210669459.5A CN115274841A (en) | 2022-06-14 | 2022-06-14 | Silicon controlled rectifier structure capable of adjusting high maintaining voltage and low trigger voltage |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116314277A (en) * | 2023-05-15 | 2023-06-23 | 微龛(广州)半导体有限公司 | SCR (selective catalytic reduction) type ESD (electro-static discharge) protection device, electronic device and preparation method |
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2022
- 2022-06-14 CN CN202210669459.5A patent/CN115274841A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116314277A (en) * | 2023-05-15 | 2023-06-23 | 微龛(广州)半导体有限公司 | SCR (selective catalytic reduction) type ESD (electro-static discharge) protection device, electronic device and preparation method |
| CN116314277B (en) * | 2023-05-15 | 2023-08-22 | 微龛(广州)半导体有限公司 | SCR (selective catalytic reduction) type ESD (electro-static discharge) protection device, electronic device and preparation method |
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