CN109861076A - A kind of picosecond pulse generating circuit for semiconductor laser - Google Patents
A kind of picosecond pulse generating circuit for semiconductor laser Download PDFInfo
- Publication number
- CN109861076A CN109861076A CN201910051936.XA CN201910051936A CN109861076A CN 109861076 A CN109861076 A CN 109861076A CN 201910051936 A CN201910051936 A CN 201910051936A CN 109861076 A CN109861076 A CN 109861076A
- Authority
- CN
- China
- Prior art keywords
- phase inverter
- pulse
- capacitor
- potentiometer
- varactor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Lasers (AREA)
- Pulse Circuits (AREA)
Abstract
The invention discloses a kind of picosecond pulse generating circuit for semiconductor laser, including trigger signal module and CMOS pulse generation module, the trigger signal module connects CMOS pulse generation module, and CMOS pulse generation module generates pulse output.The present invention, which is utilized, inputs the relationship competed between output with door, to generate a short pulse.The amplitude and pulsewidth of pulse can be controlled by adjusting the bias size of varactor and MOSFET.Pulsewidth be can produce in 80ps-270ns range, amplitude is up to the electric impulse signal of 1.8V.The driving applied to semiconductor laser that can be convenient.
Description
Technical field
The present invention relates to electronic technology field more particularly to a kind of picosecond pulse generation electricity for semiconductor laser
Road.
Background technique
In modern science and technology, what semiconductor laser had developed reaches its maturity, and in semiconductor laser master among these
Will be based on pulsed laser, it is small in size, the service life is long, and the mode of simple Injection Current can be used to pump its work
Voltage and current is compatible with integrated circuit, thus can single-chip integration therewith.And electric current can also be directly carried out with different frequency
Modulation is to obtain the pulsed laser output that different frequency is modulated.It is in laser communication, optical storage, optical circulator, laser printing, ranging
And radar etc. has been obtained for being widely applied.Therefore the pulse generating circuit for developing continuously adjustable frequency has very
Important meaning.
Currently, two kinds of most important electric pulse producing methods are as follows: MOS transistor device, solid state microwave device such as avalanche transistor
Deng.For MOS transistor device as switching device, the electric impulse signal of generation is more to be used in series to generate nanosecond high-voltage pulse,
It is not suitable for driving general semiconductor laser.The pulse power that solid state microwave device generally generates is larger, but pulsewidth is general
Nanosecond order and circuit it is complex, be not enough to drive out the picosecond even laser pulse of subpicosecond.Therefore, it is desirable to obtain
One pulsewidth is very narrow, and the considerable electric impulse signal of amplitude must just explore other pulse producing methods.
Summary of the invention
The purpose of the present invention is in view of the deficiencies of the prior art and provide a kind of picosecond for semiconductor laser
Pulse generating circuit.
Realizing the specific technical solution of the object of the invention is:
A kind of picosecond pulse generating circuit for semiconductor laser, the circuit include: trigger signal module and CMOS arteries and veins
Generation module is rushed, the trigger signal module connects CMOS pulse generation module, and CMOS pulse generation module generates pulse output；
Wherein: the trigger signal module includes crystal oscillator U1, potentiometer R1, resistance R2, capacitor C5, capacitor C6 and capacitor C7, power supply electricity
Pressure VCC is 3.3V, frequency 1.8MHZ, rising edge 1ns.The end VCC of the crystal oscillator U1 passes through three capacitor C5, electricity in parallel
Holding C6 and capacitor C7 and meets power supply VCC, the end GND ground connection, OUT terminal controls the amplitude of crystal oscillator output signal by connection potentiometer R1,
Output signal after adjusting is linked into junior CMOS pulse generation module, after resistance R2 is in parallel with the output end of trigger signal module
It has been grounded current-limiting protection effect；
The CMOS pulse generation module include CMOS pulse generate chip Pulse_G, potentiometer R3, potentiometer R4, capacitor C7,
Capacitor C8 and capacitor C9, wherein CMOS pulse generation chip Pulse_G possesses several pins and respectively corresponds: foot 0 is Vss termination
Ground；Foot 1 is the trigger signal that IN terminates the output of prime trigger module；Foot 2 is TB control termination potentiometer R3 live end, potentiometer
The left and right ends R3 one terminate power vd D, one end ground connection；Foot 3 is that OUT terminal is pulse signal output end, and foot 4 is PAD_VDD termination
Power vd D；Foot 5 meets power vd D by shunt capacitance C8, capacitor C9 and capacitor C10 for the end CORE_VDD；Foot 6 is TA control terminal
Potentiometer R4 live end is connect, the left and right ends potentiometer R4 one terminate power vd D, one end ground connection；Wherein potentiometer R3 and R4 pass through
Resistance sizes are controlled to control the input voltage of TA and TB.
The CMOS pulse generate chip Pulse_G include three phase inverter B1 in piece, phase inverter B2, phase inverter B3,
MOSFET pipe M1, MOSFET pipe M2, MOSFET pipe M3, varactor C1, varactor C2, varactor C3, varactor C4 and with door T1,
Wherein, each phase inverter is made of PMOS and NMOS, and the pole G of PMOS and NMOS are connected to the input of phase inverter
End, the pole D of the NMOS of the pole S one of PMOS is connected to output end；Three phase inverters successively according to the output end of phase inverter B1 with
The input terminal of phase inverter B2 connects, and the mode that the output end of phase inverter B2 is connect with the input terminal of phase inverter B3 cascades, wherein instead
The input terminal of phase device B1 connects trigger signal, the input terminal A of the output end connection and door T1 of phase inverter B3；Three phase inverter B1,
The pole D of the PMOS tube of phase inverter B2, phase inverter B3 is connected in parallel power vd D, phase inverter B1, phase inverter B2, phase inverter B3
The pole S of NMOS tube is coupled in parallel to TA after successively connecting with the pole D of MOSFET pipe M1, MOSFET pipe M2, MOSFET pipe M3；Transfiguration
Pipe C1, varactor C2, varactor C3, varactor C4 one end be successively connected in parallel on phase inverter B1, phase inverter B2, phase inverter B3, with
The output end of door T1, the other end are parallel to TB；Trigger signal is connect with the input terminal B of door T1.
Beneficial effects of the present invention:
The present invention takes full advantage of integrated circuit technique the most advanced instantly, based on input output gate in Digital Logical Circuits it
Between competition-venture relationship generate a spike, utilize the delay time of CMOS inverter and CMOS supply voltage difference
The trigger signal of output pulse width and amplitude as semiconductor laser is controlled, it is great to have application prospect.
Detailed description of the invention
Fig. 1 is structure of the invention figure；
Fig. 2 is that CMOS pulse of the present invention generates chip Pulse_G circuit diagram；
Fig. 3 is the logic schematic diagram of CMOS pulse generating circuit of the present invention.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, in the following with reference to the drawings and specific embodiments,
The present invention is described in more detail.
The present invention generates ultrashort picosecond using trigger signal circuit and the CMOS pulse generating circuit based on 40nm technique
Pulse signal is suitable for the driving application of semiconductor laser.
Embodiment
It refering to fig. 1, is structure of the invention figure, the present invention includes two modules, and in figure, the left side is data triggering signals mould
Block, the right are pulse generating modules.There is source crystal oscillator U1 to generate square wave trigger signal defeated as the data of CMOS pulse generating module
Enter, the pulse signal that amplitude and pulse width are continuously adjusted, the amplitude and arteries and veins of signal are finally generated by CMOS pulse generating module
Width can be adjusted by TA and TB.
Each component part of the present embodiment is described in detail individually below.
Trigger signal module
In the present embodiment, trigger signal module is a square-wave signal generation circuit, and which includes source crystal oscillator U1 and potentiometers
R1 has output end access the potentiometer R1, potentiometer R1 of source crystal oscillator U1 to adjust the amplitude of square-wave signal, has source crystal oscillator U1 to generate solid
The square-wave signal for determining frequency generates amplitude 1.7V, the square-wave signal of repetition rate 1.8MHz, square wave rising edge by potentiometer R1
About 1ns.R2 is current-limiting resistance ground connection.
CMOS pulse generation module
Refering to fig. 1, right-hand component is CMOS pulse generation module, which includes: CMOS pulse generation designed by the present invention
Circuit chip Pulse_G, potentiometer R3 and R4, capacitor C7, C8, C9.Wherein the foot 0 of chip Pulse_G is the end VSS ground connection, core
The foot 1 of piece Pulse_G is the square wave data-signal that IN terminates that prime trigger signal module generates, and the foot 2 of chip Pulse_G is TB
Input connects potentiometer R4 live end, and the left and right ends R4 one terminate power vd D, one end ground connection；The foot 3 of chip Pulse_G is OUT terminal
Connect the output of pulse signal；The foot 4 of chip Pulse_G meets VDD；The foot 5 of chip Pulse_G is that the end CORE_VDD passes through electricity in parallel
Hold C8, C9, C10 and meet power vd D, the foot 6 of chip Pulse_G is TA input, connects potentiometer R3 live end, one section of the left and right ends R3
Connect power vd D, one end ground connection.Wherein potentiometer R3 and R4 controls the input voltage of TA and TB by control resistance sizes.
Referring to Fig.2, CMOS pulse generates in chip Pulse_G circuit diagram, delay is formed by three phase inverters B1, B2, B3
The square-wave pulse signal of input after certain delay, is generated the wide arteries and veins that is same as being delayed using with door T1 by circuit
Rush waveform.The pulse width of produced waveform can be by adjusting the inclined of varactor C1-C4 and metal-oxide-semiconductor M1-M3 with shape
Pressure is to be controlled.Its principle logic chart contains two logics as shown in figure 3, can be seen that from simplified schematic diagram in Fig. 3
Module, a NOT gate and one and door.The two connection type is as shown in Figure 3.Circuit is closed using the competition between input output gate
System, to generate a short pulse.Input waveform has been divided into two paths of signals, follows different transmission paths respectively.The first via
Signal is directly connected to the input terminal with door, and second road signal is connected to the input terminal of NOT gate.The transmission delay introduced by NOT gate,
Cause to only have very small part with two input signals of door and intersect, thus generates a short pulse.Wherein, metal-oxide-semiconductor M1, M2,
M3 under TA voltage can the equivalent amplitude for controlling impulse waveform by the operating current size of control circuit at variable resistance and
Pulsewidth size.Varactor C1-C4 size is equivalent to tunable capacitor by controlling TB voltage to control phase inverter B1, B2, B3
Delay time and then the width and amplitude for controlling pulse.
The CMOS pulse generation module supply voltage VDD is 1.1V-2V.
In the present embodiment, 100 Ω of potentiometer R1 value, resistance R2 value 50 Ω, capacitor C5, C6, C7 difference value 10uF,
1uF、1nF。
Potentiometer R3 and R4 value is 100k Ω, and capacitor C8, C9, C10 distinguish value 10uF, 1uF, 1nF.
Supply voltage VCC is 3.3V, frequency 1.8MHz.
The course of work of the present embodiment is as follows:
Step 1: trigger signal module adjusts work by potentiometer R1 by the square wave data-signal for having source crystal oscillator to generate one
Voltage is 1.7V, and working frequency is the square wave data-signal of 1.8MHz；
Step 2: CMOS pulse generation module is directly inputted to the input terminal of T1 and door after the arrival of trigger data signal all the way,
Another way by B1, B2, B3 by reaching the input terminal with door T1 after certain delay, according to competing and emit in digital circuit
Danger, thus generating a spike signal with door；
Step 3: respectively adjust potentiometer R3 and R4 change respectively M1, M2, M3 equivalent variable resistance sizes and varactor C1,
The size of C2, C3, C4 change delay time and the operating current size of phase inverter so as to adjusting the pulsewidth of pulse signal
And amplitude；
Step 4: adjusting pulse generation module supply voltage VDD from 1.1V to 2V, the width and amplitude of pulse are adjusted.
Actual test shows the picosecond pulse signal that the present embodiment generates, and adjustable pulse width range is 80ps-270ns, arteries and veins
Rushing amplitude adjustable extent is 600mV-1.8V.Impulse waveform is stablized, and shakes very little, and adjustable accuracy is high.Therefore it is very suitable to half
The pulsed drive application of conductor laser.
So far, attached drawing is had been combined the present embodiment is described in detail.As described above, those skilled in the art
There should be clear understanding to the present invention.
In addition, the above-mentioned definition to each element and method be not limited in the various specific structures mentioned in embodiment,
Shape or mode, those of ordinary skill in the art simply can be changed or be replaced to it, such as:
(1) in the present embodiment, the chip technology used can also select other process to realize having a size of 40nm processing procedure
Chip circuit it is integrated；
(2) size of varactor can also be set according to specific requirement, so as to realize other parameters pulse signal.
In conclusion the present invention mainly generates square wave data-signal by using crystal oscillator, carried out by three phase inverters
Semiconductor laser, pulse signal are output to after generating a positive pulse signal wide with delay time with door after delay
Pulsewidth and amplitude can be controlled by adjusting the size of equivalent resistance, varactor and supply voltage, be shown experimentally that the hair
Bright impulse generator is satisfied with the pulsed drive demand of semiconductor laser.
Above-described embodiment is only a preferred embodiment of the invention, the substantial technological content model being not intended to limit the invention
It encloses.Although the invention is described in detail with reference to an embodiment, those skilled in the art should understand that, it is all in right
In the spirit and principles in the present invention defined by claim, modification, equivalent replacement, improvement etc. are made to the present invention, should all include
Within the scope of the present invention.
Claims (2)
1. a kind of picosecond pulse generating circuit for semiconductor laser, which is characterized in that the circuit includes: trigger signal
Module and CMOS pulse generation module, the trigger signal module connect CMOS pulse generation module, CMOS pulse generation module
Generate pulse output；Wherein: the trigger signal module include crystal oscillator U1, potentiometer R1, resistance R2, capacitor C5, capacitor C6 and
The end VCC of capacitor C7, the crystal oscillator U1 connect power supply VCC, GND termination by three capacitor C5, capacitor C6 and capacitor C7 in parallel
Ground, OUT terminal control the amplitude of crystal oscillator output signal by connection potentiometer R1, and the output signal after adjusting is linked into junior CMOS
Pulse generation module is grounded after resistance R2 is in parallel with the output end of trigger signal module；
The CMOS pulse generation module include CMOS pulse generate chip Pulse_G, potentiometer R3, potentiometer R4, capacitor C7,
Capacitor C8 and capacitor C9, wherein CMOS pulse generation chip Pulse_G possesses several pins and respectively corresponds: foot 0 is Vss termination
Ground；Foot 1 is the trigger signal that IN terminates the output of prime trigger module；Foot 2 is TB control termination potentiometer R3 live end, potentiometer
The left and right ends R3 one terminate power vd D, one end ground connection；Foot 3 is that OUT terminal is pulse signal output end, and foot 4 is PAD_VDD termination
Power vd D；Foot 5 meets power vd D by shunt capacitance C8, capacitor C9 and capacitor C10 for the end CORE_VDD；Foot 6 be TA control terminal,
Potentiometer R4 live end is connect, the left and right ends potentiometer R4 one terminate power vd D, one end ground connection.
2. picosecond pulse generating circuit according to claim 1, which is characterized in that the CMOS pulse generates chip
Pulse_G includes phase inverter B1, phase inverter B2, phase inverter B3, MOSFET pipe M1, MOSFET pipe M2, MOSFET pipe M3, varactor
C1, varactor C2, varactor C3, varactor C4 and with door T1, wherein each phase inverter is by PMOS and NMOS group
At the pole G of PMOS and NMOS are connected to the input terminal of phase inverter, and the pole D of the NMOS of the pole S one of PMOS is connected to output
End；Phase inverter is successively connect according to the output end of phase inverter B1 with the input terminal of phase inverter B2, the output end of phase inverter B2 and anti-
The input terminal connection type of phase device B3 cascades, and wherein the input terminal of phase inverter B1 connects trigger signal, the output end of phase inverter B3
The input terminal A of connection and door T1；The pole D of the PMOS tube of phase inverter B1, phase inverter B2, phase inverter B3 is connected in parallel power vd D, instead
The pole S of the NMOS tube of phase device B1, phase inverter B2, phase inverter B3 is successively with MOSFET pipe M1, MOSFET pipe M2, MOSFET pipe M3's
TA is coupled in parallel to after the connection of the pole D；Varactor C1, varactor C2, varactor C3, varactor C4 one end be successively connected in parallel on reverse phase
Device B1, phase inverter B2, phase inverter B3, with output end, the other end of door T1 it is parallel to TB；Triggering is connect with the input terminal B of door T1
Signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910051936.XA CN109861076B (en) | 2019-01-21 | 2019-01-21 | Picosecond-level pulse generation circuit for semiconductor laser |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910051936.XA CN109861076B (en) | 2019-01-21 | 2019-01-21 | Picosecond-level pulse generation circuit for semiconductor laser |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109861076A true CN109861076A (en) | 2019-06-07 |
| CN109861076B CN109861076B (en) | 2020-08-04 |
Family
ID=66895305
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910051936.XA Active CN109861076B (en) | 2019-01-21 | 2019-01-21 | Picosecond-level pulse generation circuit for semiconductor laser |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109861076B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102333195A (en) * | 2011-09-23 | 2012-01-25 | 东南大学 | Active and passive imaging readout circuit working at linear mode APD (Avalanche Photo Diode) array |
| US20150063419A1 (en) * | 2013-09-02 | 2015-03-05 | Renesas Electronics Corporation | Signal generation circuit and temperature sensor |
| CN106898946A (en) * | 2017-01-20 | 2017-06-27 | 华东师范大学 | For the turnable pulse width formula pulse generating circuit of semiconductor laser |
| CN207010539U (en) * | 2017-07-06 | 2018-02-13 | 深圳市华芯邦科技有限公司 | DC/DC switch converters power output transistor integrated drive electronics |
| CN107706737A (en) * | 2017-09-18 | 2018-02-16 | 华东师范大学 | A kind of accurate adjustable pulse generating circuit of frequency for semiconductor laser |
-
2019
- 2019-01-21 CN CN201910051936.XA patent/CN109861076B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102333195A (en) * | 2011-09-23 | 2012-01-25 | 东南大学 | Active and passive imaging readout circuit working at linear mode APD (Avalanche Photo Diode) array |
| US20150063419A1 (en) * | 2013-09-02 | 2015-03-05 | Renesas Electronics Corporation | Signal generation circuit and temperature sensor |
| CN106898946A (en) * | 2017-01-20 | 2017-06-27 | 华东师范大学 | For the turnable pulse width formula pulse generating circuit of semiconductor laser |
| CN207010539U (en) * | 2017-07-06 | 2018-02-13 | 深圳市华芯邦科技有限公司 | DC/DC switch converters power output transistor integrated drive electronics |
| CN107706737A (en) * | 2017-09-18 | 2018-02-16 | 华东师范大学 | A kind of accurate adjustable pulse generating circuit of frequency for semiconductor laser |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109861076B (en) | 2020-08-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104586435B (en) | Pulse bandwidth and amplitude adjustable broadband high-pressure narrow pulse system and pulse generating method | |
| CN104104362B (en) | High-amplitude picosecond balance pulse signal generator | |
| CN101588014A (en) | Narrow pulse high-current semiconductor laser device driving circuit | |
| CN111404515A (en) | Parameter-adjustable narrow pulse generation circuit | |
| CN106898946A (en) | For the turnable pulse width formula pulse generating circuit of semiconductor laser | |
| CN103905185A (en) | Pulse generator applied to distributing continuous variable quantum secret keys | |
| CN103326696A (en) | Ultra-wide band impulsator | |
| US8536929B2 (en) | High voltage switch with adjustable current | |
| CN109787614B (en) | Single pulse generating circuit and bidirectional level converting circuit | |
| US7990196B2 (en) | Signal driver with first pulse boost | |
| JP3055904B2 (en) | High voltage pulse generator | |
| US20030076136A1 (en) | Monocycle generator | |
| KR20060059896A (en) | Method of reducing the propagation delay and process and temperature effects on a buffer | |
| CN103066956A (en) | True random number random triangular wave generating method and device | |
| CN109861076A (en) | A kind of picosecond pulse generating circuit for semiconductor laser | |
| JPH04229713A (en) | Cmos circuit | |
| CN1691504B (en) | Impulse generation circuit | |
| CN208820751U (en) | A kind of narrow pulse generating circuit of low cost miniaturization | |
| CN101361410A (en) | High-frequency power supply circuit | |
| CN106533245A (en) | High-power pulse current generation circuit with external modulation function | |
| CN105743441B (en) | The adjustable rapid large-current pulse exciting circuit of slope in a kind of pulsewidth, amplitude and arteries and veins | |
| CN104836552A (en) | High-voltage spike pulse generating circuit | |
| US20060284664A1 (en) | Pulse generator and method for pulse generation thereof | |
| JP4412788B2 (en) | Parallel-serial conversion circuit | |
| CN204445946U (en) | The broadband high voltage narrow pulse system that pulsewidth amplitude is adjustable |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |