CN109787614B - Single pulse generating circuit and bidirectional level converting circuit - Google Patents
Single pulse generating circuit and bidirectional level converting circuit Download PDFInfo
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- CN109787614B CN109787614B CN201910114359.4A CN201910114359A CN109787614B CN 109787614 B CN109787614 B CN 109787614B CN 201910114359 A CN201910114359 A CN 201910114359A CN 109787614 B CN109787614 B CN 109787614B
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Abstract
The invention provides a single pulse generating circuit and a bidirectional level converting circuit, which comprise a first signal input end, a second signal input end, a port detecting module and a single pulse generating module; the port detection module is used for outputting a high level when at least one of the first signal input end and the second signal input end is at a low level, and outputting a low level when the first signal input end and the second signal input end are both at a high level, so that the output of the single pulse generation module is accelerated to turn to the high level; the single pulse generating module is used for outputting low-level pulses when any one of the first signal input end and the second signal input end is turned from low level to high level, so that the signal transmission speed can be increased, meanwhile, when the first signal input end and the second signal input end are turned to high level, the transmission power consumption is reduced, and meanwhile, the impedance matching performance and the signal integrity of the output port are ensured.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuits, and more particularly, to a single pulse generating circuit and a bidirectional level shifting circuit.
Background
Level shifting chips are one of the common chip types in integrated circuits and are widely used in data transmission, logic control, digital-to-analog conversion, and other systems. The level conversion chip is used for transmitting the logic level signal under the lower voltage domain at one end to the higher voltage domain at the other end, or transmitting the logic level signal under the higher voltage domain at one end to the lower voltage domain at the other end, and reducing transmission delay as much as possible in the transmission process, and simultaneously maintaining the integrity of the signal.
To reduce the delay of the level shifting, it is often necessary to add a fast pull-up tube at the output. In order to reduce the power consumption caused by the continuous conduction of the pull-up tube, a pull-up control module is generally used to control the on and off of the pull-up tube. The duration of the control pulse output by the existing pull-up control module is fixed, if one end of the pull-up control module is turned from a low level to a high level within the duration of the control pulse, the pull-up control module still continuously outputs the control pulse, which not only causes larger power consumption, but also damages the impedance matching property and the signal integrity of the output port.
Disclosure of Invention
In view of this, the present invention provides a single pulse generating circuit and a bidirectional level shifting circuit to solve the problems of large power consumption, and damage to the impedance matching and signal integrity of the output port of the existing pull-up control module.
In order to achieve the above purpose, the present invention provides the following technical solutions:
a single pulse generating circuit comprises a first signal input end, a second signal input end, a port detection module and a single pulse generating module;
the first input end of the port detection module is electrically connected with the first signal input end, the second input end of the port detection module is electrically connected with the second signal input end, the output end of the port detection module is electrically connected with the first input end of the single pulse generation module, the port detection module is used for outputting high level when at least one of the first signal input end and the second signal input end is low level, and outputting low level when the first signal input end and the second signal input end are both high level, so that the output of the single pulse generation module is accelerated to turn to high level;
the second input end of the single pulse generating module is electrically connected with the first signal input end, the third input end of the single pulse generating module is electrically connected with the second signal input end, and the single pulse generating module is used for outputting low-level pulses when any one of the first signal input end and the second signal input end is turned from low level to high level.
Optionally, the port detection module includes a nand gate and first to fourth inverters;
the input end of the first inverter is electrically connected with the first signal input end, the input end of the second inverter is electrically connected with the output end of the first inverter, and the output end of the second inverter is electrically connected with one input end of the NAND gate;
the input end of the third inverter is electrically connected with the second signal input end, the input end of the fourth inverter is electrically connected with the output end of the third inverter, and the output end of the fourth inverter is electrically connected with the other input end of the NAND gate;
the input end of the first inverter is electrically connected with the first input end of the port detection module, the input end of the third inverter is electrically connected with the second input end of the port detection module, and the output end of the NAND gate is electrically connected with the output end of the port detection module.
Optionally, the single pulse generating module includes first to third transistors, a first resistor, a second resistor, fifth to seventh inverters, a first nor gate, and a second nor gate;
one input end of the first NOR gate is electrically connected with the first signal input end, the other input end of the first NOR gate is electrically connected with the second signal input end, and the output end of the first NOR gate is electrically connected with the grid electrode of the first transistor;
the first end of the first transistor is electrically connected with a power supply end, the second end of the first transistor is electrically connected with one end of the first resistor, the other end of the first resistor is electrically connected with one end of the second resistor, the other end of the second resistor is electrically connected with the first end of the second transistor, the second end of the second transistor is electrically connected with a grounding end, and the grid electrode of the second transistor is electrically connected with the output end of the first NOR gate;
the grid electrode of the third transistor is electrically connected with the output end of the port detection module, the first end of the third transistor is electrically connected with one end of the first resistor, and the second end of the third transistor is electrically connected with the other end of the first resistor;
the input end of the fifth inverter is electrically connected with the other end of the second resistor, the output end of the fifth inverter is electrically connected with the input end of the sixth inverter, the output end of the sixth inverter is electrically connected with one input end of the second nor gate, the output end of the first nor gate is electrically connected with the other input end of the second nor gate, the output end of the second nor gate is electrically connected with the input end of the seventh inverter, and the output end of the seventh inverter is electrically connected with the output end of the single pulse generating module.
Optionally, the first transistor and the third transistor are PMOS transistors, and the second transistor is an NMOS transistor.
Optionally, the port detection module includes an and gate and first to fourth inverters;
the input end of the first inverter is electrically connected with the first signal input end, the input end of the second inverter is electrically connected with the output end of the first inverter, and the output end of the second inverter is electrically connected with one input end of the AND gate;
the input end of the third inverter is electrically connected with the second signal input end, the input end of the fourth inverter is electrically connected with the output end of the third inverter, and the output end of the fourth inverter is electrically connected with the other input end of the AND gate;
the input end of the first inverter is electrically connected with the first input end of the port detection module, the input end of the third inverter is electrically connected with the second input end of the port detection module, and the output end of the AND gate is electrically connected with the output end of the port detection module.
Optionally, the single pulse generating module includes first to third transistors, a first resistor, a second resistor, fifth to seventh inverters, a first nor gate, and a second nor gate;
one input end of the first NOR gate is electrically connected with the first signal input end, the other input end of the first NOR gate is electrically connected with the second signal input end, and the output end of the first NOR gate is electrically connected with the grid electrode of the first transistor;
the first end of the first transistor is electrically connected with a power supply end, the second end of the first transistor is electrically connected with one end of the first resistor, the other end of the first resistor is electrically connected with one end of the second resistor, the other end of the second resistor is electrically connected with the first end of the second transistor, the second end of the second transistor is electrically connected with a grounding end, and the grid electrode of the second transistor is electrically connected with the output end of the first NOR gate;
the grid electrode of the third transistor is electrically connected with the output end of the port detection module, the first end of the third transistor is electrically connected with one end of the second resistor, and the second end of the third transistor is electrically connected with the other end of the second resistor;
the input end of the fifth inverter is electrically connected with the other end of the second resistor, the output end of the fifth inverter is electrically connected with the input end of the sixth inverter, the output end of the sixth inverter is electrically connected with one input end of the second nor gate, the output end of the first nor gate is electrically connected with the other input end of the second nor gate, the output end of the second nor gate is electrically connected with the input end of the seventh inverter, and the output end of the seventh inverter is electrically connected with the output end of the single pulse generating module.
Optionally, the first transistor is a PMOS transistor, and the second transistor and the third transistor are NMOS transistors.
A bidirectional level conversion circuit comprising a signal transmission tube, a first pull-up tube, a second pull-up tube and a single pulse generation circuit, wherein the single pulse generation circuit is the single pulse generation circuit;
the first end of the first pull-up tube is electrically connected with a first voltage end, the second end of the first pull-up tube is electrically connected with the first end of the signal transmission tube, the first end of the second pull-up tube is electrically connected with a second voltage end, and the second end of the second pull-up tube is electrically connected with the second end of the signal transmission tube;
the first signal input end of the single pulse generating circuit is electrically connected with the first end of the signal transmission tube, the second signal input end of the single pulse generating circuit is electrically connected with the second end of the signal transmission tube, and the output end of the single pulse generating circuit is electrically connected with the grid electrodes of the first pull-up tube and the second pull-up tube.
Optionally, the first pull-up transistor and the second pull-up transistor are PMOS transistors.
Optionally, the circuit further comprises a driving circuit;
the driving circuit is used for controlling the signal transmission tube to be conducted when the two ends of the signal transmission tube are at low level.
Compared with the prior art, the technical scheme provided by the invention has the following advantages:
according to the single-pulse generating circuit and the bidirectional level converting circuit provided by the invention, when any one of the first signal input end and the second signal input end is turned from low level to high level, the single-pulse generating module outputs low-level pulses so as to control the pull-up tube to be conducted and accelerate the signal transmission speed; when both ends in the first signal input end and the second signal input end are turned to high level, the port detection module outputs low level, so that the output of the single pulse generation module is turned to high level from low level pulse to control the pull-up tube to be turned off, thereby reducing power consumption and ensuring impedance matching property and signal integrity of the output port.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a conventional level shift chip;
FIG. 2 is a schematic diagram of a control circuit shown in FIG. 1;
FIG. 3 is a schematic diagram of a single pulse generating circuit according to an embodiment of the present invention;
FIG. 4 is a signal timing diagram of a single pulse generating circuit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of another single pulse generating circuit according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a bidirectional level shifter circuit according to an embodiment of the present invention.
Detailed Description
As described in the background art, in the existing level shift chip, the pull-up control module may cause a larger power consumption of the chip. As shown in fig. 1, fig. 1 is a schematic structural diagram of a conventional level shift chip, when a first end a of a signal transmission end MN turns from a low level to a high level, a second control module controls a second pull-up tube MP2 to be turned on, and pulls a second end B of the signal transmission end MN from the low level to the high level; when the second end B of the signal transmission end MN turns from low level to high level, the first control module controls the first pull-up tube MP1 to be turned on, and pulls the first end a of the signal transmission end MN from low level to high level.
As shown in fig. 2, fig. 2 is a schematic structural diagram of a conventional control module, when the first end a or the second end B is turned from low level to high level, the node B1 generates a delay signal from high to low through a filter network formed by a resistor R0 and a capacitor C0, the node B2 and the node B1 are in-phase signals, and also generate a delay signal from high to low, so that for the and gate unit D1, a high level signal is output within a time delay t≡r0×c0, and therefore, the output terminal LOUT outputs a low level signal within a pulse width t, and the pull-up tube MP1 or MP2 is accelerated to open.
However, since the time of the low level signal is fixed, if the level of the pull-up port B or a is turned to a high level within the pulse width t in application, the control module does not recognize the port level and still keeps the strong pull-up state, so that the pull-up tube is continuously turned on, resulting in increased power consumption of the circuit and damage to the impedance matching and signal integrity of the output port.
Accordingly, the present invention provides a single pulse generating circuit, which overcomes the above-mentioned problems of the prior art, and includes a first signal input terminal, a second signal input terminal, a port detection module, and a single pulse generating module;
the first input end of the port detection module is electrically connected with the first signal input end, the second input end of the port detection module is electrically connected with the second signal input end, the output end of the port detection module is electrically connected with the first input end of the single pulse generation module, the port detection module is used for outputting high level when at least one of the first signal input end and the second signal input end is low level, and outputting low level when the first signal input end and the second signal input end are both high level, so that the output of the single pulse generation module is accelerated to turn to high level;
the second input end of the single pulse generating module is electrically connected with the first signal input end, the third input end of the single pulse generating module is electrically connected with the second signal input end, and the single pulse generating module is used for outputting low-level pulses when any one of the first signal input end and the second signal input end is turned from low level to high level.
According to the single pulse generating circuit provided by the invention, when any one of the first signal input end and the second signal input end is turned from low level to high level, the single pulse generating module outputs low level pulse to control the pull-up tube to be conducted, and when both ends of the first signal input end and the second signal input end are turned to high level, the port detecting module outputs low level, so that the output of the single pulse generating module is turned from low level pulse to high level to control the pull-up tube to be turned off, thereby reducing power consumption and ensuring impedance matching and signal integrity of the output port.
The foregoing is a core idea of the present invention, and in order that the above-mentioned objects, features and advantages of the present invention can be more clearly understood, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The embodiment of the invention provides a single pulse generating circuit, which is shown in fig. 3, and comprises a first signal input end LA, a second signal input end LB, a port detection module and a single pulse generating module;
the port detection module is used for outputting a low level when the first signal input end LA and the second signal input end LB are both in a high level, and outputting a high level when at least one of the first signal input end LA and the second signal input end LB is in a low level.
The second input end of the single pulse generating module is electrically connected with the first signal input end LA, the third input end of the single pulse generating module is electrically connected with the second signal input end LB, and the single pulse generating module is used for outputting low-level pulses when any one of the first signal input end LA and the second signal input end LB is turned from low level to high level. The single pulse generating module is also used for accelerating the inversion of the output from the low level pulse to the high level when the output of the port detecting module is inverted from the high level to the low level.
As shown in fig. 3, the port detection module includes a nand gate NA1 and first to fourth inverters NV1 to NV4; the input end of the first inverter NV1 is electrically connected with the first signal input end LA, the input end of the second inverter NV2 is electrically connected with the output end of the first inverter NV1, and the output end of the second inverter NV2 is electrically connected with one input end of the NAND gate NA 1; the input end of the third inverter NV3 is electrically connected with the second signal input end LB, the input end of the fourth inverter NV4 is electrically connected with the output end of the third inverter NV3, and the output end of the fourth inverter NV4 is electrically connected with the other input end of the NAND gate NA 1; the input end of the first inverter NV1 is electrically connected with the first input end of the port detection module, the input end of the third inverter NV3 is electrically connected with the second input end of the port detection module, and the output end of the nand gate NA1 is electrically connected with the output end A1 of the port detection module.
The single pulse generating module includes first to third transistors M1 to M3, a first resistor R1, a second resistor R2, fifth to seventh inverters NV5 to NV7, a first NOR gate NOR1, and a second NOR gate NOR2. One input end of the first NOR gate NOR1 is electrically connected with the first signal input end LA, the other input end of the first NOR gate NOR1 is electrically connected with the second signal input end LB, and an output end A2 of the first NOR gate NOR1 is electrically connected with a gate of the first transistor M1; the first end of the first transistor M1 is electrically connected with the power supply end VA, the second end of the first transistor M1 is electrically connected with one end of the first resistor R1, the other end of the first resistor R1 is electrically connected with one end of the second resistor R2, the other end of the second resistor R2 is electrically connected with the first end of the second transistor M2, the second end of the second transistor M2 is electrically connected with the grounding end GND, and the grid electrode of the second transistor M2 is electrically connected with the output end of the first NOR gate NOR 1; the grid electrode of the third transistor M3 is electrically connected with the output end A1 of the port detection module, the first end of the third transistor M3 is electrically connected with one end of the first resistor R1, and the second end of the third transistor M3 is electrically connected with the other end of the first resistor R1; the input end of the fifth inverter NV5 is electrically connected to the other end of the second resistor R2, the output end of the fifth inverter NV5 is electrically connected to the input end of the sixth inverter NV6, the output end of the sixth inverter NV6 is electrically connected to one input end of the second NOR gate NOR2, the output end of the first NOR gate NOR1 is electrically connected to the other input end of the second NOR gate NOR2, the output end of the second NOR gate NOR2 is electrically connected to the input end of the seventh inverter NV7, and the output end of the seventh inverter NV7 is electrically connected to the output end LOUT of the single pulse generating module.
The first transistor M1 and the third transistor M3 are PMOS transistors, and the second transistor M2 is an NMOS transistor. Of course, the present invention is not limited thereto, and in other embodiments, the first transistor M1 and the third transistor M3 may be NMOS transistors, and the second transistor M2 may be PMOS transistors.
Referring to fig. 3 and 4, when both the first signal input terminal LA and the second signal input terminal LB are at a high level, the output terminal A1 of the port detection circuit outputs a low level, the output terminal A2 of the first NOR gate NOR1 outputs a low level, the second transistor M2 is turned off, the first transistor M1 and the third transistor M3 are turned on, the nodes A3 and A4 are pulled up to a high level, and the output terminal LOUT outputs a high level.
When the first signal input terminal LA and the second signal input terminal LB are at low level, the output terminal A1 outputs a high level, the third transistor M3 is turned off, the output terminal A2 outputs a high level, so that the first transistor M1 is turned off, the second transistor M2 is turned on, the nodes A3 and A4 are pulled down to be at low level, and the output terminal LOUT outputs a high level.
When either one of the first signal input terminal LA and the second signal input terminal LB is turned from low to high, for example, when the first signal input terminal LA is turned from low to high, the output terminal A1 still outputs high, the third transistor M3 remains off, the output terminal A2 outputs low, such that the first transistor M1 is turned on, the second transistor M2 is turned off, the node A3 is turned from low to high, but, since the current is limited by the first resistor R1 and the second resistor R2 at this time, the node A3 is delayed, such that the node A4 is turned from low to high, and the output terminal LOUT outputs a low pulse for a certain period t. Where t= (r1+r2) C, C is the parasitic capacitance of node A3.
And, after time t, nodes A3 and A4 flip to high, and output LOUT outputs high. In addition, when the second terminal B connected to the second signal input terminal LB is pulled to a high level at t1, t1 is smaller than t, the output terminal A1 is turned to a low level, and the third transistor M3 is turned on, so that the current flowing through the first transistor M1 increases, and the output terminal LOUT is turned to a high level in advance, so that it is not necessary to wait for t-t1 time and then turn to a high level.
When the single-pulse generating circuit shown in fig. 3 is applied to the level converting circuit to control the pull-up tube, referring to fig. 6, the first signal input terminal LA is electrically connected with the first terminal a of the signal transmission tube, the second signal input terminal LB is electrically connected with the second terminal B of the signal input tube, when any one of the first terminal a and the second terminal B is turned from low level to high level, if the first terminal a is turned from low level to high level, the first signal input terminal LA is turned from low level to high level, the output terminal of the single-pulse generating module, i.e., the output terminal LOUT of the single-pulse generating circuit, outputs a low-level pulse for a certain period of time t, controls the pull-up tubes MP1 and MP2 to be turned on, pulls the other end, i.e., the second end B, to high level, and when the other end, i.e., the second end B is pulled up to high level, the port detecting module outputs a low level, so that the output terminal LOUT of the single-pulse generating circuit is turned to high level in advance, and controls the pull-up tubes MP1 and MP2 to be turned off, thereby reducing power consumption and guaranteeing impedance matching and signal integrity of the ports.
In another embodiment of the present invention, as shown in fig. 5, the port detection module includes an and gate NA2 and first to fourth inverters NV1 to NV4; the input end of the first inverter NV1 is electrically connected with the first signal input end LA, the input end of the second inverter NV2 is electrically connected with the output end of the first inverter NV1, and the output end of the second inverter NV2 is electrically connected with one input end of the AND gate NA 2; the input end of the third inverter NV3 is electrically connected with the second signal input end LB, the input end of the fourth inverter NV4 is electrically connected with the output end of the third inverter NV3, and the output end of the fourth inverter NV4 is electrically connected with the other input end of the AND gate NA 2; the input end of the first inverter NV1 is electrically connected with the first input end of the port detection module, the input end of the third inverter NV3 is electrically connected with the second input end of the port detection module, and the output end of the and gate NA2 is electrically connected with the output end A1 of the port detection module.
The single pulse generating module comprises a first transistor M1 to a third transistor M3, a first resistor R1, a second resistor R2, fifth to seventh inverters NV5 to NV7, a first NOR gate NOR1 and a second NOR gate NOR2; one input end of the first NOR gate NOR1 is electrically connected with the first signal input end LA, the other input end of the first NOR gate NOR1 is electrically connected with the second signal input end LB, and an output end A2 of the first NOR gate NOR1 is electrically connected with a gate of the first transistor M1; the first end of the first transistor M1 is electrically connected with the power supply end VA, the second end of the first transistor M1 is electrically connected with one end of the first resistor R1, the other end of the first resistor R1 is electrically connected with one end of the second resistor R2, the other end of the second resistor R2 is electrically connected with the first end of the second transistor M2, the second end of the second transistor M2 is electrically connected with the grounding end GND, and the grid electrode of the second transistor M2 is electrically connected with the output end of the first NOR gate NOR 1; the grid electrode of the third transistor M3 is electrically connected with the output end A1 of the port detection module, the first end of the third transistor M3 is electrically connected with one end of the second resistor R2, and the second end of the third transistor M3 is electrically connected with the other end of the second resistor R2; the input end of the fifth inverter NV5 is electrically connected to the other end of the second resistor R2, the output end of the fifth inverter NV5 is electrically connected to the input end of the sixth inverter NV6, the output end of the sixth inverter NV6 is electrically connected to one input end of the second NOR gate NOR2, the output end of the first NOR gate NOR1 is electrically connected to the other input end of the second NOR gate NOR2, the output end of the second NOR gate NOR2 is electrically connected to the input end of the seventh inverter NV7, and the output end of the seventh inverter NV7 is electrically connected to the output end LOUT of the single pulse generating module. The first transistor M1 is a PMOS transistor, and the second transistor M2 and the third transistor M3 are NMOS transistors.
When the first signal input terminal LA and the second signal input terminal LB are both at the high level, the output terminal A1 of the port detection circuit outputs the high level, the output terminal A2 of the first NOR gate NOR1 outputs the low level, the second transistor M2 is turned off, the first transistor M1 and the third transistor M3 are turned on, the nodes A3 and A4 are pulled up to the high level, and the output terminal LOUT outputs the high level.
When the first signal input terminal LA and the second signal input terminal LB are at low level, the output terminal A1 outputs low level, the third transistor M3 is turned off, the output terminal A2 outputs high level, so that the first transistor M1 is turned off, the second transistor M2 is turned on, the nodes A3 and A4 are pulled down to low level, and the output terminal LOUT outputs high level.
When either one of the first signal input terminal LA and the second signal input terminal LB is turned from low to high, for example, when the first signal input terminal LA is turned from low to high, the output terminal A1 still outputs low, the third transistor M3 remains off, the output terminal A2 outputs low, such that the first transistor M1 is turned on, the second transistor M2 is turned off, the node A3 is turned from low to high, but, since the current is limited by the first resistor R1 and the second resistor R2 at this time, the node A3 is delayed, such that the node A4 is turned from low to high, and the output terminal LOUT outputs a low pulse for a certain period t. Where t= (r1+r2) C, C is the parasitic capacitance of node A3.
And, after time t, nodes A3 and A4 flip to high, and output LOUT outputs high. In addition, when the second terminal B connected to the second signal input terminal LB is pulled to a high level at t1, t1 is smaller than t, the output terminal A1 is turned to a high level, and the third transistor M3 is turned on, so that the current flowing through the first transistor M1 increases, and the output terminal LOUT is turned to a high level in advance, so that it is not necessary to wait for t-t1 time and then turn to a high level.
When the single pulse generating circuit shown in fig. 5 is applied to the level converting circuit to control the pull-up tube, referring to fig. 6, the first signal input terminal LA is electrically connected with the first terminal a of the signal transmission tube, the second signal input terminal LB is electrically connected with the second terminal B of the signal input tube, when any one of the first terminal a and the second terminal B is turned from low level to high level, for example, when the second terminal B is turned from low level to high level, the second signal input terminal LB is turned from low level to high level, the output terminal of the single pulse generating module, i.e., the output terminal LOUT of the single pulse generating circuit, outputs a low level pulse for a certain period of time t, controls the pull-up tubes MP1 and MP2 to be turned on, pulls the other end, i.e., the first end a, to high level, and when the other end, i.e., the first end a is pulled up to high level, the port detecting module outputs a low level, so that the output terminal LOUT of the single pulse generating circuit is turned to high level in advance, controls the pull-up tubes MP1 and MP2 to be turned off, thereby reducing power consumption and guaranteeing impedance matching and signal integrity of the ports.
The embodiment of the invention also provides a bidirectional level conversion circuit, as shown in fig. 6, wherein the signal transmission tube, the first pull-up tube, the second pull-up tube and the single pulse generating circuit are provided by any embodiment;
the first end of the first pull-up tube is electrically connected with the first voltage end, the second end of the first pull-up tube is electrically connected with the first end of the signal transmission tube, the first end of the second pull-up tube is electrically connected with the second voltage end, and the second end of the second pull-up tube is electrically connected with the second end of the signal transmission tube; the first signal input end of the single pulse generating circuit is electrically connected with the first end of the signal transmission tube, the second signal input end of the single pulse generating circuit is electrically connected with the second end of the signal transmission tube, and the output end of the single pulse generating circuit is electrically connected with the grid electrodes of the first pull-up tube and the second pull-up tube.
When the first pull-up transistor MP1 and the second pull-up transistor MP2 are PMOS transistors, the first level is a low level, and when the first pull-up transistor MP1 and the second pull-up transistor MP2 are NMOS transistors, the first level is a high level. In the embodiment of the present invention, the first pull-up transistor MP1 and the second pull-up transistor MP2 are PMOS transistors and the signal transmission transistor MN is an NMOS transistor.
It should be noted that, as shown in fig. 6, the bidirectional level conversion circuit in the embodiment of the present invention further includes a driving circuit; the driving circuit is used for controlling the signal transmission tube MN to be conducted when the two ends of the signal transmission tube MN are at the first level. Specifically, when the signal transmission tube MN is an NMOS transistor, the driving circuit is configured to control the signal transmission tube MN to be turned on when both ends of the signal transmission tube MN are at a low level, and to control the signal transmission tube MN to be turned off when both ends of the signal transmission tube MN are at a high level.
That is, in the bidirectional level conversion circuit in the embodiment of the present invention, when both the first end a and the second end B are at a low level, the signal transmission tube MN is controlled to be turned on, so as to realize the transmission of two voltage domain signals, and when either the first end a or the second end B is at a high level, the first pull-up tube MP1 or the second pull-up tube MP2 is controlled to be turned on, so that the other end is pulled up to be at a high level, so as to realize the transmission of two voltage domain signals.
According to the single pulse generating circuit and the bidirectional level converting circuit provided by the invention, when any one of the first signal input end and the second signal input end is turned from low level to high level, the single pulse generating module outputs low level pulse to control the turn-on of the pull-up tube, and when both ends of the first signal input end and the second signal input end are turned to high level, the port detecting module outputs low level, so that the output of the single pulse generating module is turned from low level pulse to high level to control the turn-off of the pull-up tube, thereby reducing power consumption and ensuring impedance matching property and signal integrity of the output port. In addition, since the single pulse generating circuit provided by the embodiment of the invention does not need to integrate the delay capacitor C0, the area and the cost are reduced.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. The single pulse generating circuit is characterized by comprising a first signal input end, a second signal input end, a port detection module and a single pulse generating module;
the first input end of the port detection module is electrically connected with the first signal input end, the second input end of the port detection module is electrically connected with the second signal input end, the output end of the port detection module is electrically connected with the first input end of the single pulse generation module, the port detection module is used for outputting high level when at least one of the first signal input end and the second signal input end is low level, and outputting low level when the first signal input end and the second signal input end are both high level, so that the output of the single pulse generation module is accelerated to turn to high level;
the second input end of the single pulse generating module is electrically connected with the first signal input end, the third input end of the single pulse generating module is electrically connected with the second signal input end, and the single pulse generating module is used for outputting low-level pulses when any one of the first signal input end and the second signal input end is turned from low level to high level;
the single pulse generating module comprises first to third transistors, a first resistor, a second resistor, fifth to seventh inverters, a first nor gate and a second nor gate;
one input end of the first NOR gate is electrically connected with the first signal input end, the other input end of the first NOR gate is electrically connected with the second signal input end, and the output end of the first NOR gate is electrically connected with the grid electrode of the first transistor;
the first end of the first transistor is electrically connected with the power supply end, the second end of the first transistor is electrically connected with one end of the first resistor, the other end of the first resistor is electrically connected with one end of the second resistor, the other end of the second resistor is electrically connected with the first end of the second transistor, the second end of the second transistor is electrically connected with the grounding end, and the grid electrode of the second transistor is electrically connected with the output end of the first NOR gate;
the grid electrode of the third transistor is electrically connected with the output end of the port detection module, the first end of the third transistor is electrically connected with one end of the first resistor, and the second end of the third transistor is electrically connected with the other end of the first resistor; or, the first end of the third transistor is electrically connected with one end of the second resistor, and the second end of the third transistor is electrically connected with the other end of the second resistor;
the input end of the fifth inverter is electrically connected with the other end of the second resistor, the output end of the fifth inverter is electrically connected with the input end of the sixth inverter, the output end of the sixth inverter is electrically connected with one input end of the second nor gate, the output end of the first nor gate is electrically connected with the other input end of the second nor gate, the output end of the second nor gate is electrically connected with the input end of the seventh inverter, and the output end of the seventh inverter is electrically connected with the output end of the single pulse generating module.
2. The circuit of claim 1, wherein the port detection module comprises a nand gate and first through fourth inverters when a gate of the third transistor is electrically connected to an output terminal of the port detection module, a first terminal of the third transistor is electrically connected to one terminal of the first resistor, and a second terminal of the third transistor is electrically connected to the other terminal of the first resistor;
the input end of the first inverter is electrically connected with the first signal input end, the input end of the second inverter is electrically connected with the output end of the first inverter, and the output end of the second inverter is electrically connected with one input end of the NAND gate;
the input end of the third inverter is electrically connected with the second signal input end, the input end of the fourth inverter is electrically connected with the output end of the third inverter, and the output end of the fourth inverter is electrically connected with the other input end of the NAND gate;
the input end of the first inverter is electrically connected with the first input end of the port detection module, the input end of the third inverter is electrically connected with the second input end of the port detection module, and the output end of the NAND gate is electrically connected with the output end of the port detection module.
3. The circuit of claim 2, wherein the first transistor and the third transistor are PMOS transistors and the second transistor is an NMOS transistor.
4. The circuit of claim 1, wherein the port detection module comprises an and gate and first to fourth inverters when a gate of the third transistor is electrically connected to an output terminal of the port detection module, a first terminal of the third transistor is electrically connected to one terminal of the second resistor, and a second terminal of the third transistor is electrically connected to the other terminal of the second resistor;
the input end of the first inverter is electrically connected with the first signal input end, the input end of the second inverter is electrically connected with the output end of the first inverter, and the output end of the second inverter is electrically connected with one input end of the AND gate;
the input end of the third inverter is electrically connected with the second signal input end, the input end of the fourth inverter is electrically connected with the output end of the third inverter, and the output end of the fourth inverter is electrically connected with the other input end of the AND gate;
the input end of the first inverter is electrically connected with the first input end of the port detection module, the input end of the third inverter is electrically connected with the second input end of the port detection module, and the output end of the AND gate is electrically connected with the output end of the port detection module.
5. The circuit of claim 4, wherein the first transistor is a PMOS transistor and the second and third transistors are NMOS transistors.
6. A bidirectional level conversion circuit, comprising a signal transmission tube, a first pull-up tube, a second pull-up tube and a single pulse generating circuit, wherein the single pulse generating circuit is the single pulse generating circuit according to any one of claims 1 to 5;
the first end of the first pull-up tube is electrically connected with a first voltage end, the second end of the first pull-up tube is electrically connected with the first end of the signal transmission tube, the first end of the second pull-up tube is electrically connected with a second voltage end, and the second end of the second pull-up tube is electrically connected with the second end of the signal transmission tube;
the first signal input end of the single pulse generating circuit is electrically connected with the first end of the signal transmission tube, the second signal input end of the single pulse generating circuit is electrically connected with the second end of the signal transmission tube, and the output end of the single pulse generating circuit is electrically connected with the grid electrodes of the first pull-up tube and the second pull-up tube.
7. The circuit of claim 6, wherein the first pull-up tube and the second pull-up tube are PMOS transistors.
8. The circuit of claim 6, further comprising a drive circuit;
the driving circuit is used for controlling the signal transmission tube to be conducted when the two ends of the signal transmission tube are at low level.
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| CN113541912B (en) * | 2020-04-17 | 2022-11-01 | 苏州库瀚信息科技有限公司 | Data transmission device and method |
| CN111817705B (en) * | 2020-07-27 | 2021-11-09 | 中国电子科技集团公司第五十八研究所 | Self-induction self-acceleration bidirectional level conversion circuit |
| CN113611245B (en) * | 2021-08-17 | 2022-08-26 | 深圳市绿源半导体技术有限公司 | Bidirectional transmission device and control method |
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| CN104836552A (en) * | 2015-05-13 | 2015-08-12 | 中国电子科技集团公司第二十四研究所 | High-voltage spike pulse generating circuit |
| CN108566163A (en) * | 2018-06-22 | 2018-09-21 | 上海艾为电子技术股份有限公司 | A kind of pierce circuit |
| CN108768363A (en) * | 2018-08-24 | 2018-11-06 | 上海艾为电子技术股份有限公司 | A kind of tri-state Zero-cross comparator circuit and power management chip |
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2019
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104836552A (en) * | 2015-05-13 | 2015-08-12 | 中国电子科技集团公司第二十四研究所 | High-voltage spike pulse generating circuit |
| CN108566163A (en) * | 2018-06-22 | 2018-09-21 | 上海艾为电子技术股份有限公司 | A kind of pierce circuit |
| CN108768363A (en) * | 2018-08-24 | 2018-11-06 | 上海艾为电子技术股份有限公司 | A kind of tri-state Zero-cross comparator circuit and power management chip |
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