CN109861076B

CN109861076B - Picosecond-level pulse generation circuit for semiconductor laser

Info

Publication number: CN109861076B
Application number: CN201910051936.XA
Authority: CN
Inventors: 陈少强; 冉旭; 刁盛锡; 田赟鹏; 李鹏涛; 徐冬冬; 王亚斯
Original assignee: East China Normal University
Current assignee: East China Normal University
Priority date: 2019-01-21
Filing date: 2019-01-21
Publication date: 2020-08-04
Anticipated expiration: 2039-01-21
Also published as: CN109861076A

Abstract

The invention discloses a picosecond pulse generation circuit for a semiconductor laser, which comprises a trigger signal module and a CMOS pulse generation module, wherein the trigger signal module is connected with the CMOS pulse generation module, and the CMOS pulse generation module generates pulse output. The invention utilizes the competing relationship between the and gate input and output to produce a short pulse. The amplitude and pulse width of the pulse can be controlled by adjusting the bias voltage levels of the varactor and MOSFET. Can generate electric pulse signals with the pulse width ranging from 80ps to 270ns and the amplitude of up to 1.8V. The driving method can be conveniently applied to the driving of the semiconductor laser.

Description

Picosecond-level pulse generation circuit for semiconductor laser

Technical Field

The invention relates to the technical field of electronics, in particular to a picosecond pulse generation circuit for a semiconductor laser.

Background

Semiconductor lasers have been developed in modern technology, and among them, they are mainly pulsed lasers, which are small and long-lived, and can be pumped with their operating voltages and currents by simple injection of currents compatible with integrated circuits and thus monolithically integrated therewith. And may also be directly current modulated with different frequencies to obtain laser pulse outputs modulated at different frequencies. It has been widely used in laser communication, optical storage, optical gyro, laser printing, ranging, and radar. Therefore, the research of the pulse generating circuit with continuously adjustable frequency is of great significance.

Currently, the two most prominent ways of generating electrical pulses are: MOS device, microwave solid state device such as avalanche transistor, etc. The MOS tube device is used as a switch device, and the generated electric pulse signals are more used in series to generate nanosecond high-voltage pulses, so that the MOS tube device is not suitable for driving a common semiconductor laser. Microwave solid-state devices generally generate high pulse power, but the pulse width is generally in the order of nanoseconds and the circuit is complex, and thus, the microwave solid-state devices are not enough to drive picosecond-level or even subpicosecond laser pulses. Therefore, in order to obtain an electrical pulse signal with a narrow pulse width and a considerable amplitude, other pulse generation methods must be explored.

Disclosure of Invention

The invention aims to provide a picosecond pulse generation circuit for a semiconductor laser aiming at the defects of the prior art.

The specific technical scheme for realizing the purpose of the invention is as follows:

a picosecond pulser circuit for a semiconductor laser, comprising: the CMOS pulse generator comprises a trigger signal module and a CMOS pulse generation module, wherein the trigger signal module is connected with the CMOS pulse generation module, and the CMOS pulse generation module generates pulse output; wherein: the trigger signal module comprises a crystal oscillator U1, a potentiometer R1, a resistor R2, a capacitor C5, a capacitor C6 and a capacitor C7, the power supply voltage VCC is 3.3V, the frequency is 1.8MHZ, and the rising edge is 1 ns. The VCC end of the crystal oscillator U1 is connected with a power supply VCC through three capacitors C5, C6 and C7 which are connected in parallel, the GND end is grounded, the OUT end controls the amplitude of the output signal of the crystal oscillator through being connected with a potentiometer R1, the regulated output signal is connected to a lower-level CMOS pulse generation module, and a resistor R2 is connected with the output end of the trigger signal module in parallel and then grounded to play a role in current limiting protection;

the CMOS Pulse generation module comprises a CMOS Pulse generation chip Pulse _ G, a potentiometer R3, a potentiometer R4, a capacitor C7, a capacitor C8 and a capacitor C9, wherein the CMOS Pulse generation chip Pulse _ G is provided with a plurality of pins which correspond to the pins respectively: pin 0 is Vss terminal ground; pin 1 is IN end connected with the trigger signal output by the preceding stage trigger module; the pin 2 is an effective end of a TB control terminal potentiometer R3, one end of the left end and the right end of the potentiometer R3 is connected with a power supply VDD, and the other end is grounded; a pin 3 is an OUT end and a pulse signal output end, and a pin 4 is a PAD _ VDD end and a power supply VDD; a pin 5 is a CORE _ VDD end and is connected with a power supply VDD through a parallel capacitor C8, a capacitor C9 and a capacitor C10; the pin 6 is the effective end of a TA control terminal potentiometer R4, one end of the left end and the right end of the potentiometer R4 is connected with a power supply VDD, and the other end is grounded; wherein the potentiometers R3 and R4 control the input voltage of TA and TB by controlling the resistor size.

The CMOS Pulse generation chip Pulse _ G comprises three phase inverters B1, B2, B3, a MOSFET tube M1, a MOSFET tube M2, a MOSFET tube M3, a varactor tube C1, a varactor tube C2, a varactor tube C3, a varactor tube C4 and an AND gate T1 in a chip, wherein each phase inverter consists of a PMOS and an NMOS, the G poles of the PMOS and the NMOS are connected to serve as the input end of the phase inverter, and the S poles of the PMOS and the D pole of the NMOS are connected to serve as the output end; the three inverters are connected in series in a mode that the output end of the inverter B1 is connected with the input end of the inverter B2, the output end of the inverter B2 is connected with the input end of the inverter B3, the input end of the inverter B1 is connected with a trigger signal, and the output end of the inverter B3 is connected with the input end A of the AND gate T1; d poles of PMOS tubes of the three phase inverters B1, B2 and B3 are connected with a power supply VDD in parallel, and S poles of NMOS tubes of the phase inverters B1, B2 and B3 are connected with D poles of a MOSFET tube M1, a MOSFET tube M2 and a MOSFET tube M3 in sequence and then connected to TA in parallel; one end of a varactor C1, a varactor C2, a varactor C3 and a varactor C4 are connected in parallel to the output ends of a phase inverter B1, a phase inverter B2, a phase inverter B3 and an AND gate T1 in sequence, and the other end of the varactor C4 is connected in parallel to TB; the input terminal B of the and gate T1 is connected to the trigger signal.

The invention has the beneficial effects that:

the invention fully utilizes the most advanced integrated circuit technology at present, generates a spike pulse based on the competition-risk relationship between input and output gates in a digital logic circuit, respectively controls the output pulse width and amplitude as the trigger signal of the semiconductor laser by utilizing the delay time of a CMOS inverter and the CMOS power supply voltage, and has extremely wide application prospect.

Drawings

FIG. 1 is a block diagram of the present invention;

FIG. 2 is a circuit diagram of a CMOS Pulse generating chip Pulse _ G according to the present invention;

FIG. 3 is a logic diagram of the CMOS pulse generating circuit of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

The invention adopts the trigger signal circuit and the CMOS pulse generating circuit based on 40nm technology to generate ultrashort picosecond-level pulse signals, and is suitable for the driving application of the semiconductor laser.

Examples

Referring to fig. 1, which is a structural diagram of the present invention, the present invention includes two modules, in the drawing, a data trigger signal module is provided on the left side, and a pulse generation module is provided on the right side. The active crystal oscillator U1 generates a square wave trigger signal as the data input of the CMOS pulse generation module, and finally the CMOS pulse generation module generates a pulse signal with continuously adjustable amplitude and pulse width, and the amplitude and pulse width of the signal can be adjusted through TA and TB.

The respective components of the present embodiment will be described in detail below.

Trigger signal module

In this embodiment, the trigger signal module is a square wave signal generating circuit, which includes an active crystal oscillator U1 and a potentiometer R1, an output end of the active crystal oscillator U1 is connected to the potentiometer R1, the potentiometer R1 adjusts an amplitude of the square wave signal, the active crystal oscillator U1 generates a square wave signal with a fixed frequency, the potentiometer R1 generates a square wave signal with an amplitude of 1.7V and a repetition frequency of 1.8MHz, and a rising edge of the square wave is about 1 ns. R2 is a current limiting resistor grounded.

CMOS pulse generating module

Referring to fig. 1, the right portion is a CMOS pulse generation module, which includes: the CMOS Pulse generation circuit comprises a CMOS Pulse generation circuit chip Pulse _ G, potentiometers R3 and R4, capacitors C7, C8 and C9. Pin 0 of chip Pulse _ G is grounded at VSS end, pin 1 of chip Pulse _ G is IN end connected with square wave data signal generated by front stage trigger signal module, pin 2 of chip Pulse _ G is TB input end connected with effective end of potentiometer R4, one end of R4 is connected with power supply VDD, and the other end is grounded; a pin 3 of the chip Pulse _ G is an output of an OUT terminating Pulse signal; pin 4 of chip Pulse _ G is connected with VDD; the pin 5 of the chip Pulse _ G is a CORE _ VDD end and is connected with a power supply VDD through parallel capacitors C8, C9 and C10, the pin 6 of the chip Pulse _ G is a TA input and is connected with an effective end of a potentiometer R3, the left end and the right end of the R3 are connected with the power supply VDD, and one end of the R3 is grounded. Wherein the potentiometers R3 and R4 control the input voltage of TA and TB by controlling the resistor size.

Referring to fig. 2, in the circuit diagram of the CMOS Pulse generation chip Pulse _ G, a delay circuit is formed by three inverters B1, B2, and B3, and an input square wave Pulse signal is delayed by a certain time and then passes through an and gate T1 to generate a Pulse waveform with the same width as the delay. The pulse width and shape of the generated waveform can be controlled by adjusting the bias voltages of the varactors C1-C4 and MOS transistors M1-M3. The schematic logic diagram is shown in fig. 3, and it can be seen from the simplified schematic diagram that fig. 3 includes two logic blocks, a not gate and an and gate. The connection of the two is shown in figure 3. The circuit uses the competition between the input and output gates to generate a short pulse. The input waveform is divided into two signals, which follow different transmission paths. The first path of signal is directly connected to the input end of the AND gate, and the second path of signal is connected to the input end of the NOT gate. The propagation delay introduced by the not-gate results in only a small fraction of the two input signals to the and-gate crossing, thus generating a short pulse. The MOS tubes M1, M2 and M3 can be equivalent to variable resistors under the TA voltage, and the amplitude and the pulse width of the pulse waveform can be controlled by controlling the working current of the circuit. The size of the varactors C1-C4 is equivalent to an adjustable capacitor by controlling TB voltage, so that the delay time of the inverters B1, B2 and B3 is controlled, and the width and the amplitude of a pulse are controlled.

The power supply voltage VDD of the CMOS pulse generation module is 1.1V-2V.

In this embodiment, the potentiometer R1 takes a value of 100 Ω, the resistor R2 takes a value of 50 Ω, and the capacitors C5, C6, and C7 take values of 10uF, 1uF, and 1nF, respectively.

Potentiometers R3 and R4 take the value of 100k omega, and capacitors C8, C9 and C10 take the values of 10uF, 1uF and 1nF respectively.

The supply voltage VCC is 3.3V and the frequency is 1.8 MHz.

The working process of the embodiment is as follows:

step one, a trigger signal module generates a square wave data signal through an active crystal oscillator, and the square wave data signal with the working voltage of 1.7V and the working frequency of 1.8MHz is adjusted through a potentiometer R1;

after a trigger data signal arrives, one path of the CMOS pulse generation module is directly input to the input end of a T1 AND gate, and the other path of the CMOS pulse generation module reaches the input end of an AND gate T1 after certain delay through B1, B2 and B3, so that a spike pulse signal is generated in the AND gate according to competition and risk in a digital circuit;

step three, adjusting potentiometers R3 and R4 respectively to change the equivalent variable resistance of M1, M2 and M3 and the size of varactors C1, C2, C3 and C4 respectively to change the delay time and the working current of the inverter so as to adjust the pulse width and the amplitude of the pulse signal;

and step four, adjusting the power supply voltage VDD of the pulse generation module from 1.1V to 2V, and adjusting the width and amplitude of the pulse.

Practical tests show that the picosecond pulse signal generated by the embodiment has the adjustable range of the pulse width of 80ps-270ns and the adjustable range of the pulse amplitude of 600 mV-1.8V. The pulse waveform is stable, the jitter is very small, and the adjustable precision is high. And is therefore well suited for pulsed driving applications of semiconductor lasers.

Up to this point, the present embodiment has been described in detail with reference to the accompanying drawings. From the above description, those skilled in the art should clearly recognize the present invention.

Furthermore, the above definitions of the various elements and methods are not limited to the particular structures, shapes or arrangements of parts mentioned in the examples, which may be easily modified or substituted by one of ordinary skill in the art, for example:

(1) in this embodiment, the chip process size used is 40nm, and other process sizes may be selected to realize integration of the chip circuit;

(2) the size of the varactor can also be set according to specific requirements, so that other parameter pulse signals can be realized.

In summary, the invention mainly uses the crystal oscillator to generate the square wave data signal, generates a positive pulse signal with the same width as the delay time at the and gate after being delayed by the three inverters, and outputs the positive pulse signal to the semiconductor laser, the pulse width and the amplitude of the pulse signal can be controlled by adjusting the equivalent resistance, the varactor and the supply voltage, and experiments show that the pulse generator of the invention meets the pulse driving requirement of the semiconductor laser.

The above embodiment is merely a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been described in detail with reference to the embodiments, it should be understood by those skilled in the art that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A picosecond pulser circuit for a semiconductor laser, comprising: the CMOS pulse generator comprises a trigger signal module and a CMOS pulse generation module, wherein the trigger signal module is connected with the CMOS pulse generation module, and the CMOS pulse generation module generates pulse output; wherein: the trigger signal module comprises a crystal oscillator U1, a potentiometer R1, a resistor R2, a capacitor C5, a capacitor C6 and a capacitor C7, the VCC end of the crystal oscillator U1 is connected with a power VCC through three capacitors C5, a capacitor C6 and a capacitor C7 which are connected in parallel, the GND end is grounded, the OUT end controls the amplitude of an output signal of the crystal oscillator through being connected with the potentiometer R1, the regulated output signal is connected to the lower-level CMOS pulse generation module, and the resistor R2 is connected with the output end of the trigger signal module in parallel and then grounded;

the CMOS Pulse generation module comprises a CMOS Pulse generation chip Pulse _ G, a potentiometer R3, a potentiometer R4, a capacitor C7, a capacitor C8 and a capacitor C9, wherein the CMOS Pulse generation chip Pulse _ G is provided with a plurality of pins which correspond to the pins respectively: pin 0 is Vss terminal ground; pin 1 is IN end connected with the trigger signal output by the preceding stage trigger module; the pin 2 is an effective end of a TB control terminal potentiometer R3, one end of the left end and the right end of the potentiometer R3 is connected with a power supply VDD, and the other end is grounded; a pin 3 is an OUT end and a pulse signal output end, and a pin 4 is a PAD _ VDD end and a power supply VDD; a pin 5 is a CORE _ VDD end and is connected with a power supply VDD through a parallel capacitor C8, a capacitor C9 and a capacitor C10; pin 6 is a TA control end and is connected with an effective end of a potentiometer R4, one end of the left end and the right end of the potentiometer R4 is connected with a power supply VDD, and the other end is grounded; wherein:

the CMOS Pulse generation chip Pulse _ G comprises a phase inverter B1, a phase inverter B2, a phase inverter B3, a MOSFET tube M1, a MOSFET tube M2, a MOSFET tube M3, a varactor tube C1, a varactor tube C2, a varactor tube C3, a varactor tube C4 and an AND gate T1, wherein each phase inverter consists of a PMOS and an NMOS, the G poles of the PMOS and the NMOS are connected to serve as the input end of the phase inverter, and the S pole of the PMOS and the D pole of the NMOS are connected to serve as the output end; the inverter is connected with the input end of an inverter B2 according to the output end of an inverter B1 in sequence, the output end of an inverter B2 is connected with the input end of an inverter B3 in a cascade mode, the input end of the inverter B1 is connected with a trigger signal, and the output end of an inverter B3 is connected with the input end A of an AND gate T1; d poles of PMOS tubes of the phase inverter B1, the phase inverter B2 and the phase inverter B3 are connected with a power supply VDD in parallel, and S poles of NMOS tubes of the phase inverter B1, the phase inverter B2 and the phase inverter B3 are connected with D poles of a MOSFET tube M1, a MOSFET tube M2 and a MOSFET tube M3 in sequence and then connected to TA in parallel; one end of a varactor C1, a varactor C2, a varactor C3 and a varactor C4 are connected in parallel to the output ends of an inverter B1, an inverter B2, an inverter B3 and an AND gate T1 in sequence, and the other end of the varactor C4 is connected in parallel to a TB; the input terminal B of the and gate T1 is connected to the trigger signal.