Utility model content
The technical problems to be solved in the utility model is to avoid above-mentioned the deficiencies in the prior art part and propose one kind more
Simplified high-order N-type power transistor VThDrive circuit, can not only simplify in the prior art complicated bit level displacement
Circuit, circuit efficiency is improved, reduce circuit delay;And corresponding support circuit can be simplified.
The utility model solves the problems, such as that the technical scheme of above-mentioned technology is a kind of defeated for DC/DC switch converters power
Go out the integrated drive electronics of transistor driving, including the high-order driving prime buffering for high-order driving control signal input buffering
Device, the bootstrap capacitor elevated for signal potential, for the Capacitance Coupled drive circuit of signal coupling, for high-order buffered-display driver
Second phase inverter of signals reverse;High-order driving control signal is that the second pulse-width signal drives pre-stage buffer from a high position
Input terminal inputs;The high-order negative plate for driving the high-order buffered-display driver signal of pre-stage buffer output to bootstrap capacitor, at the same it is high
Position driving pre-stage buffer exports high-order buffered-display driver signal to the input terminal of the second phase inverter;The positive plate of bootstrap capacitor and
The first input end electrical connection of Capacitance Coupled drive circuit;The output end of second phase inverter and the of Capacitance Coupled drive circuit
Two input terminals electrically connect;3rd input terminal of Capacitance Coupled drive circuit is used to access outside 3rd external input power
3rd d. c. voltage signal;The first lead-out terminal of Capacitance Coupled drive circuit electrically connects with high-order N-type power transistor grid,
Second lead-out terminal of Capacitance Coupled drive circuit electrically connects with high-order N-type power transistor source electrode;Second phase inverter, bootstrapping electricity
Hold and Capacitance Coupled drive circuit cooperates, the signal potential of high-order buffered-display driver signal is raised, it is brilliant in high-order N-type electric power
After the conducting of body pipe, the first lead-out terminal of Capacitance Coupled drive circuit can be made persistently to provide the high-order N-type electric power crystalline substance of suitable potential
Body tube grid drive signal, i.e., high-order drive signal.
The Capacitance Coupled drive circuit includes first switch, second switch, the first coupled capacitor and the second N-type metal-oxide-semiconductor;
One end of second switch is used as the 3rd input terminal of Capacitance Coupled drive circuit, that is, accesses the 3rd of the 3rd external input power
D. c. voltage signal;The other end of second switch and one end electrical connection of first switch, while the other end of the second switch is also
The positive plate electrical connection of first input end as Capacitance Coupled drive circuit, the first input end and bootstrap capacitor, connects
Enter coupling drive circuit control signal;The other end of first switch is used as the first lead-out terminal of Capacitance Coupled drive circuit, defeated
Go out high-order N-type power transistor gate drive signal uGPTo the grid of high-order N-type power transistor;Meanwhile the first switch
The other end also electrically connects with the drain electrode of the second N-type metal-oxide-semiconductor;The first d. c. voltage signal of coupling drive circuit control signal and input
The switch of first switch described in co- controlling;The source electrode of second N-type metal-oxide-semiconductor is used as the second output end of Capacitance Coupled drive circuit
The sub source electrode with high-order N-type power transistor electrically connects;The grid of second N-type metal-oxide-semiconductor and one end of the first coupled capacitor are electrically connected
Connect;The other end of first coupled capacitor is used as the second input terminal of Capacitance Coupled drive circuit, and the output of the second phase inverter
End electrical connection;One end of second switch from bootstrap capacitor positive plate access coupling drive circuit control signal, second switch it is another
The 3rd d. c. voltage signal is accessed in one end, and coupling drive circuit control signal and the 3rd d. c. voltage signal co- controlling second are opened
The switch of pass.
The first switch is the first p-type metal-oxide-semiconductor, the leakage of the grid of the first p-type metal-oxide-semiconductor and high-order N-type power transistor
Pole electrically connects, and the drain electrode of the first p-type metal-oxide-semiconductor and the drain electrode of the second N-type metal-oxide-semiconductor electrically connect, and the source electrode of the first p-type metal-oxide-semiconductor is used as
The first input end of Capacitance Coupled drive circuit;
The source electrode of first p-type metal-oxide-semiconductor electrically connects with the positive plate of bootstrap capacitor, accesses coupling drive circuit control signal;
The grid of first p-type metal-oxide-semiconductor accesses the first d. c. voltage signal;Coupling drive circuit control signal and the first d. c. voltage signal
The on off state of co- controlling the first p-type metal-oxide-semiconductor.
The second switch is the first diode, and the positive pole the as Capacitance Coupled drive circuit the 3rd of the first diode is defeated
Enter terminal, access the 3rd d. c. voltage signal of the 3rd external input power;The negative pole and bootstrap capacitor of first diode are just
Pole plate electrical connection access coupling drive circuit control signal;Coupling drive circuit control signal and the 3rd d. c. voltage signal are common
Control the switch of the first diode.
The second switch includes the 4th N-type metal-oxide-semiconductor, the second coupled capacitor and the second diode, and the second diode is just
Pole is used as the 3rd input terminal of Capacitance Coupled drive circuit, accesses the 3rd d. c. voltage signal of the 3rd external input power;
Meanwhile second diode positive pole and the 4th N-type metal-oxide-semiconductor source electrode electrical connection;The negative pole of second diode and the 4th N-type MOS
The grid electrical connection of pipe;The grid of 4th N-type metal-oxide-semiconductor also electrically connects with one end of the second coupled capacitor;Second coupled capacitor
One end of the other end and the first coupled capacitor electrically connects, and the connection terminal is used as the second input of Capacitance Coupled drive circuit
The lead-out terminal electrical connection of son, the connection terminal and the second phase inverter;The drain electrode of 4th N-type metal-oxide-semiconductor drives as Capacitance Coupled
The first input end of circuit, and the positive plate electrical connection of bootstrap capacitor, access coupling drive circuit control signal;Coupling driving
The on off state of second switch described in circuit control signal and the 3rd d. c. voltage signal co- controlling.
The clamp circuit of gate source voltage control, the clamp circuit bag are provided between the grid and source electrode of second N-type metal-oxide-semiconductor
Include the first resistor and second resistance being connected between the grid and source electrode of the second N-type metal-oxide-semiconductor;The clamp circuit also includes setting
Put the 3rd N-type metal-oxide-semiconductor between the grid and source electrode of the second N-type metal-oxide-semiconductor;The drain electrode of 3rd N-type metal-oxide-semiconductor and the second N-type MOS
The source electrode electrical connection of the grid electrical connection of pipe, the source electrode of the 3rd N-type metal-oxide-semiconductor and the second N-type metal-oxide-semiconductor, the grid of the 3rd N-type metal-oxide-semiconductor
Pole while and first resistor and second resistance electrical connection.
The integrated drive electronics for the driving of DC/DC switch converters power output transistor, in addition to first is anti-
Phase device, low level driving control signal level displacement circuit and low level driving buffer;Low level driving control signal is the first pulsewidth
Modulated signal is " logic NOT " signal of the second pulse-width signal;Low level driving control signal is that the first pulse-width signal is defeated
Enter to low level driving control signal level displacement circuit to carry out the displacement of signal potential, by the pulse electricity of the first pulse-width signal
Position is transformed into the 4th d. c. voltage signal current potential of outside 4th external input power from the first input power high potential, while low
Position driving control signal level displacement circuit turns the space current potential of the first pulse-width signal from the first input power ground potential
Change to the source potential of low level N-type power transistor;Low level driving control signal level displacement circuit outputs signal to low level drive
Dynamic buffer, low level driving buffer exports low level drive signal to the grid of low level N-type power transistor, for low level N-type
The driving of power transistor;It is anti-phase to the first phase inverter, first that low level driving control signal is that the first pulse-width signal inputs
It is that the second pulse-width signal a to high position drives pre-stage buffer that device, which exports high-order driving control signal,.
The integrated drive electronics for the driving of DC/DC switch converters power output transistor, in addition to ZCD moulds
Block, for detecting the zero current cross of the i.e. high-order N-type power transistor of rectifying tube and/or low level N-type power transistor;When applying
The DC/DC switch converters of the integrated drive electronics, when being operated in BUCK patterns and being used as BUCK systems, the both ends of ZCD modules
Drain electrode with low level N-type power transistor and source electrode electrical connection respectively;Low level N-type power transistor is rectifying tube, then ZCD modules
The current signal between the drain electrode of low level N-type power transistor and the source electrode of low level N-type power transistor can be detected;
It is used as BOOST systems when being operated in BOOST patterns in the DC/DC switch converters for applying the integrated drive electronics
During system, the both ends drain electrode with high-order N-type power transistor and the source electrode electrical connection respectively of ZCD modules;High-order N-type power transistor
For rectifying tube, ZCD modules will be detected between the drain electrode of high-order N-type power transistor and the source electrode of high-order N-type power transistor
Between current signal;When being operated in BUCK-BOOST patterns in the DC/DC switch converters for applying the integrated drive electronics
When being used as BUCK-BOOST systems, the drain electrode with low level N-type power transistor and source electrode are electrically connected respectively at the both ends of ZCD modules
Connect;Low level N-type power transistor is rectifying tube, then ZCD modules can detect the drain electrode of low level N-type power transistor and low level N-type electricity
Current signal between the source electrode of power transistor.
The integrated drive electronics for the driving of DC/DC switch converters power output transistor also includes ring and eliminated
Module, the both ends of the both ends of ring cancellation module respectively with external inductors L1 electrically connect, for removing with DC/DC switch converters
Ring caused by the external inductors L1 self-oscillations of connection;When the DC/DC switching converter operations of the application integrated drive electronics
In dcm mode, and by ZCD modules to detect rectification tube current be zero when, now high-order N-type power transistor and low level N
When type power transistor is all closed, ring cancellation module is removed in external inductors L1 due to ring caused by self-oscillation.
The utility model solves the problems, such as that the technical scheme of above-mentioned technology can also be a kind of above-mentioned integrated drive electronics
DC/DC switch converters, including anti-ganged up for prevent that high-order N-type power transistor and low level N-type power transistor from ganging up
Circuit unit;It is anti-gang up circuit unit include the 3rd level displacement circuit, the 3rd phase inverter, first with door, the 4th phase inverter and
Second and door;Low level drive signal inputs from the input terminal of the 3rd level displacement circuit, the output of the 3rd level displacement circuit
Terminal electrically connects with the input terminal of the 3rd phase inverter, the lead-out terminal of the 3rd phase inverter and first with the first input end of door
Electrical connection, first is used to inputting low level driving control signal i.e. the first pulse-width signal with the second input terminal of door, and first
The first phase inverter is outputed signal to door;High-order buffered-display driver signal inputs from the input terminal of the 4th phase inverter, and the 4th is anti-phase
The lead-out terminal of device electrically connects with second with the first input end of door, and second is used to input low level with the second input terminal of door
Driving control signal is the first pulse-width signal, and second outputs signal to low level driving control signal level shift electricity with door
Road.
Compared with the existing technology compared with the beneficial effects of the utility model are:1st, a high position complicated in the prior art is simplified
Level displacement circuit, circuit efficiency is improved, reduce circuit delay;2nd, the drive circuit drives the electricity of buffering to high-order prime
Road requires lower so that high-order prime driving buffering need not be reduced the requirement to device, reduced collection using isolation class device
Into the area of circuit;3rd, to applying the DC/DC switch converters of the drive circuit, its periphery prevents that high-order N-type electric power is brilliant
Body pipe VThWith low level N-type power transistor VTlThe circuit structure ganged up also due to the change of high bit driver circuit, can simplify fall it is low
Level displacement circuit before bit driver circuit.
Embodiment
Embodiment of the present utility model is further described below in conjunction with each accompanying drawing.
The embodiment of the integrated drive electronics 200 driven shown in Fig. 1 for DC/DC switch converters power output transistor
In, including for high-order driving control signalThe high-order driving pre-stage buffer 260 of input buffering, for signal potential
The bootstrap capacitor C elevatedBOOT, for the Capacitance Coupled drive circuit 230 of signal coupling, for high-order buffered-display driver signal uDRP
The second reverse phase inverter 268;High-order driving control signal is the second pulse-width signalDelay from high position driving prime
Rush the input terminal input of device 260;High position driving pre-stage buffer 260 exports high-order buffered-display driver signal uDRPTo bootstrap capacitor
CBOOTNegative plate, while high-order driving pre-stage buffer 260 exports high-order buffered-display driver signal uDRPTo the second phase inverter 268
Input terminal;Bootstrap capacitor CBOOTPositive plate and Capacitance Coupled drive circuit 230 first input end electrical connection;Second
The output end of phase inverter 268 and the second input terminal electrical connection of Capacitance Coupled drive circuit 230;Capacitance Coupled drive circuit
230 the 3rd input terminal is used for the 3rd d. c. voltage signal u for accessing the 3rd external input power VREG of outsideREG;Electric capacity coupling
Close the first lead-out terminal of drive circuit 230 and high-order N-type power transistor VThGrid electrically connects, Capacitance Coupled drive circuit
230 the second lead-out terminal and high-order N-type power transistor VThSource electrode electrically connects;Second phase inverter 268, bootstrap capacitor CBOOTWith
Capacitance Coupled drive circuit 230 cooperates, by high-order buffered-display driver signal uDRPSignal potential raise, in high-order N-type electric power
Transistor VThAfter conducting, the first lead-out terminal of Capacitance Coupled drive circuit 230 can be made persistently to provide the high-order N of suitable potential
Type power transistor VThGate drive signal, i.e., high-order drive signal uGP。
In embodiment shown in Fig. 1, the Capacitance Coupled drive circuit 230 includes first switch K1, second switch K2, the
One coupled capacitor CBC1With the second N-type metal-oxide-semiconductor Q2;Second switch K2 one end the as Capacitance Coupled drive circuit 230 the 3rd is defeated
Enter terminal, that is, access the 3rd external input power VREG the 3rd d. c. voltage signal uREG;The second switch K2 other end and
One switch K1 one end electrical connection, while the second switch K2 other end also serves as the first of Capacitance Coupled drive circuit 230
Input terminal, and bootstrap capacitor CBOOTPositive plate electrical connection;The first switch K1 other end is used as Capacitance Coupled drive circuit
230 first lead-out terminal, export high-order N-type power transistor VThGate drive signal uGPTo high-order N-type power transistor
VThGrid;Meanwhile drain electrode of the first switch K1 other end also with the second N-type metal-oxide-semiconductor Q2 electrically connects;Coupling driving electricity
Road control signal uVBOOTWith the first d. c. voltage signal u of inputP1First switch K1 switch described in co- controlling;Second N-type
Metal-oxide-semiconductor Q2 source electrode is used as the second lead-out terminal of Capacitance Coupled drive circuit 230 and high-order N-type power transistor VThSource
Pole electrically connects;Second N-type metal-oxide-semiconductor Q2 grid and the first coupled capacitor CBC1One end electrical connection;First coupled capacitor CBC1's
The other end is used as the second input terminal of Capacitance Coupled drive circuit 230, and the output end electrical connection of the second phase inverter 268;The
Two switch K2 one end is from bootstrap capacitor CBOOTPositive plate access coupling drive circuit control signal uVBOOT, second switch K2's
The other end accesses the 3rd d. c. voltage signal uREG, coupling drive circuit control signal uVBOOTWith the 3rd d. c. voltage signal uREGAltogether
With control second switch K2 switch.
In embodiment shown in Fig. 2 and 3, the first switch K1 is the first p-type metal-oxide-semiconductor Q1, the first p-type metal-oxide-semiconductor Q1's
Grid and high-order N-type power transistor VThDrain electrode electrical connection, the first p-type metal-oxide-semiconductor Q1 drain electrode and the second N-type metal-oxide-semiconductor Q2
Drain electrode electrical connection, the first p-type metal-oxide-semiconductor Q1 source electrode are used as the first input end and bootstrapping electricity of Capacitance Coupled drive circuit 230
Hold CBOOTPositive plate electrical connection;First p-type metal-oxide-semiconductor Q1 source electrode and bootstrap capacitor CBOOTPositive plate electrical connection, access coupling
Drive circuit control signal uVBOOT;First p-type metal-oxide-semiconductor Q1 grid accesses the first DC voltage to be transformed from circuit node P1
Signal uP1;Coupling drive circuit control signal uVBOOTWith the first d. c. voltage signal uP1Co- controlling the first p-type metal-oxide-semiconductor Q1's
On off state.
In embodiment shown in Fig. 2, the second switch K2 is the first diode D1, and the first diode D1 positive pole is used as
3rd input terminal of Capacitance Coupled drive circuit 230, access the 3rd external input power VREG the 3rd d. c. voltage signal
uREG;First diode D1 negative pole and bootstrap capacitor CBOOTPositive plate electrical connection access coupling drive circuit control signal
uVBOOT;Coupling drive circuit control signal uVBOOTWith the 3rd d. c. voltage signal uREGCo- controlling the first diode D1's opens
Close.
In embodiment shown in Fig. 3, the second switch K2 includes the 4th N-type metal-oxide-semiconductor Q4, the second coupled capacitor CBC2With
Second diode D2, the second diode D2 positive pole is used as the 3rd input terminal of Capacitance Coupled drive circuit 230, access the 3rd
External input power VREG the 3rd d. c. voltage signal uREG;Meanwhile second diode D2 positive pole and the 4th N-type metal-oxide-semiconductor Q4
Source electrode electrical connection;Second diode D2 negative pole and the 4th N-type metal-oxide-semiconductor Q4 grid electrically connect;4th N-type metal-oxide-semiconductor Q4's
Grid also with the second coupled capacitor CBC2One end electrical connection;Second coupled capacitor CBC2The other end and the first coupled capacitor CBC1
One end electrical connection, the connection terminal be used as Capacitance Coupled drive circuit 230 the second input terminal, the connection terminal and second
The lead-out terminal electrical connection of phase inverter 268;4th N-type metal-oxide-semiconductor Q4 drain electrode first as Capacitance Coupled drive circuit 230 is defeated
Enter terminal, and bootstrap capacitor CBOOTPositive plate electrical connection, access coupling drive circuit control signal uVBOOT;Coupling drive circuit
Control signal uVBOOTWith the 3rd d. c. voltage signal uREGSecond switch K2 on off state described in co- controlling.
It is visible in signal timing diagram shown in Figure 4 and 5, as the voltage signal u on circuit node DRPDRPAbove earth potential is VDD
When, by the second phase inverter 268, the voltage signal u on circuit node DRP_NDRP-NAbove earth potential is zero potential VGND, voltage letter
Number uDRP-NIt is connected to the first coupled capacitor CBC1Negative plate, then due to the first coupled capacitor CBC1Coupling, the second N-type
Metal-oxide-semiconductor Q2 grid above earth potential is zero potential VGND, the second N-type metal-oxide-semiconductor Q2 closings;Bootstrap capacitor CBOOTPositive plate current potential
V is lifted to by bootstrappingREG+VDD;In this case, second switch K2 disconnects, the electrical connection open circuit of its two terminal circuit, first switch
K1 closures turn on, now bootstrap capacitor CBOOTPositive plate is that circuit node VBOOT directly connects with circuit node GP, bootstrap capacitor
CBOOTThe voltage signal u of positive plateVBOOTIt is directly inputted to high-order N-type power transistor VThGrid turn into high-order drive signal
uGP, now high-order drive signal uGPSignal above earth potential be VREG+VDD, can be by high-order N-type power transistor VThOpen, and
After the conducting of high-order N-type power transistor, high-order driving letter of the Capacitance Coupled drive circuit output with high driving ability can be made
Number to high-order N-type power transistor grid.
It is visible in signal timing diagram shown in Figure 4 and 5, as the voltage signal u on circuit node DRPDRPAbove earth potential is zero
Current potential VGNDWhen, bootstrap capacitor CBOOTNegative plate current potential be pulled down to zero potential VGND, bootstrap capacitor CBOOTPositive plate it is electric over the ground
Position is coupled to VREG, first switch K1 disconnects, second switch K2 closures, now bootstrap capacitor CBOOTPositive plate be circuit section
Point VBOOT and circuit node GP disconnect, by the second phase inverter 268, the voltage signal u on circuit node DRP_NDRP-NIt is electric over the ground
Position is VDD, meet the first coupled capacitor CBC1Negative plate, then due to the first coupled capacitor CBC1Coupling, the second N-type
Metal-oxide-semiconductor Q2 grid above earth potential is VDD, the second N-type metal-oxide-semiconductor Q2 openings, high-order N-type power transistor VThGate source voltage it is poor
It is pulled low, high-order N-type power transistor VThClose.
As shown in figure 5, when DC/DC switching converter operations are in BUCK patterns, circuit node P1 is an externally input straight
Flow voltage signal uINInput terminal, circuit node P1 voltage signal uP1=uIN;Circuit node P2 signal is designated as uP2, its
Current potential is ground potential VGND;Circuit node P3 signal is designated as uP3, circuit node P3 is DC/DC switch converters output voltages
Terminal, it is the d. c. voltage signal u passed through after conversion that it, which is exported,OUT, i.e. uP3=uOUT.Its course of work is is exactly on the whole
First pulse-width signal u of DC/DC switch converters control loop outputPWMAs high-order driving control signal, with the first arteries and veins
Wide modulated signal uPWMImpulse phase and the current potential height of space phase control high-order N-type power transistor VThWith low level N
Type power transistor VTlAlternate conduction.First pulse-width signal uPWMWith the second pulse-width signalPulse electricity
Position is the first input power VDD high potential VDD, its space current potential is the first input power VDD ground potential VGND;Second pulsewidth
Modulated signalWith the first pulse-width signal uPWMLogic non-signal each other.
As shown in figure 5, in the first pulse-width signal uPWMFirst phase be the first pulse-width signal uPWMCurrent potential
For space current potential when, the first pulse-width signal uPWMSignal potential be zero potential VGND, it is defeated after the first phase inverter 264
Go out the second pulse-width signalSecond pulse-width signalSignal potential be high potential VDD;Second pulsewidth
Modulated signalAfter a high position drives pre-stage buffer 260, high position driving pre-stage buffer 260 exports high bit buffering and driven
Dynamic signal uDRP;High-order buffered-display driver signal uDRPWith the second pulse-width signalSame-phase, high-order buffered-display driver signal
uDRPPulse potential be high potential VDD, space current potential is zero potential VGND;First switch K1 and second switch K2 control signal
Anti-phase each other, i.e. first switch K1 and second switch K2 on off state is mutual exclusion, controls of two switches in control signal
Under, a closing, another opening;As high-order buffered-display driver signal uDRPIt is that signal potential is high potential in pulse potential
VDDWhen, due to bootstrap capacitor CBOOTCoupling, bootstrap capacitor CBOOTThe current potential of positive plate is coupled to VREG+VDD, now
One switch K1 closures, second switch K2 are disconnected, and the second N-type metal-oxide-semiconductor Q2 is closed, bootstrap capacitor CBOOTPositive plate and circuit node GP
Directly connect, bootstrap capacitor CBOOTThe voltage signal u of positive plateVBOOTIt is directly inputted to high-order N-type power transistor VThGrid
As high-order drive signal uGP, its current potential is VREG+VDD, high-order N-type power transistor VThOpen;Similarly, the first pulsewidth modulation
Signal uPWMAfter level displacement circuit 265 and low level driving buffer 266, u is obtainedGN, in uGPAbove earth potential is VREG+
VDDWhen, uGNAbove earth potential be zero potential VGND, low level N-type power transistor VTlClose;Therefore in the first pulse-width signal
uPWMFirst phase when, circuit node SW voltage signal is circuit node P1 voltage signal uP1, external inductors L1 flows through
Electric current enters rise period.
As shown in figure 5, in the first pulse-width signal uPWMSecond phase be the first pulse-width signal uPWMCurrent potential
For pulse potential when, the first pulse-width signal uPWMSignal potential be high potential VDD, after the first phase inverter 264, output
Second pulse-width signalSecond pulse-width signalSignal potential be zero potential VGND;Second pulsewidth is adjusted
Signal processedAfter a high position drives pre-stage buffer 260, high position driving pre-stage buffer 260 exports high-order buffered-display driver
Signal uDRP;High-order buffered-display driver signal uDRPWith the second pulse-width signalSame-phase, high-order buffered-display driver signal uDRP
Pulse potential be high potential VDD, space current potential is zero potential VGND;Now high-order buffered-display driver signal uDRPIn space current potential
For zero potential VGND;As high-order buffered-display driver signal uDRPIt is that signal potential is zero potential V in pulse potentialGNDWhen, first switch
K1 is disconnected, second switch K2 closures, and the second N-type metal-oxide-semiconductor Q2 is opened, high-order N-type power transistor VThGrid potential drawn
It is low, high-order N-type power transistor VThClose;Meanwhile bootstrap capacitor CBOOTThe above earth potential of positive plate is VREG, second switch K2
Closure, will supplement energy to bootstrap capacitor CBOOTOn positive plate;Similarly, the first pulse-width signal uPWMBy level shift
After circuit 265 and low level driving buffer 266, low level drive signal u is obtainedGN, low level drive signal uGNAbove earth potential be
Current potential VVNCLP, low level N-type power transistor VTlOpen;Therefore in the first pulse-width signal uPWMSecond phase when, circuit
Node SW voltage signal is circuit node P1 voltage signal uP1, electric current that external inductors L1 flows through, which enters, declines the period.
As shown in figure 5, in the first pulse-width signal uPWMSecond phase after be third phase, in third phase, the
One pulse-width signal uPWMRemain in that the pulse potential V of second phaseDD;When ZCD modules 105 detect that inductive current declines
During to 0, other control circuits in ZCD modules 105 or DC/DC switch converters can control low level N-type power transistor VTl
Close, now high-order drive signal uGPWith low level drive signal uGNCurrent potential be zero potential VGND, circuit node SW signal
For uP3, inductive current 0.
In embodiment as shown in Figures 2 and 3, the grid that first switch K1 is the first p-type metal-oxide-semiconductor Q1 is accessed from circuit node
First d. c. voltage signal u of P1 inputsP1.It is visible in signal timing diagram with reference to shown in Figure 4 and 5, when on circuit node DRP
Voltage signal uDRPAbove earth potential is VDD, bootstrap capacitor CBOOTPositive plate is circuit node VBOOT voltage signal uVBOOTIt is coupled
To than the first d. c. voltage signal uP1Higher above earth potential, the first p-type metal-oxide-semiconductor Q1 are closed automatically, bootstrap capacitor CBOOTPositive pole
Plate directly connects with circuit node GP, bootstrap capacitor CBOOTThe voltage signal u of positive plateVBOOTIt is directly inputted to high-order N-type electric power
Transistor VThGrid turn into high-order drive signal uGP;As the voltage signal u on circuit node DRPDRPAbove earth potential is zero electricity
Position VGND, bootstrap capacitor CBOOTThe voltage signal u of positive plateVBOOTCurrent potential is pulled down to the 3rd d. c. voltage signal uREGIt is electric over the ground
Position VREG, above earth potential VREGLess than the first d. c. voltage signal uP1Above earth potential VP1;First p-type metal-oxide-semiconductor Q1 is from dynamic circuit breaker
Open, bootstrap capacitor CBOOTConnection between positive plate and circuit node GP is in off state.
In embodiment as shown in Figures 2 and 3, second switch K2 is the first diode D1, or second switch K2 is by the
Four N-type metal-oxide-semiconductor Q4, the second coupled capacitor CBC2With the switch module of the second diode D2 compositions.Signal with reference to shown in Figure 4 and 5
Visible in timing diagram, second switch K2 effect is to realize the 3rd d. c. voltage signal uREGInput terminal and bootstrap capacitor CBOOT
Single-phase conducting between positive plate;3rd d. c. voltage signal uREGInput terminal and bootstrap capacitor CBOOTList between positive plate
It is conducted, for supplementing each cycle due to bootstrap capacitor C in switching processBOOTEnergy loss on positive plate.
As shown in Fig. 2 the reality of the integrated drive electronics 200 for the driving of DC/DC switch converters power output transistor
Apply in example, when DC/DC switch converters normal work is in first phase Phase1, that is, high-order driving control signal is
When two pulse-width signals are in pulse potential, circuit node VBOOT current potential VVBOOTIt can be elevated, work as VVBOOT>VP1+VTHWhen,
Wherein VP1For circuit node P1 current potential, VTHThreshold value for the first p-type metal-oxide-semiconductor Q1 is the absolute value of grid source cut-in voltage, high-order
Drive signal uGPCurrent potential is by circuit node VBOOT current potential VVBOOTDraw high, make high-order N-type power transistor VThOpen;Meanwhile
Due to the first coupled capacitor CBC1Coupling, the second N-type metal-oxide-semiconductor Q2 signal is circuit node SW signal, makes the 2nd N
Type metal-oxide-semiconductor Q2 is closed;DC/DC switch converters normal work is in second phase Phase2, that is, high-order drive control letter
Number i.e. the second pulse-width signal is when being in pulse potential, circuit node VBOOT current potential VVBOOTAgain V is dropped toREG-VD1,
VD1Numerical value be the first diode D1 forward conduction voltage, now the second switch K2 be the first p-type metal-oxide-semiconductor Q1 be close
, circuit node VBC signal potential is opened coupled to a high position, the second N-type metal-oxide-semiconductor Q2, high-order drive signal uGPCurrent potential is drawn
It is low, make high-order N-type power transistor VThClose.
In an embodiment as illustrated in figure 2, as bootstrap capacitor CBOOTThe above earth potential of positive plate is less than VREG-VD1When, will
Energy is supplemented to bootstrap capacitor CBOOTOn positive plate;Wherein VREGFor the 3rd d. c. voltage signal uREGAbove earth potential, VD1For
The cut-in voltage of one diode D1 forward conductions;The advantages of embodiment scheme is simple, is had about on diode during shortcoming
0.7V pressure drop, efficiency and driving voltage can be influenceed.
As shown in figure 3, the reality of the integrated drive electronics 200 for the driving of DC/DC switch converters power output transistor
Apply in example, the first switch K1 includes the 4th N-type metal-oxide-semiconductor Q4, the second coupled capacitor CBC2With the second diode D2, the two or two
Pole pipe D2 positive pole is used as the 3rd lead-out terminal of Capacitance Coupled drive circuit 230, accesses the second DC voltage of outside input
Signal uREG;Meanwhile second diode D2 positive pole and the 4th N-type metal-oxide-semiconductor Q4 source electrode electrical connection, the second diode D2's is negative
Pole and the 4th N-type metal-oxide-semiconductor Q4 grid electrically connect;4th N-type metal-oxide-semiconductor Q4 grid also with the second coupled capacitor CBC2One end
Electrical connection;Second coupled capacitor CBC2The other end and the first coupled capacitor CBC1One end electrical connection, the connection terminal be used as electricity
Hold the second input terminal of coupling drive circuit 230, and the output end electrical connection of the second phase inverter 268;The second switch K2
For the first p-type metal-oxide-semiconductor Q1, the first p-type metal-oxide-semiconductor Q1 grid and high-order N-type power transistor VThDrain electrode electrical connection, the first P
Type metal-oxide-semiconductor Q1 drain electrode and the second N-type metal-oxide-semiconductor Q2 drain electrode electrically connect, and the first p-type metal-oxide-semiconductor Q1 source electrode is used as Capacitance Coupled
The first input end and bootstrap capacitor C of drive circuit 230BOOTPositive plate electrical connection;Second N-type metal-oxide-semiconductor Q2 grid and
The first resistor R1 and second resistance R2 of series connection are provided between source electrode, is also set between the second N-type metal-oxide-semiconductor Q2 grid and source electrode
It is equipped with the 3rd N-type metal-oxide-semiconductor Q3;3rd N-type metal-oxide-semiconductor Q3 drain electrode and the second N-type metal-oxide-semiconductor Q2 grid electrically connect, the 3rd N-type
Metal-oxide-semiconductor Q3 source electrode and the second N-type metal-oxide-semiconductor Q2 source electrode electrically connect, the 3rd N-type metal-oxide-semiconductor Q3 grid while and first resistor
R1 and second resistance R2 electrical connections.
In embodiment as shown in Figure 3, using the 4th controlled N-type metal-oxide-semiconductor Q4, the second coupled capacitor CBC2With the two or two
Pole pipe D2 realizes second switch K2 switch control;When circuit node DRP above earth potential is VDDWhen, the second coupled capacitor CBC2
Electric capacity can make the 4th N-type metal-oxide-semiconductor Q4 grid above earth potential the 4th N-type metal-oxide-semiconductor Q4 be closed, as circuit node DRP toward lower coupling
Above earth potential be zero potential VGNDWhen, the second coupled capacitor CBC2The 4th N-type metal-oxide-semiconductor Q4 grid can be made to be coupled toward high potential,
The 4th N-type metal-oxide-semiconductor Q4 is opened completely, can make bootstrap capacitor CBOOTPositive plate and the 3rd d. c. voltage signal uREGInput terminal
Directly turn on, bootstrap capacitor CBOOTIt is able to supplement energy.Fig. 3 is with the second coupled capacitor CBC2And the two or two pole for voltage stabilizing
Pipe D2 and the 4th N-type metal-oxide-semiconductor Q4 compositions, its operation principle are when needing the 4th N-type metal-oxide-semiconductor Q4 openings, pass through the second coupling electricity
Hold CBC2Coupling Q4 is opened, this implementation advantage is that the 4th N-type metal-oxide-semiconductor Q4 is to open completely, to efficiency and drive
Dynamic voltage is without influence.
As shown in figure 3, the reality of the integrated drive electronics 200 for the driving of DC/DC switch converters power output transistor
Apply in example, when DC/DC switch converters normal work is in first phase Phase1, that is, high-order driving control signal is
When two pulse-width signals are in pulse potential, circuit node VBOOT current potential VVBOOTIt can be elevated, work as VVBOOT>VP1+VTHWhen,
Wherein VP1For circuit node P1 current potential, VTHThreshold value for the first p-type metal-oxide-semiconductor Q1 is grid source cut-in voltage absolute value, and a high position is driven
Dynamic signal uGPCurrent potential is by circuit node VBOOT current potential VVBOOTDraw high, make high-order N-type power transistor VThOpen;Meanwhile by
In the first coupled capacitor CBC1Coupling, the second N-type metal-oxide-semiconductor Q2 signal current potential is VREG-VD2, make the second N-type metal-oxide-semiconductor Q2
Close;DC/DC switch converters normal work is in second phase Phase2, that is, high-order driving control signal is the second arteries and veins
When wide modulated signal is in pulse potential, circuit node VBOOT current potential VVBOOTAgain V is dropped toREG, now the first p-type MOS
Pipe Q1 is to close, and circuit node VBC signal potential is opened coupled to a high position, the second N-type metal-oxide-semiconductor Q2, high-order drive signal
uGPCurrent potential is pulled low, and makes high-order N-type power transistor VThClose.
Fig. 2 and Fig. 3 embodiment is different to be, second switch K2 is simply real with diode in embodiment illustrated in fig. 2
It is existing, second switch K2 the 4th N-type metal-oxide-semiconductor Q4, the second coupled capacitor C in embodiment illustrated in fig. 3BC2It is total to the second diode D2
With composition;Specifically difference is bootstrap capacitor C to two embodimentsBOOTThe above earth potential of upper precharge is in different size;Fig. 2 institutes
It is V to show the precharge potential size in embodimentREG-VD2, the precharge level in embodiment illustrated in fig. 3 is VREG, cause most rear-guard
Move high-order N-type power transistor VThGate source voltage absolute value it is different, respectively VREG-VD2And VREG, due to shown in Fig. 3
High-order N-type power transistor VT in embodimenthGate source voltage be higher than embodiment illustrated in fig. 2 in high-order N-type power transistor VTh
Gate source voltage, therefore with high-order N-type power transistor VT in embodiment illustrated in fig. 3hDuring conducting state, its conducting resistance phase
To smaller.
The embodiment of the integrated drive electronics 200 driven shown in Fig. 1 for DC/DC switch converters power output transistor
It is middle to complete high-order N-type power transistor VT with more simplified circuithWith low level N-type power transistor VTlDriving, with respect to Fig. 4
The drive circuit of shown prior art simplifies bit level shift circuit complicated in the prior art, improves circuit efficiency,
Reduce circuit delay;The drive circuit drives the circuit requirement of buffering lower high-order prime so that high-order prime driving is slow
Punching need not be reduced the requirement to device, reduced the area of integrated circuit using isolation class device.
In the double NMOS power transistor drive circuit structures of the typical case of prior art shown in Fig. 6, the first pulse-width signal uPWM
It is being controlled for switching tube switch for the closed control circuit output in the DC/DC switch converters for apply the circuit framework
Square-wave signal;In high-order N-type power transistor VThSwitch driving circuit in, pulse-width signal uPWMInput to phase inverter
64, phase inverter exports " non-" signal i.e. the second pulse-width signal of first pulse-width signalSecond pulsewidth is adjusted
Signal processedIt is input to bit level shift circuit 61, the second pulse-width signalPulse potential for outside first
Portion input power VDD high potential VDD, the second pulse-width signalSpace current potential be the first external input power VDD
Ground potential VGND;Bit level shift circuit 61 is by the second pulse-width signalPulse potential from first outside it is defeated
Enter power vd D high potential VDDIt is transformed into bootstrap capacitor positive plate current potential VBOOT, while bit level shift circuit 61 is by second
Pulse-width signalSpace current potential from the first external input power VDD ground potential VGNDIt is transformed into high-order N-type electric power
Transistor VThSource potential VSW;The output u of bit level shift circuit 61DRPSignal buffers to high position driving buffer 60,
Signal u of the high position driving output of buffer 60 with strong driving forceGPTo high-order N-type power transistor VThGrid, carry out high
Position N-type power transistor VThSwitch drive.Second pulse-width signalSignal potential integral raising to suitable
Level, particularly in high-order N-type power transistor VThSource potential VSWWith respect to the first external input power VDD ground potential
VGNDWhen higher, preferably to carry out high-order N-type power transistorSwitch drive.
Low level N-type power transistor VT in the double NMOS power transistor circuits frameworks of typical case shown in Fig. 6hSwitch drive
In circuit, the first pulse-width signal uPWMIt is input to low level level displacement circuit 65, the first pulse-width signal uPWMPulse
Current potential is the first external input power VDD high potential VDD, pulse-width signal uPWMSpace current potential for the first outside input electricity
Source VDD ground potential VGND;Low level level displacement circuit 65 is by the first pulse-width signal uPWMPulse potential outside first
Input power VDD high potential VDDIt is transformed into the current potential V of the 4th external input power VNCLP high potentialNCLP, while low level electricity
Prosposition shift circuit 65 is by the first pulse-width signal uPWMSpace current potential from the first external input power VDD ground potential VGNDTurn
Change to low level N-type power transistor VTlSource potential VP2;The output signal u of low level level displacement circuit 65DRNIt is input to low
Position driving buffer 66 buffers, drive signal u of the low level driving output of buffer 66 with strong driving forceGNTo low level N-type electricity
Power transistor VTlGrid, carry out low level N-type power transistor VTlSwitch drive.
In Fig. 1 and Fig. 6, the 4th d. c. voltage signal u of the 4th external input power VNCLP inputsNCLPIt is to be used for low level
Drive the power supply signal of buffer, under Buck patterns, the 4th d. c. voltage signal uNCLPEqual to the voltage to be transformed of outside input
Signal is the first d. c. voltage signal uP1Voltage signal caused by LDO either inside DC/DC switch converters;Boost patterns
Under, the 4th d. c. voltage signal uNCLPIt is the voltage signal u from circuit node P3 inputsP3, can also be signal node P1 outputs
Voltage signal uP1-out, or voltage signal caused by LDO inside DC/DC switch converters;Under Buck-BOOST patterns,
4th d. c. voltage signal uNCLPIt is the difference letter of voltage signal caused by LDO and signal node P2 inside DC/DC switch converters
Number, the difference signal is that fixed level drives buffer power supply as low level.
Bootstrap capacitor C in Fig. 6BOOTPositive plate simultaneously and bit level shift circuit 61 input terminal, a height
The negative pole electrical connection of the input terminal, diode D1 of position driving buffer 60;Bootstrap capacitor CBOOTNegative plate and high-order N
Type power transistor VThSource electrode electrical connection;uREGIt is the 3rd straight to be that the LDO that is set from DC/DC switch converters is obtained for signal
Flow voltage signal uREG, its above earth potential is VREG, uREGSignal for high bit driver circuit after diode D1 decompressions by providing work
Power supply.
In Fig. 1 and Fig. 6, the 3rd d. c. voltage signal uREGIt is to be used to supplement each switch periods of CBOOT because switch causes
Energy loss, under Buck patterns, the 3rd d. c. voltage signal uREGVoltage signal to be transformed equal to outside input is first straight
Flow voltage signal uP1Or voltage signal caused by LDO inside DC/DC switch converters;Under Boost patterns, the 3rd DC voltage
Signal uREGEqual to the voltage signal u inputted from circuit node P3P3, also can be the first d. c. voltage signal uP1Or DC/DC is opened
Close voltage signal caused by LDO inside converter;Under Buck-BOOST patterns, VREG signal is inside DC/DC switch converters
Voltage signal caused by LDO.
As shown in Fig. 7 to 8, when DC/DC switching converter operations are in BUCK patterns, in the drive circuit of prior art,
The d. c. voltage signal u that circuit node P1 is an externally inputINInput terminal, circuit node P1 the first d. c. voltage signal
uP1=uIN;Circuit node P2 signal is designated as uP2, its current potential is ground potential VGND;Circuit node P3 signal is designated as uP3, circuit
Node P3 is the terminal of DC/DC switch converters output voltages, and it is the d. c. voltage signal u passed through after conversion that it, which is exported,OUT,
That is uP3=uOUT。
As shown in Fig. 6 to 8, when DC/DC switching converter operations are in BOOST patterns, in the drive circuit of prior art,
The d. c. voltage signal u that circuit node P3 is an externally inputINInput terminal, circuit node P3 voltage signal uP3=uIN;Electricity
Circuit node P2 signal is designated as uP2, its current potential is ground potential VGND;Circuit node P1 signal is designated as uP1, circuit node P1 is
The terminal of DC/DC switch converters output voltages, it is the d. c. voltage signal u passed through after conversion that it, which is exported,OUT, i.e. uP1=
uOUT。
As shown in Fig. 6 to 8, when DC/DC switching converter operations are in BUCK-BOOST patterns, the driving electricity of prior art
The d. c. voltage signal u that Lu Zhong, circuit node P1 are an externally inputINInput terminal, circuit node P1 voltage signal uP1=
uIN;Its current potential is ground potential VGND;Circuit node P3 signal is designated as uP3, its current potential is ground potential VGND;Circuit node P2 letter
Number it is designated as uP2, circuit node P2 is the terminal of DC/DC switch converters output voltages, and it is the direct current passed through after conversion that it, which is exported,
Voltage signal uOUT, i.e. uP2=uOUT。
As shown in Fig. 6 to 8, in the drive circuit of prior art, by taking BUCK patterns as an example, circuit node SW voltage signal
It is designated as uSW, the signal is switching signal when inductive current is not zero.When DC/DC switch converters operate in CCM working methods
When, there are the first operating phase and the second operating phase both phase states to correspond to the first pulse-width signal u respectivelyPWMSky
Lattice phase and impulse phase.As the first pulse-width signal uPWMWhen being in space phase, high-order N-type power transistor VThBeat
Open, low level N-type power transistor VTlClose, circuit node SW signals uSWCurrent potential is equal to circuit node P1 input signals UP1Electricity
Position VP1, bootstrap capacitor CBOOTPositive plate is that circuit node VBOOT above earth potential is VREG-VD1+VP1, bootstrap capacitor CBOOTTwo
Terminal voltage difference is VREG-VD1, wherein VREGFor the d. c. voltage signal u inputted from diode positive poleREGAbove earth potential, VD1For
Voltage on one diode D1, VP1It is high-order N-type power transistor VThDrain electrode above earth potential, due to high-order N-type electric power crystal
Pipe VThConducting, high-order N-type power transistor VThSource electrode above earth potential be exactly high-order N-type power transistor VThDrain electrode over the ground
Current potential VP1, therefore high-order N-type power transistor VThGrid and source electrode between voltage VGS=VREG-VD1.When the first pulsewidth is adjusted
Signal u processedPWMWhen being switched to space phase from impulse phase, circuit node SW signal uSWCurrent potential from circuit node P2 over the ground
Current potential VP2Under BUCK patterns, the current potential is ground potential VP2=VGNDIt is rapidly switched to circuit node P1 current potential VP1;Bootstrapping electricity
Hold CBOOTPositive plate on current potential elevated to VREG-VD1+VP1, bootstrap capacitor CBOOTNegative plate on current potential be high-order N-type
Power transistor VThDrain potential VP1, bootstrap capacitor CBOOTOn voltage remain in that as VREG-VD1;So that high-order driving is slow
Rush the drive signal u of outputGNAbove earth potential be VREG-VD1+VP1, so as to high-order N-type power transistor VThGrid and source electrode it
Between gate source voltage VGS=VREG-VD1, such gate source voltage can be maintained at high-order N-type power transistor VThCut-in voltage it
On so that high-order N-type power transistor VThIt is able to continue to maintain conducting state.
As shown in Fig. 6 to 8, in the drive circuit of prior art, by taking BUCK patterns as an example, when DC/DC switch converters are transported
Row has the first operating phase, the second operating phase and the 3rd operating phase these three phase states in DCM working methods;Its
In the corresponding first pulse-width signal u of the first operating phasePWMSpace phase;Second operating phase and the 3rd operating phase pair
Answer the first pulse-width signal uPWMImpulse phase.Wherein the first operating phase, the second operating phase circuit work schedule and
CCM working methods are identicals;In DCM working methods the 3rd operating phase state is only presented on different from CCM working methods;
In the 3rd operating phase state, the electric current of outside energy storage inductor can drop to zero, ZCD modules and detect that inductive current drops to 0, so
After can close low level N-type power transistor VTl, circuit node SW signal uSWCurrent potential is equal to now circuit node P3 electricity over the ground
Position VP3。
Fig. 9 show bit level shift circuit 61 in the double NMOS power transistor drive circuit structures of prior art typical case
Detailed circuit, the circuit structure is complicated, has used 8 transistors;Need to incite somebody to action by the collaborative work of 8 transistors
The pulse-width signal u of inputPWMIt is lifted to suitable high-order N-type power transistor VThThe current potential of raster data model;Bit level position
Not only itself the meeting consumed energy, and signal delay can be introduced of shift circuit 61.
Figure 10 show commonly used in the double NMOS power transistor drive circuit structures of prior art prevent high-order N-type electric power
Transistor VThWith low level N-type power transistor VTlThe circuit structure block diagram ganged up, in order to ensure that high bit driver circuit and low level drive
Dynamic circuit is operated in sequential in correspondence with each other, therefore in fig. 8, and circuit unit that power tube is ganged up is prevented marked as 80
In, level displacement circuit is provided with before high bit driver circuit and before low level drive circuit, circuit structure is complicated.
With respect to Fig. 6 drive circuits of the prior art, without the bit level displacement of complexity in the embodiment shown in Fig. 1
Circuit 61, and circuit is more simple used by realizing related circuit, the chip area that circuit element occupies also is substantially reduced;It is existing
There is the bit level shift circuit 61 in technology to need matched high-order prime to drive the circuit in buffering to need higher
Pressure-resistant performance, the drive circuit drives the circuit requirement of buffering lower high-order prime so that high-order prime driving buffering nothing
Isolation class device need to be used, the requirement to device is reduced, further reduces the area of integrated circuit;Moreover, this reality
With in new integrated drive electronics, due to eliminating bit level shift circuit 61 of the prior art shown in Fig. 4, to application
The DC/DC switch converters of the drive circuit, its periphery prevent high-order N-type power transistor VThIt is brilliant with low level N-type electric power
Body pipe VTlThe circuit structure ganged up is also due to the change of high bit driver circuit, can simplify the level before falling low level drive circuit
Shift circuit so that the area of integrated circuit can further reduce.
The integrated drive electronics 200 for being used for the driving of DC/DC switch converters power output transistor as shown in Figure 1 is implemented
In example, the clamp circuit of gate source voltage control, the clamp circuit bag are provided between the second N-type metal-oxide-semiconductor Q2 grid and source electrode
Include the first resistor R1 and second resistance R2 being connected between the second N-type metal-oxide-semiconductor Q2 grid and source electrode;The clamp circuit also wraps
Include the 3rd N-type metal-oxide-semiconductor Q3 being arranged between the second N-type metal-oxide-semiconductor Q2 grid and source electrode;3rd N-type metal-oxide-semiconductor Q3 drain electrode and
Second N-type metal-oxide-semiconductor Q2 grid electrical connection, the 3rd N-type metal-oxide-semiconductor Q3 source electrode and the second N-type metal-oxide-semiconductor Q2 source electrode electrical connection,
3rd N-type metal-oxide-semiconductor Q3 grid electrically connects with first resistor R1 and second resistance R2 simultaneously.The effect of the clamp circuit is to be used for
Second N-type metal-oxide-semiconductor Q2 gate source voltage clamp, it is ensured that when first phase switchs to the switching of the second operating phase, the second N-type MOS
Pipe Q2 is now changed into open mode by closing, due to circuit node SW signal uSWThe rapid decrease of current potential, the second N-type MOS
Pipe Q2 grid voltage can not follow quickly, the second N-type metal-oxide-semiconductor Q2 gate source voltage difference can be made to become big, to ensure the second N-type
Metal-oxide-semiconductor Q2 gate source voltage not over process devices working range, it is necessary to make clamper to Q2 gate source voltages, its clamp voltage
For VTH× (R1+R2)/R2, wherein VTHFor the 3rd N-type metal-oxide-semiconductor Q3 turn-on threshold voltage.
The integrated drive electronics 200 for being used for the driving of DC/DC switch converters power output transistor as shown in Figure 1 is implemented
In example, in addition to the first phase inverter 264, low level driving control signal level displacement circuit 265 and low level driving buffer 266;
Low level driving control signal is the first pulse-width signal uPWMFor the second pulse-width signal" logic NOT " signal;
Low level driving control signal is the first pulse-width signal uPWMInput to low level driving control signal level displacement circuit 265 enters
The displacement of row signal potential, by the first pulse-width signal uPWMPulse potential from the first input power VDD high potentials VDDConversion
To the 4th external input power VNCLP of outside the 4th d. c. voltage signal uNCLPCurrent potential VNCLP, while low level drive control is believed
Number level displacement circuit 265 is by the first pulse-width signal uPWMSpace current potential from the first input power VDD ground potentials VGNDTurn
Change to low level N-type power transistor VTlSource potential VP2;The output signal of low level driving control signal level displacement circuit 265
Buffer 266 is driven to low level, low level driving buffer 266 exports low level drive signal uGNTo low level N-type power transistor VTl
Grid, for low level N-type power transistor VTlDriving;Low level driving control signal is the first pulse-width signal uPWMIt is defeated
Enter to the first phase inverter 264, the first phase inverter 264 and export high-order driving control signal i.e. the second pulse-width signalExtremely
High position driving pre-stage buffer 260.
As shown in figure 1, the reality of the integrated drive electronics 200 for the driving of DC/DC switch converters power output transistor
Apply in example, in addition to ZCD modules 105 are used to detect the i.e. high-order N-type power transistor VT of rectifying tubehAnd/or low level N-type electric power is brilliant
Body pipe VTlZero current cross;When being operated in BUCK patterns in the DC/DC switch converters for applying the integrated drive electronics 200
When being used as BUCK systems, low level N-type power transistor VTlFor rectifying tube, then ZCD modules 105 can detect low level N-type electric power crystalline substance
Body pipe VTlDrain electrode and low level N-type power transistor VTlSource electrode between current signal;When applying the integrated drive electronics
When BOOST patterns be operated in 200 DC/DC switch converters being used as BOOST systems, high-order N-type power transistor VThFor
Rectifying tube, ZCD modules 105 will detect high-order N-type power transistor VThDrain electrode and high-order N-type power transistor VThSource
Current signal between pole;When being operated in BUCK- in the DC/DC switch converters for applying the integrated drive electronics 200
When BOOST patterns are used as BUCK-BOOST systems, low level N-type power transistor VTlFor rectifying tube, then ZCD modules 105 can be examined
Survey low level N-type power transistor VTlDrain electrode and low level N-type power transistor VTlSource electrode between current signal.
As shown in figure 1, the reality of the integrated drive electronics 200 for the driving of DC/DC switch converters power output transistor
Apply in example, in addition to ring cancellation module 101 is used to remove in external inductors L1 due to ring caused by self-oscillation;When the collection
Worked in into the DC/DC switch converters of drive circuit 200 under DCM patterns, and rectifying tube is detected by ZCD modules 105
When electric current is 0, now high-order N-type power transistor VThAnd/or low level N-type power transistor VTlWhen all closing, ring eliminates mould
Block 101 is removed in external inductors L1 due to ring caused by self-oscillation.
As shown in Fig. 2 the reality of the integrated drive electronics 200 for the driving of DC/DC switch converters power output transistor
Apply in example, the positive pole that the first switch K1 is the first diode D1, the first diode D1 is used as Capacitance Coupled drive circuit 230
The 3rd lead-out terminal, access the second d. c. voltage signal u of outside inputREG;First diode D1 negative pole and the first p-type
Metal-oxide-semiconductor Q1 source electrode electrical connection;The second switch K2 is the first p-type metal-oxide-semiconductor Q1, the first p-type metal-oxide-semiconductor Q1 grid and a high position
N-type power transistor VThDrain electrode electrical connection, the first p-type metal-oxide-semiconductor Q1 drain electrode and the second N-type metal-oxide-semiconductor Q2 drain electrode are electrically connected
Connect, the first p-type metal-oxide-semiconductor Q1 source electrode is used as the first input end and bootstrap capacitor C of Capacitance Coupled drive circuit 230BOOT's
Positive plate electrically connects;The first resistor R1 and second resistance of series connection are provided between second N-type metal-oxide-semiconductor Q2 grid and source electrode
R2, the 3rd N-type metal-oxide-semiconductor Q3 is additionally provided between the second N-type metal-oxide-semiconductor Q2 grid and source electrode;3rd N-type metal-oxide-semiconductor Q3 drain electrode
Electrically connected with the second N-type metal-oxide-semiconductor Q2 grid, the 3rd N-type metal-oxide-semiconductor Q3 source electrode and the second N-type metal-oxide-semiconductor Q2 source electrode are electrically connected
Connect, the 3rd N-type metal-oxide-semiconductor Q3 grid electrically connects with first resistor R1 and second resistance R2 simultaneously.
It is another it should be noted that, the negative pole of outside power supply source is the zero-potential point of circuit in the utility model, the utility model
In other circuit nodes potential value be all the relative zero-potential point numerical value;Battery or externally fed source voltage are its positive pole
With the potential difference of negative pole.For convenience, part of module employs one, second-class serial number, these serial numbers not generation
Its position of table or restriction sequentially, it is convenient to be intended merely to description.
Embodiment of the present utility model is the foregoing is only, above-described circuit topological structure is only of the present utility model
A kind of specific embodiment, the scope of the claims of the present utility model is not thereby limited, it is every to utilize utility model specification and accompanying drawing
The equivalent structure or equivalent flow conversion that content is made, or other related technical areas are directly or indirectly used in, similarly
It is included in scope of patent protection of the present utility model.