CN109671813A - A kind of GaN base light emitting epitaxial wafer and preparation method thereof - Google Patents
A kind of GaN base light emitting epitaxial wafer and preparation method thereof Download PDFInfo
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- CN109671813A CN109671813A CN201811320218.XA CN201811320218A CN109671813A CN 109671813 A CN109671813 A CN 109671813A CN 201811320218 A CN201811320218 A CN 201811320218A CN 109671813 A CN109671813 A CN 109671813A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
Abstract
The invention discloses a kind of GaN base light emitting epitaxial wafers and preparation method thereof, belong to GaN base light emitting technical field.The LED epitaxial slice includes: substrate, the buffer layer being sequentially deposited over the substrate, undoped GaN layer, N-type GaN layer, low temperature stress release layer, multiple quantum well layer, electronic barrier layer, p-type GaN layer, and p-type ohmic contact layer, the multiple quantum well layer includes the trap barrier layer of several stackings, the trap barrier layer includes the luminous well layer of InGaN of stacked above one another, shine trap protective layer, and GaN barrier layer, GaN barrier layer in the trap barrier layer of the electronic barrier layer is contacted with the electronic barrier layer, the luminous trap protective layer includes AlInN layers, the InGaN shines well layer as the luminous well layer of low temperature InGaN, the luminous trap protective layer is the luminous trap protective layer of medium temperature, the GaN barrier layer is high temperature GaN barrier layer.
Description
Technical field
The present invention relates to GaN base light emitting field, in particular to a kind of GaN base light emitting epitaxial wafer and its system
Preparation Method.
Background technique
GaN (gallium nitride) base LED (Light Emitting Diode, light emitting diode) generally comprises epitaxial wafer and outside
Prolong the electrode of on piece preparation.Epitaxial wafer generally includes: buffer layer, the undoped GaN of substrate and stacked above one another on substrate
Layer, N-type GaN layer, MQW (Multiple Quantum Well, multiple quantum wells) layer, electronic barrier layer, p-type GaN layer and ohm connect
Contact layer.When a current passes through, the hole of the p type island regions such as the electronics of the N-type regions such as N-type GaN layer and p-type GaN layer enters MQW active area
And it is compound, issue visible light.The conventional structure of mqw layer is that InGaN Quantum Well/GaN quantum builds the superlattice structure constituted.
In the implementation of the present invention, the inventor finds that the existing technology has at least the following problems: InGaN Quantum Well
Low 100 DEG C of growth temperature or so of growth temperature ratio GaN quantum base, on the one hand, between InGaN Quantum Well and GaN quantum base
Larger temperature difference influences carrier and passes rapidly through this so that there are apparent interfaces because of crystal quality difference between trap base
Interfacial migration is to Quantum Well；On the other hand, the growth temperature that GaN quantum is built is higher, so that the In in InGaN Quantum Well is largely analysed
Out, the quality that is incorporated to of In component in Quantum Well is reduced, and the reduction of In constituent content, it will affect the combined efficiency of carrier.
Summary of the invention
The embodiment of the invention provides a kind of GaN base light emitting epitaxial wafers and preparation method thereof, can be improved trap base
Between interface crystal quality, and reduce InGaN Quantum Well in In be largely precipitated.The technical solution is as follows:
In a first aspect, providing a kind of GaN base light emitting epitaxial wafer, the LED epitaxial slice includes:
Substrate, the buffer layer being sequentially deposited over the substrate, undoped GaN layer, N-type GaN layer, low temperature stress release
Layer, multiple quantum well layer, electronic barrier layer, p-type GaN layer and p-type ohmic contact layer, the multiple quantum well layer include several layers
Folded trap barrier layer, the trap barrier layer includes the luminous well layer of InGaN of stacked above one another, shine trap protective layer and GaN barrier layer, is leaned on
GaN barrier layer in the trap barrier layer of the nearly electronic barrier layer is contacted with the electronic barrier layer, and the luminous trap protective layer includes
AlInN layers, the InGaN shines well layer as the luminous well layer of low temperature InGaN, and the luminous trap protective layer is the luminous trap protection of medium temperature
Layer, the GaN barrier layer are high temperature GaN barrier layer.
Optionally, described AlInN layers is Al1-xInxN layers, 0.1 < x < 0.5.
Optionally, the InGaN shine well layer with a thickness of 2~4nm, described AlInN layers with a thickness of 0.5~2nm, institute
State GaN barrier layer with a thickness of 6~12nm.
Optionally, the luminous trap protective layer further includes AlN layers, and described AlN layers is located at described AlInN layers and the GaN
Between barrier layer, described AlN layers is medium temperature AlN layers.
Optionally, described AlN layers with a thickness of 0.5~2nm.
Optionally, the trap barrier layer further includes the trap transition zone that shines, and the luminous well layer of the InGaN is located at the luminous trap mistake
It crosses between layer and the luminous trap protective layer, luminous trap transition zone and institute in the trap barrier layer of the low temperature stress release layer
The contact of low temperature stress release layer is stated, the luminous trap transition zone is the luminous trap transition zone of GaN or the luminous trap transition zone of AlInN.
Optionally, when the luminous trap transition zone shines trap transition zone for AlInN, the luminous trap transition zone is Al1- yInyN layers, 0.1 < y < 0.5.
Optionally, the growth thickness of the luminous trap transition zone is 0.5~2nm.
Second aspect provides a kind of preparation method of GaN base light emitting epitaxial wafer, which comprises
Substrate is provided；
It is sequentially deposited buffer layer, undoped GaN layer, N-type GaN layer, low temperature stress release layer, Multiple-quantum over the substrate
Well layer, electronic barrier layer, p-type GaN layer and p-type ohmic contact layer；
The multiple quantum well layer includes the trap barrier layer of several stackings, and the trap barrier layer includes that the InGaN of stacked above one another shines
Well layer, shine trap protective layer and GaN barrier layer, GaN barrier layer and the electronics in the trap barrier layer of the electronic barrier layer
Barrier layer contact, the luminous trap protective layer includes AlInN layers, and the growth temperature of the luminous well layer of the InGaN is lower than the hair
The growth temperature of ligh trap protective layer, the growth temperature of the luminous trap protective layer are lower than the growth temperature of the GaN barrier layer.
Optionally, the growth temperature of the luminous well layer of the InGaN is 700 DEG C~800 DEG C, described AlInN layers of growth temperature
Degree is 750 DEG C~850 DEG C, and the growth temperature of the GaN barrier layer is 850 DEG C~950 DEG C.
Technical solution provided in an embodiment of the present invention has the benefit that by multiple quantum well layer include several stackings
Trap barrier layer, trap barrier layer include stacked above one another InGaN shine well layer, shine trap protective layer and GaN barrier layer, due to InGaN
Luminous well layer is the luminous well layer of low temperature InGaN, and the trap protective layer that shines is the luminous trap protective layer of medium temperature, and GaN barrier layer is the base high temperature GaN
The growth temperature of layer, the i.e. luminous well layer of InGaN is lower than the growth temperature for the trap protective layer that shines, the growth temperature for the trap protective layer that shines
Lower than the growth temperature of GaN barrier layer, the growth temperature of the trap protective layer that shines in this way shines well layer and GaN barrier layer between InGaN
Between growth temperature, during the growth process, the low temperature for the well layer that can shine from InGaN is gradually transitions the high temperature of GaN barrier layer
Degree, but due to shine trap protective layer include AlInN layers, the lattice constant of AlInN between InGaN and the lattice constant of GaN,
And AlInN can obtain higher crystal quality under lower growth temperature, therefore, this is conducive to improve the interface between trap base
Crystal quality；Also, under the protection for the trap protective layer that shines, it can reduce or avoid the In in InGaN Quantum Well to be analysed
Out, improve In component in Quantum Well is incorporated to content, improves the combined efficiency of carrier.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is a kind of flow chart of the preparation method of GaN base light emitting epitaxial wafer provided in an embodiment of the present invention；
Fig. 2 is a kind of flow chart of the preparation method of GaN base light emitting epitaxial wafer provided in an embodiment of the present invention；
Fig. 3 is a kind of structural schematic diagram of GaN base light emitting epitaxial wafer provided in an embodiment of the present invention；
Fig. 4 is the structural schematic diagram of the trap barrier layer of the first structure provided in an embodiment of the present invention；
Fig. 5 is the structural schematic diagram of the trap barrier layer of second of structure provided in an embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
Fig. 1 shows a kind of preparation method of GaN base light emitting epitaxial wafer provided in an embodiment of the present invention.Referring to figure
1, this method process includes the following steps.
Step 101 provides substrate.
Step 102 is sequentially deposited buffer layer on substrate, is undoped GaN layer, N-type GaN layer, low temperature stress release layer, more
Quantum well layer, electronic barrier layer, p-type GaN layer and p-type ohmic contact layer.
Wherein, multiple quantum well layer includes the trap barrier layer of several stackings.Trap barrier layer includes the luminous trap of InGaN of stacked above one another
Layer, shine trap protective layer and GaN barrier layer.GaN barrier layer in the trap barrier layer of electronic barrier layer connects with electronic barrier layer
Touching.The trap protective layer that shines includes AlInN layers.The growth temperature of the luminous well layer of InGaN is lower than the growth temperature for the trap protective layer that shines,
The growth temperature of luminous trap protective layer is lower than the growth temperature of GaN barrier layer.
The embodiment of the present invention includes the trap barrier layer of several stackings by multiple quantum well layer, and trap barrier layer includes stacked above one another
InGaN shine well layer, shine trap protective layer and GaN barrier layer, since the shine growth temperature of well layer of InGaN is lower than the trap that shines
The growth temperature of the growth temperature of protective layer, the trap protective layer that shines is lower than the growth temperature of GaN barrier layer, and shine trap protective layer in this way
Growth temperature shine between well layer and the growth temperature of GaN barrier layer between InGaN, during the growth process, can be sent out from InGaN
The low temperature of ligh trap layer is gradually transitions the high-temperature of GaN barrier layer, and since the trap protective layer that shines includes AlInN layers, AlInN's
Lattice constant is between InGaN and the lattice constant of GaN, and AlInN can obtain higher crystalline substance under lower growth temperature
Weight, therefore, this is conducive to the crystal quality for improving the interface between trap base；Also, under the protection for the trap protective layer that shines,
It can reduce or avoid the In in InGaN Quantum Well to be precipitated, improve the content that is incorporated to of In component in Quantum Well, improve and carry
Flow the combined efficiency of son.
Fig. 2 shows a kind of preparation methods of GaN base light emitting epitaxial wafer provided in an embodiment of the present invention.Referring to figure
2, this method process includes the following steps.
Step 201 provides substrate.
Illustratively, substrate can be (0001) crystal orientation Sapphire Substrate (Al2O3)。
Step 202 makes annealing treatment substrate.
Wherein, annealing mode depends on the growth pattern of buffer layer.When using PVD (Physical Vapor
Deposition, physical vapour deposition (PVD)) method buffer layer when, annealing mode includes: that substrate is placed into PVD equipment
Reaction chamber in, and reaction chamber is vacuumized, starts to carry out heat temperature raising to Sapphire Substrate while vacuumizing.When this
Bottom vacuum is evacuated to lower than 1*10-7When Torr, heating temperature is stablized at 350~750 DEG C, Sapphire Substrate is toasted, dries
The roasting time is 2~12 minutes.When using MOCVD, (Metal-organic Chemical Vapor Deposition, metal have
Machine compound chemical gaseous phase deposition) method buffer layer when, annealing mode includes: that substrate is placed into MOCVD device
Reaction chamber in, then made annealing treatment 10 minutes in hydrogen atmosphere, clean substrate surface, annealing temperature is at 1000 DEG C and 1200
Between DEG C, nitrogen treatment is then carried out.
Step 203, on substrate buffer layer.
Wherein, buffer layer can be GaN buffer layer, be also possible to AlN buffer layer.
When buffer layer is GaN buffer layer, using MOCVD method grown buffer layer, comprising: firstly, by MOCVD device
Reaction cavity temperature is adjusted to 400 DEG C -600 DEG C, and the thick GaN buffer layer of growth 15 to 35nm, growth pressure section is
200Torr-600Torr.Secondly, buffer layer in-situ annealing is handled, temperature is at 1000 DEG C -1200 DEG C, and the time was at 5 minutes to 10 points
Between clock, pressure 200Torr-600Torr.
When buffer layer is AlN buffer layer, using PVD method grown buffer layer, comprising: will be in the reaction chamber of PVD equipment
Temperature is adjusted to 400-700 DEG C, adjustment sputtering power be 3000~5000W, adjustment pressure be 1~10torr, grow 15 to
The AlN buffer layer of 35nm thickness.
It should be noted that undoped GaN layer, N-type GaN layer in epitaxial layer, low temperature stress release layer, multiple quantum wells
Layer, electronic barrier layer, p-type GaN layer and p-type ohmic contact layer can be grown using MOCVD method.
Step 204 deposits undoped GaN layer on the buffer layer.
Illustratively, the growth temperature of undoped GaN layer is 1000 DEG C -1100 DEG C, and growth thickness is at 0.8 to 1.2 micron
Between, growth pressure is in 100Torr between 450Torr.
Step 205, the deposited n-type GaN layer in undoped GaN layer.
Illustratively, the thickness of N-type GaN layer is between 1-3 microns, and growth temperature is at 1000 DEG C -1200 DEG C, growth pressure
In 100Torr between 300Torr, Si doping concentration is 1018cm-3-1019cm-3Between.
Step 206, the deposit low temperature stress release layer in N-type GaN layer.
Illustratively, low temperature stress release layer can for insertion InGaN GaN layer, low temperature stress release layer with a thickness of
150-300nm, growth temperature are 800~900 DEG C, and growth pressure is 200~400Torr.
Step 207 deposits multiple quantum well layer on low temperature stress release layer.
Wherein, multiple quantum well layer includes the trap barrier layer of several stackings.The embodiment of the present invention provides the trap barrier layer of two kinds of structures.
In the first structure, trap barrier layer includes the luminous well layer of InGaN of stacked above one another, shine trap protective layer and the base GaN
Layer.The luminous well layer of InGaN in the trap barrier layer of low temperature stress release layer is contacted with low temperature stress release layer.It is hindered close to electronics
GaN barrier layer in the trap barrier layer of barrier is contacted with electronic barrier layer.The growth temperature of the luminous well layer of InGaN is lower than the trap protection that shines
The growth temperature of the growth temperature of layer, the trap protective layer that shines is lower than the growth temperature of GaN barrier layer.
In second of structure, trap barrier layer includes the luminous trap transition zone of stacked above one another, the luminous well layer of InGaN, shine trap guarantor
Sheath and GaN barrier layer.Luminous trap transition zone in the trap barrier layer of low temperature stress release layer connects with low temperature stress release layer
Touching.GaN barrier layer in the trap barrier layer of electronic barrier layer is contacted with electronic barrier layer.The growth temperature of the luminous well layer of InGaN
Lower than the growth temperature of luminous trap protective layer, the growth temperature for the trap protective layer that shines is lower than the growth temperature of GaN barrier layer.
The trap barrier layer of second of structure increases luminous trap transition zone than the trap barrier layer of the first structure.Shine trap transition zone
For the transition of stress between barrier layer to well layer, it is incorporated to conducive to In in luminous well layer.Illustratively, luminous trap transition zone is
The luminous trap transition zone of GaN or the luminous trap transition zone of AlInN.
Illustratively, when luminous trap transition zone shines trap transition zone for AlInN, the trap transition zone that shines is Al1-yInyN
Layer, 0.1 < y < 0.5.
Wherein, the trap protective layer that shines includes AlInN layers.Due to InGaN shine well layer growth temperature be lower than shine trap protect
The growth temperature of the growth temperature of sheath, the trap protective layer that shines is lower than the growth temperature of GaN barrier layer, and shine trap protective layer in this way
Growth temperature shines between well layer and the growth temperature of GaN barrier layer between InGaN, during the growth process, can shine from InGaN
The low temperature of well layer is gradually transitions the high-temperature of GaN barrier layer, and since the trap protective layer that shines includes AlInN layers, the crystalline substance of AlInN
Lattice constant is between InGaN and the lattice constant of GaN, and AlInN can obtain higher crystal under lower growth temperature
Quality, therefore, this is conducive to the crystal quality for improving the interface between trap base；Also, under the protection for the trap protective layer that shines, energy
It enough reduces or avoids the In in InGaN Quantum Well to be precipitated, improve the content that is incorporated to of In component in Quantum Well, improve current-carrying
The combined efficiency of son.
Illustratively, the embodiment of the present invention provides the luminous trap protective layer of two kinds of structures.The luminous trap of the first structure is protected
Sheath is AlInN layers；The luminous trap protective layer of second of structure includes AlInN layers and AlN layers, AlN layers be located at AlInN layer and
Between GaN barrier layer.
When the trap protective layer that shines only includes AlInN layers, the Al component with preferable crystal quality and certain content, Al group
Divide the crystal quality that can be used for improving this layer and adjustment bandwidth.Compared to the luminous trap protective layer of the first structure,
AlN layers are increased in the luminous trap protective layer of two kinds of structures, AlN layers can provide the content of more high Al contents, can be further
Enhance multiple quantum wells interface quality.
Illustratively, it shines in trap protective layer, AlInN layers are Al1-xInxN layers, 0.1 < x < 0.5.Further, the model of x
Enclose is 0.1~0.2.Especially as x=0.13, Al is obtained0.87In0.13The lattice constant and GaN of N exactly matches, at this time the layer
Crystal quality is best.
Due to the notable difference of N-P doping efficiency and electron-hole mobility, it is grown on the luminous trap on luminous well layer both sides
Transition zone and luminous trap protective layer, due to AlInN and AlN layers of presence, i.e. Al component is incorporated to, and can be improved luminous well layer two
Electronics preferably can be confined to the well layer participation photoreactivation that shines under LED current driving by the forbidden bandwidth of side.
About growth temperature, illustratively, the growth temperature for the trap transition zone that shines is 750 DEG C~900 DEG C, and InGaN shines
The growth temperature of well layer is 700 DEG C~800 DEG C, and AlInN layers of growth temperature is 750 DEG C~850 DEG C, AlN layers of growth temperature
It is 800 DEG C~900 DEG C, the growth temperature of GaN barrier layer is 850 DEG C~950 DEG C.
About growth pressure, illustratively, the growth pressure for the trap transition zone that shines is 100torr~500tor, InGaN hair
The growth pressure of ligh trap layer is 100torr~500torr, and AlInN layers of growth pressure is 50torr~00torr, AlN layers
Growth pressure is 50torr~500torr, and the growth pressure of GaN barrier layer is 100torr~500torr.
About thickness, illustratively, the growth thickness for the trap transition zone that shines is 0.5~2nm, the thickness of the luminous well layer of InGaN
Degree is 2~4nm, AlInN layers with a thickness of 0.5~2nm, AlN layers with a thickness of 0.5~2nm, GaN barrier layer with a thickness of 6~
12nm。
Illustratively, the overall thickness of trap protective layer of shining can be less than or equal to 2nm, the overall thickness of trap barrier layer be 10nm~
18nm。
Step 208 deposits electronic barrier layer on multiple quantum well layer.
Illustratively, electronic barrier layer is p-type AlGaN layer, the growth temperature of electronic barrier layer 850 DEG C with 1050 DEG C it
Between, growth pressure is between 100Torr and 500Torr.The thickness of electronic barrier layer is in 20nm between 100nm.
Step 209 deposits p-type GaN layer on electronic barrier layer.
Illustratively, the growth temperature of p-type GaN layer is between 750 DEG C and 1080 DEG C, growth pressure be 200Torr with
Between 600Torr, growth thickness is in 50nm between 200nm.
Step 210 deposits p-type ohmic contact layer in p-type GaN layer.
Illustratively, p-type ohmic contact layer with a thickness of 0.5nm between 10nm, growth temperature section is 850 DEG C-
1050 DEG C, growth pressure section is 100Torr-600Torr.
Illustratively, after the growth of p-type ohmic contact layer, the reaction cavity temperature of MOCVD device is reduced, in nitrogen
It is made annealing treatment in atmosphere, annealing temperature section is 650 DEG C -850 DEG C, is made annealing treatment 5 to 15 minutes, and room temperature is down to, and completes extension
Growth.
Fig. 3 shows a kind of GaN base light emitting epitaxial wafer provided in an embodiment of the present invention, the LED epitaxial
Piece can by Fig. 1 or Fig. 2 shows method be prepared.Referring to Fig. 3, the LED epitaxial slice include: substrate 1, with
And buffer layer 2, undoped GaN layer 3, n-type doping GaN layer 4, the low temperature stress release layer 5, volume being sequentially deposited on substrate 1
Sub- well layer 6, electronic barrier layer 7, p-type GaN layer 8 and p-type ohmic contact layer 9.Multiple quantum well layer 6 includes the trap barrier layer of several stackings
60, trap barrier layer 60 includes the luminous well layer 62 of InGaN of stacked above one another, shine trap protective layer 63 and GaN barrier layer 64.Close to electricity
GaN barrier layer 63 in the trap barrier layer 60 on sub- barrier layer 7 is contacted with electronic barrier layer 7.The trap protective layer 63 that shines includes AlInN layers
631, InGaN luminous well layer 62 are the luminous well layer of low temperature InGaN, and the trap protective layer 63 that shines is the luminous trap protective layer of medium temperature, and GaN is built
Layer 64 is high temperature GaN barrier layer.
Illustratively, the embodiment of the present invention provides the trap barrier layer 60 of two kinds of structures.
In the first structure, referring to fig. 4, trap barrier layer 60 includes the luminous well layer 62 of InGaN of stacked above one another, shine trap protection
63 and GaN of layer barrier layer 64.The luminous well layer 62 of InGaN and low temperature stress in the trap barrier layer 60 of low temperature stress release layer 5
Releasing layer 5 contacts.GaN barrier layer 64 in the trap barrier layer 60 of electronic barrier layer 7 is contacted with electronic barrier layer 7.InGaN shines
The growth temperature of well layer 62 is lower than the growth temperature for the trap protective layer 63 that shines, and the growth temperature for the trap protective layer 63 that shines is lower than GaN
The growth temperature of barrier layer 64.
In second of structure, referring to Fig. 5, trap barrier layer 60 includes the luminous trap transition zone 61 of stacked above one another, the luminous trap of InGaN
Layer 62, shine trap protective layer 63 and GaN barrier layer 64.Luminous trap transition in the trap barrier layer 60 of low temperature stress release layer 5
Layer 61 is contacted with low temperature stress release layer 5.GaN barrier layer 64 and electronic barrier layer 7 in the trap barrier layer 60 of electronic barrier layer 7
Contact.The growth temperature of the luminous well layer 62 of InGaN is lower than the growth temperature for the trap protective layer 63 that shines, the life for the trap protective layer 63 that shines
Long temperature is lower than the growth temperature of GaN barrier layer 64.
The trap barrier layer 60 of second of structure increases luminous trap transition zone 61 than the trap barrier layer 60 of the first structure.Shine trap
Transition zone 61 is incorporated to for transition of stress between barrier layer to well layer conducive to In in luminous well layer.Illustratively, shine trap
Transition zone 61 is the luminous trap transition zone of GaN or the luminous trap transition zone of AlInN.
Illustratively, when luminous trap transition zone 61 shines trap transition zone for AlInN, the trap transition zone 61 that shines is Al1- yInyN layers, 0.1 < y < 0.5.Such as y=0.2.
Wherein, the trap protective layer 63 that shines includes AlInN layer 631.Due to InGaN shine well layer 62 growth temperature lower than hair
The growth temperature of the growth temperature of ligh trap protective layer 63, the trap protective layer 63 that shines is lower than the growth temperature of GaN barrier layer 64, sends out in this way
The growth temperature of ligh trap protective layer 63 shines between well layer 62 and the growth temperature of GaN barrier layer 64 between InGaN, in growth course
In, the low temperature for the well layer 62 that can shine from InGaN is gradually transitions the high-temperature of GaN barrier layer 64, and due to the trap protection that shines
Layer 63 include AlInN layer 631, the lattice constant of AlInN between InGaN and the lattice constant of GaN, and AlInN can compared with
Higher crystal quality is obtained under low growth temperature, therefore, this is conducive to the crystal quality for improving the interface between trap base；And
And under the protection for the trap protective layer 63 that shines, it can reduce or avoid the In in InGaN Quantum Well 62 to be precipitated, improve
In component is incorporated to content in Quantum Well, improves the combined efficiency of carrier.
Illustratively, the embodiment of the present invention provides the luminous trap protective layer 63 of two kinds of structures.Referring to Fig. 3, the first structure
Luminous trap protective layer 63 be AlInN layer 631；Referring to Fig. 5, the luminous trap protective layer 63 of second of structure includes AlInN layer 631
With AlN layer 632, AlN layer 632 is between AlInN layer 631 and GaN barrier layer 64.During AlN layer 632 and AlInN layer 631 be respectively
Warm AlN layers and medium temperature AlInN layers.
When the trap protective layer 63 that shines only includes AlInN layer 631, the Al group with preferable crystal quality and certain content
Point, Al component can be used for improving the crystal quality and adjustment bandwidth of this layer.Luminous trap compared to the first structure is protected
Sheath 63 increases AlN layer 632 in the luminous trap protective layer 63 of second of structure, and AlN layer 632 can provide more high Al contents
Content, multiple quantum wells interface quality can be further enhanced.
Illustratively, it shines in trap protective layer 63, AlInN layer 631 is Al1-xInxN layers, 0.1 < x < 0.5.Such as x=
0.2.Further, the range of x is 0.1~0.2.Especially as x=0.13, Al is obtained0.87In0.13The lattice constant of N and
GaN exact matching, the layer crystal weight is best at this time.
Due to the notable difference of N-P doping efficiency and electron-hole mobility, it is grown on the luminous trap on luminous well layer both sides
Transition zone and luminous trap protective layer, due to AlInN and AlN layers of presence, i.e. Al component is incorporated to, and can be improved luminous well layer two
Electronics preferably can be confined to the well layer participation photoreactivation that shines under LED current driving by the forbidden bandwidth of side.
About growth temperature, illustratively, the growth temperature for the trap transition zone 61 that shines is 750 DEG C~900 DEG C, InGaN hair
The growth temperature of ligh trap layer 62 is 700 DEG C~800 DEG C, and the growth temperature of AlInN layer 631 is 750 DEG C~850 DEG C, AlN layer 632
Growth temperature be 800 DEG C~900 DEG C, the growth temperature of GaN barrier layer 64 is 850 DEG C~950 DEG C.
About thickness, illustratively, the growth thickness for the trap transition zone 61 that shines is 0.5~2nm, and InGaN shines well layer 62
With a thickness of 2~4nm, AlInN layer 631 with a thickness of 0.5~2nm, AlN layer 632 with a thickness of 0.5~2nm, GaN barrier layer 64
With a thickness of 6~12nm.
Since the forbidden bandwidth for the trap protective layer 63 that shines is higher than the forbidden bandwidth of GaN barrier layer 64, shine trap protective layer
The injection efficiency of the 63 too thick electrons and holes that can reduce multiple quantum wells, shine trap protective layer 63 too it is thin then to the covering of well layer not
It is enough.Illustratively, the overall thickness of luminous trap protective layer 63 can be less than or equal to 2nm.
Illustratively, the overall thickness of trap barrier layer 60 is 10nm~18nm.For example, shine trap transition zone 61 with a thickness of
1.0nm, InGaN shine well layer 62 thickness can be 3.0nm, shine trap protective layer 63 in AlInN layer 631 with a thickness of
1.5nm, AlN layer 632 with a thickness of 1.0nm, GaN barrier layer 64 with a thickness of 8nm.
The embodiment of the present invention includes the trap barrier layer of several stackings by multiple quantum well layer, and trap barrier layer includes stacked above one another
InGaN shine well layer, shine trap protective layer and GaN barrier layer, since the InGaN well layer that shines is that low temperature InGaN shines well layer,
The trap protective layer that shines is the luminous trap protective layer of medium temperature, and GaN barrier layer is high temperature GaN barrier layer, the i.e. growth temperature of the luminous well layer of InGaN
Lower than the growth temperature of luminous trap protective layer, the growth temperature for the trap protective layer that shines is lower than the growth temperature of GaN barrier layer, sends out in this way
The growth temperature of ligh trap protective layer shines between well layer and the growth temperature of GaN barrier layer between InGaN, during the growth process, energy
It is enough to be gradually transitions the high-temperature of GaN barrier layer from the shine low temperature of well layer of InGaN, and since the trap protective layer that shines includes
AlInN layers, the lattice constant of AlInN is between InGaN and the lattice constant of GaN, and AlInN can be in lower growth temperature
Under obtain higher crystal quality, therefore, this be conducive to improve trap build between interface crystal quality；Also, in luminous trap
Under the protection of protective layer, it can reduce or avoid the In in InGaN Quantum Well to be precipitated, improve In component in Quantum Well
It is incorporated to content, improves the combined efficiency of carrier.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of GaN base light emitting epitaxial wafer, which is characterized in that the LED epitaxial slice includes:
It is substrate, the buffer layer being sequentially deposited over the substrate, undoped GaN layer, N-type GaN layer, low temperature stress release layer, more
Quantum well layer, electronic barrier layer, p-type GaN layer and p-type ohmic contact layer, the multiple quantum well layer include the trap of several stackings
Barrier layer, the trap barrier layer includes the luminous well layer of InGaN of stacked above one another, shine trap protective layer and GaN barrier layer, close to described
GaN barrier layer in the trap barrier layer of electronic barrier layer is contacted with the electronic barrier layer, and the luminous trap protective layer includes AlInN
Layer, the InGaN shines well layer as the luminous well layer of low temperature InGaN, and the luminous trap protective layer is the luminous trap protective layer of medium temperature, institute
Stating GaN barrier layer is high temperature GaN barrier layer.
2. epitaxial wafer according to claim 1, which is characterized in that described AlInN layers is Al1-xInxN layers, 0.1 < x < 0.5.
3. epitaxial wafer according to claim 2, which is characterized in that the InGaN shine well layer with a thickness of 2~4nm, institute
State AlInN layers with a thickness of 0.5~2nm, the GaN barrier layer with a thickness of 6~12nm.
4. epitaxial wafer according to claim 1, which is characterized in that the luminous trap protective layer further includes AlN layers, described
AlN layers between described AlInN layers and the GaN barrier layer, described AlN layers be medium temperature AlN layers.
5. epitaxial wafer according to claim 4, which is characterized in that described AlN layers with a thickness of 0.5~2nm.
6. epitaxial wafer according to claim 1, which is characterized in that the trap barrier layer further includes the trap transition zone that shines, described
InGaN shines well layer between the luminous trap transition zone and the luminous trap protective layer, close to the low temperature stress release
Luminous trap transition zone in the trap barrier layer of layer is contacted with the low temperature stress release layer, and the luminous trap transition zone shines for GaN
Trap transition zone or the luminous trap transition zone of AlInN.
7. epitaxial wafer according to claim 6, which is characterized in that when the luminous trap transition zone is the luminous trap mistake of AlInN
When crossing layer, the luminous trap transition zone is Al1-yInyN layers, 0.1 < y < 0.5.
8. epitaxial wafer according to claim 7, which is characterized in that the growth thickness of the luminous trap transition zone be 0.5~
2nm。
9. a kind of preparation method of GaN base light emitting epitaxial wafer, which is characterized in that the described method includes:
Substrate is provided；
It is sequentially deposited buffer layer, undoped GaN layer, N-type GaN layer, low temperature stress release layer, multiple quantum wells over the substrate
Layer, electronic barrier layer, p-type GaN layer and p-type ohmic contact layer；
The multiple quantum well layer includes the trap barrier layer of several stackings, the trap barrier layer include stacked above one another InGaN shine well layer,
Shine trap protective layer and GaN barrier layer, GaN barrier layer and the electronic blocking in the trap barrier layer of the electronic barrier layer
Layer contact, the luminous trap protective layer includes AlInN layers, and the growth temperature of the luminous well layer of the InGaN is lower than the luminous trap
The growth temperature of protective layer, the growth temperature of the luminous trap protective layer are lower than the growth temperature of the GaN barrier layer.
10. according to the method described in claim 9, the growth temperature of well layer is 700 DEG C it is characterized in that, the InGaN shines
~800 DEG C, AlInN layers of the growth temperature is 750 DEG C~850 DEG C, and the growth temperature of the GaN barrier layer is 850 DEG C~950
℃。
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