CN109860356A - A kind of GaN base light emitting epitaxial wafer and preparation method thereof - Google Patents
A kind of GaN base light emitting epitaxial wafer and preparation method thereof Download PDFInfo
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Abstract
The invention discloses a kind of GaN base light emitting epitaxial wafers and preparation method thereof, belong to GaN base light emitting field.The LED epitaxial slice includes: substrate, the buffer layer being sequentially deposited over the substrate, undoped GaN layer, n-type doping GaN layer, low temperature stress release layer, multiple quantum well layer, low temperature p-type GaN layer, electronic barrier layer, high temperature p-type GaN layer, and p-type contact layer, the multiple quantum well layer includes the trap barrier layer of several stackings, the trap barrier layer includes quantum well layer and quantum barrier layer, the quantum well layer includes the first InGaN layer, the quantum barrier layer includes the first AlInGaN layers of stacked above one another, GaN layer, and the 2nd AlInGaN layers, quantum well layer in the trap barrier layer of the low temperature stress release layer is contacted with the low temperature stress release layer.
Description
Technical field
The present invention relates to GaN base light emitting field, in particular to a kind of GaN base light emitting epitaxial wafer and its system
Preparation Method.
Background technique
GaN (gallium nitride) base LED (Light Emitting Diode, light emitting diode) generally comprises epitaxial wafer and outside
Prolong the electrode of on piece preparation.Epitaxial wafer generally includes: buffer layer, the undoped GaN of substrate and stacked above one another on substrate
Layer, N-type GaN layer, MQW (Multiple Quantum Well, multiple quantum wells) layer, electronic barrier layer, p-type GaN layer and contact
Layer.When there is electric current to inject GaN base LED, the hole of the p type island regions such as the electronics of the N-type regions such as N-type GaN layer and p-type GaN layer enters MQW
Active area and compound, sending visible light.Wherein, the week of InGaN well layer and GaN barrier layer alternating growth is usually used in mqw layer
Phase structure.
In the implementation of the present invention, the inventor finds that the existing technology has at least the following problems: InGaN well layer and
There are biggish lattice mismatches between GaN barrier layer, very big by being formed at the heterojunction boundary of InGaN well layer and GaN barrier layer
Stress, and then generate very strong piezoelectric polarization.Piezoelectric polarization will cause quantum confined stark effect, i.e., generate in Quantum Well
Enabled band run-off the straight is changed the energy level of conduction band and valence band, reduces carrier transition energy by built in field, the built in field,
Also change the bound state wave function of carrier in energy band, so that electrons and holes wave function space separates, reduces electron wave function
It is overlapping with hole wave functions, reduce the radiation recombination efficiency of electrons and holes.
Summary of the invention
The embodiment of the invention provides a kind of GaN base light emitting epitaxial wafers and preparation method thereof, can reduce even
It eliminates trap caused by mismatching because of traditional InGaN/GaN lattice and builds the stress that interface is formed.The technical solution is as follows:
In a first aspect, providing a kind of GaN base light emitting epitaxial wafer, the LED epitaxial slice includes:
Substrate, the buffer layer being sequentially deposited over the substrate, undoped GaN layer, n-type doping GaN layer, low temperature stress are released
Put layer, multiple quantum well layer, low temperature p-type GaN layer, electronic barrier layer, high temperature p-type GaN layer and p-type contact layer, the Multiple-quantum
Well layer includes the trap barrier layer of several stackings, and the trap barrier layer includes quantum well layer and quantum barrier layer, and the quantum well layer includes the
One InGaN layer, the quantum barrier layer includes the first AlInGaN layers of stacked above one another, GaN layer and the 2nd AlInGaN layers, is leaned on
Quantum well layer in the trap barrier layer of the nearly low temperature stress release layer is contacted with the low temperature stress release layer.
Optionally, the quantum well layer is low temperature quantum well layer, the described first AlInGaN layers and the 2nd AlInGaN
Layer is low temperature AI InGaN layer, and the GaN layer is high-temperature gan layer.
Optionally, the quantum well layer further includes InN layers and the second InGaN layer, and described InN layers is located at described first
Between InGaN layer and second InGaN layer, the first InGaN in quantum well layer that is contacted with the low temperature stress release layer
Layer is contacted with the low temperature stress release layer.
Optionally, first InGaN layer and second InGaN layer are Inx1Ga1-x1N layers, described first
AlInGaN layers and the described 2nd AlInGaN layers be AlyInx2Ga1-x2-yN layers, 0.1≤y≤0.8,0.1≤x1≤0.3,0.05
≤x2≤0.2。
Optionally, the thickness of first InGaN layer and second InGaN layer isIt is InN layers described
With a thickness ofDescribed first AlInGaN layers and the described 2nd AlInGaN layers of thickness isIt is described
GaN layer with a thickness ofThe quantity of the trap barrier layer is 6~10.
Second aspect provides a kind of preparation method of GaN base light emitting epitaxial wafer, which comprises
Substrate is provided；
It is sequentially deposited buffer layer, undoped GaN layer, n-type doping GaN layer, low temperature stress release layer, more over the substrate
Quantum well layer, low temperature p-type GaN layer, electronic barrier layer, high temperature p-type GaN layer and p-type contact layer, the multiple quantum well layer packet
The trap barrier layer of several stackings is included, the trap barrier layer includes quantum well layer and quantum barrier layer, and the quantum well layer includes the first InGaN
Layer, the quantum barrier layer includes the first AlInGaN the layer of stacked above one another, GaN layer and the 2nd AlInGaN layers, close described low
Quantum well layer in the trap barrier layer of warm stress release layer is contacted with the low temperature stress release layer.
Optionally, the quantum well layer, the described first AlInGaN layers and the described 2nd AlInGaN layers of growth temperature phase
Together, the growth temperature of the GaN layer is 100~150 DEG C higher than the growth temperature of the quantum well layer.
Optionally, the quantum well layer further includes InN layers and the second InGaN layer, and described InN layers is located at described first
Between InGaN layer and second InGaN layer, the first InGaN in quantum well layer that is contacted with the low temperature stress release layer
Layer is contacted with the low temperature stress release layer.
Optionally, first InGaN layer and second InGaN layer are Inx1Ga1-x1N layers, described first
AlInGaN layers and the described 2nd AlInGaN layers be AlyInx2Ga1-x2-yN layers, 0.1≤y≤0.8,0.1≤x1≤0.3,0.05
≤x2≤0.2。
Optionally, the thickness of first InGaN layer and second InGaN layer isIt is InN layers described
With a thickness ofDescribed first AlInGaN layers and the described 2nd AlInGaN layers of thickness isInstitute
State GaN layer with a thickness ofThe quantity of the trap barrier layer is 6~10.
Technical solution provided in an embodiment of the present invention has the benefit that by multiple quantum well layer include several stackings
Trap barrier layer, and each trap barrier layer includes quantum well layer and quantum barrier layer, and quantum well layer includes the first InGaN layer, quantum barrier layer
The first AlInGaN layers including stacked above one another, GaN layer and the 2nd AlInGaN layers；In this way, GaN layer is located at the first AlInGaN
Layer and the 2nd is between AlInGaN layers, the first AlInGaN layers and the 2nd AlInGaN layers respectively with the first InGaN in quantum well layer
Layer contact；Since the lattice of quaternary alloy AlInGaN is between the lattice of InGaN and the lattice of GaN, InGaN with
Quaternary alloy AlInGaN is introduced between GaN, can reduce trap caused by even being eliminated because of traditional InGaN/GaN lattice mismatch
The stress that interface is formed is built, stress bring piezoelectric polarization is reduced to reduce built in field effect and keeps normal energy band,
It is overlapping with hole wave functions to improve electron wave function, improves the radiation recombination efficiency of electrons and holes.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is a kind of structural schematic diagram of GaN base light emitting epitaxial wafer provided in an embodiment of the present invention；
Fig. 2 is the energy band and wave function schematic diagram of tradition InGaN/GaN multiple quantum well layer provided in an embodiment of the present invention；
Fig. 3 is the Multiple-quantum provided in an embodiment of the present invention between InGaN well layer and GaN barrier layer after introducing AlInGaN
The energy band and wave function schematic diagram of well layer；
Fig. 4 is the structural schematic diagram of multiple quantum well layer provided in an embodiment of the present invention；
Fig. 5 is the energy band and wave provided in an embodiment of the present invention that the multiple quantum well layer after InN is inserted between InGaN well layer
Function schematic diagram；
Fig. 6 is a kind of flow chart of the preparation method of GaN base light emitting epitaxial wafer provided in an embodiment of the present invention；
Fig. 7 is a kind of flow chart of the preparation method of GaN base light emitting epitaxial wafer provided in an embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
Fig. 1 shows a kind of GaN base light emitting epitaxial wafer provided in an embodiment of the present invention.Referring to Fig. 1, this luminous two
Pole pipe epitaxial wafer includes: substrate 1 and the buffer layer being sequentially deposited on substrate 12, undoped GaN layer 3, n-type doping GaN layer
4, low temperature stress release layer 5, multiple quantum well layer 6, low temperature p-type GaN layer 7, electronic barrier layer 8, high temperature p-type GaN layer 9 and p-type connect
Contact layer 10.
Multiple quantum well layer 6 includes the trap barrier layer 60 of several stackings.Trap barrier layer 60 includes quantum well layer 61 and quantum barrier layer 62.
Quantum well layer 61 includes the first InGaN layer 61a.Quantum barrier layer 62 includes the first AlInGaN layers of 62a, GaN layer of stacked above one another
62b and the 2nd AlInGaN layers of 62c.Quantum well layer 61 in the trap barrier layer 60 of low temperature stress release layer 5 is answered with low temperature
Power releasing layer 5 contacts.
It include the trap barrier layer 60 of several stackings by multiple quantum well layer 6, and each trap barrier layer 60 includes 61 He of quantum well layer
Quantum barrier layer 62, quantum well layer 61 include the first InGaN layer 61a, and quantum barrier layer 62 includes the first AlInGaN layers of stacked above one another
62a, GaN layer 62b and the 2nd AlInGaN layers of 62c；In this way, GaN layer 62b is located at the first AlInGaN layers of 62a and second
Between AlInGaN layers of 62c, the first AlInGaN layers of 62a and the 2nd AlInGaN layers of 62c respectively with first in quantum well layer 61
InGaN layer 61a contact；Since the lattice of quaternary alloy AlInGaN is between the lattice of InGaN and the lattice of GaN,
Quaternary alloy AlInGaN is introduced between InGaN and GaN, be can reduce and even is eliminated because of traditional InGaN/GaN multiple quantum well layer
Trap caused by InGaN and GaN lattice mismatch in (i.e. the periodic structure of InGaN well layer and GaN barrier layer alternating growth) builds interface
The stress of formation reduces stress bring piezoelectric polarization, to reduce built in field effect, keeps normal energy band, improves electricity
Wavelet function is overlapping with hole wave functions, improves the radiation recombination efficiency of electrons and holes.
Further, since the effective mass of electronics is lower relative to hole, this will lead to a large amount of electronics from quantum well region overflow
To P-type layer area, especially the overflow of electronics is become apparent from the LED light emitting device under high current density, finally will lead to LED device
Part luminous efficiency greatly reduces, this especially in the luminous efficiency of high current density and Long wavelength region by serious decline
Phenomenon is known as the droop effect of LED.By introducing quaternary alloy AlInGaN between InGaN and GaN, it can reduce LED's
Droop effect.
Fig. 2 is the energy band and wave function schematic diagram of tradition InGaN/GaN multiple quantum well layer, Fig. 3 be in InGaN well layer and
The energy band and wave function schematic diagram of the multiple quantum well layer after AlInGaN are introduced between GaN barrier layer.For ease of description, in Fig. 2 and
The energy band and wave function signal at two neighboring quantum base and a Quantum Well have only been intercepted in Fig. 3.For example, in Fig. 2, tradition
The conduction band CB of InGaN/GaN multiple quantum well layer is made of three sections of horizontal lines, and higher-height two horizontal lines correspond to leading for GaN quantum base
Band, a lower height of horizontal line correspond to the conduction band of InGaN Quantum Well.Referring to fig. 2, the conduction band of traditional InGaN/GaN multiple quantum well layer
Forbidden band FB narrower width between CB and valence band VB, and entire energy band tilts.Also, hole wave functions WF1 and electron waves
Farther out, the combined efficiency of both hole and electron is lower for function WF2 space length.
In Fig. 3, the conduction band CB' of the multiple quantum well layer after introducing AlInGaN is made of five sections of horizontal lines, height highest two
The conduction band that horizontal line corresponding A lInGaN quantum is built, higher-height two horizontal lines correspond to the conduction band at GaN quantum base, highly lower
Horizontal line correspond to the conduction band of InGaN Quantum Well.Referring to Fig. 3, the conduction band CB' and valence band of the multiple quantum well layer after introducing AlInGaN
Forbidden band FB' wider width between VB', and entire energy band is relatively flat.Also, hole wave functions WF1' and electron wave function
WF2' space length is closer, and the combined efficiency of both hole and electron is higher.The conduction band built based on corresponding A lInGaN quantum, it is known that,
AlInGaN layers of introducing can also increase the effective barrier height of electronics and improve electronics in the limitation of well region, to prevent electricity
Son is because its lesser effective mass causes it from well region overflow to p type island region, and a large amount of of electronics are overflow especially under high current density
Stream, and then improve the Droop effect of LED.
Illustratively, quantum well layer 61 is low temperature quantum well layer, the first AlInGaN layers of 62a and the 2nd AlInGaN layers of 62c
It is low temperature AI InGaN layer, GaN layer 62b is high-temperature gan layer.Due to the first AlInGaN layers of 62a and second in barrier layer 62
AlInGaN layers of 62c are close to quantum well layer 61, keep the lower temperature same or similar with quantum well layer 61 that can both guarantee it
Electronics effective barrier height increases the function of preventing the overflow of electronics under high current density, and is conducive to the growth of high Al contents
And it prevents the diffusion of In in MQW and high temperature base is avoided to damage quantum well layer 61.
Illustratively, referring to fig. 4, quantum well layer 61 further includes InN layers of 61b and the second InGaN layer 61c, InN layer 61b
Between the first InGaN layer 61a and the second InGaN layer 61c.In the quantum well layer 61 contacted with low temperature stress release layer 5
One InGaN layer 61a is contacted with low temperature stress release layer 5.
By introducing InGaN/InN/InGaN well layer in multiple quantum well layer 6, electrons and holes wave letter can be not only caused
Number generates stronger local effect at trap center and forms double traps, to increase the Duplication of electrons and holes wave function and improvement
The rate of radiative recombination of electrons and holes；Also, the insertion of InN layers of 61b will lead to spontaneous red shift of wavelength and emission wavelength widened
Its spontaneous emission rate is improved to yellow light and red light region, ultimately improves the luminous efficiency of LED.
Fig. 5 is the energy band and wave function schematic diagram that the multiple quantum well layer after InN is inserted between InGaN well layer.In order to just
In description, the energy band and wave function signal at two neighboring quantum base and a Quantum Well, also, the amount have only been intercepted in Fig. 5
It is GaN barrier layer that son, which is built,.In Fig. 5, the conduction band CB " of the multiple quantum well layer after being inserted into InN is made of five sections of horizontal lines, and height is highest
Two horizontal lines correspond to the conduction band at GaN quantum base, and higher-height two horizontal lines correspond to the conduction band of InGaN Quantum Well, and height is lower
Horizontal line correspond to the conduction band of InN Quantum Well.Referring to Fig. 5, the conduction band of the multiple quantum well layer after InN is inserted between InGaN well layer
Forbidden band FB " wider width between CB " and valence band VB ", and entire energy band is relatively flat.Also, hole wave functions WF1 " and electricity
Wavelet function WF2 " space length is closer, and the combined efficiency of both hole and electron is higher.Conduction band based on corresponding InGaN Quantum Well, with
And the conduction band of corresponding InN Quantum Well, it can be seen that entire Quantum Well forms double trap effects.
Illustratively, the first InGaN layer 61a and the second InGaN layer 61c is Inx1Ga1-x1N layers, the first AlInGaN layers
62a and the 2nd AlInGaN layers of 62c is AlyInx2Ga1-x2-yN layers, 0.1≤y≤0.8,0.1≤x1≤0.3,0.05≤x2≤
0.2.By the In component and Al constituent content in limitation Quantum Well and quantum base, using LED chip made from the epitaxial wafer
Light emission luminance is best.
Illustratively, the thickness of the first InGaN layer 61a and the second InGaN layer 61c areInN layers of 61b's
With a thickness ofThe thickness of first AlInGaN layers of 62a and the 2nd AlInGaN layers of 62c isGaN layer
62b with a thickness ofThe quantity of trap barrier layer 60 is 6~10.
By InN layers of 61b, the first InGaN layer 61a and the second InGaN layer 61c use relatively thin thickness, can to avoid because
Thickness is blocked up to lead to InN layers of 61b, the first InGaN layer 61a and the 61c layers of precision decline of the second InGaN layer and InN layers of 61b are blocked up
It is unfavorable for forming the effect of the double traps of local effect realization in well region, while thickness can also be avoided too thin and influence InN layers
The realization effect of 61b, the first InGaN layer 61a and the second InGaN layer 61c.
Illustratively, the quantity of trap barrier layer 60 is 8.If the quantity of trap barrier layer 60 is too low, cannot effectively increase electronics with
The radiation recombination efficiency in hole improves the utilization rate of carrier；If the quantity of trap barrier layer 60 is too high, the interface matter of multiple quantum wells
Amount is gradually deteriorated, and the phase Segregation of InGaN trap also becomes serious.Additionally, due to lattice mismatch big between GaN and InN, with
The stress of the increase of the periodicity of multiple quantum wells, well region also will increase, and along with the release of stress, a large amount of defect dislocation is immediately
It generates, and the growth pattern of InGaN well region can also change, and be unfavorable for the radiation recombination in electronics and hole.
Illustratively, multiple quantum well layer 6 with a thickness of 100~150nm.
Illustratively, substrate 1 is Sapphire Substrate；Buffer layer 2 can be GaN layer or AlN layers, and the thickness of buffer layer 2 can
To be 15 to 35nm；The thickness of undoped GaN layer 3 can be 1~3 μm；The thickness of n-type doping GaN layer 4 can be 1~2 μm；
Low temperature stress release layer 5 can be the GaN layer inserted with InGaN/GaN periodic structure, and thickness can be 134~310nm；
The thickness of low temperature p-type GaN layer 7 can be 200-400nm；Electronic barrier layer 8 can be AlGaN layer, and thickness can be 300~
500nm；The thickness of high temperature p-type GaN layer 9 can be 100nm~300nm；P-type contact layer 10 can be GaN or InGaN layer,
Its thickness can be 50~100nm.
Fig. 6 shows a kind of preparation method of GaN base light emitting epitaxial wafer provided in an embodiment of the present invention.Referring to figure
6, this method process includes the following steps.
Step 101 provides substrate.
Step 102 is sequentially deposited buffer layer, undoped GaN layer, n-type doping GaN layer, low temperature stress release on substrate
Layer, multiple quantum well layer, low temperature p-type GaN layer, electronic barrier layer, high temperature p-type GaN layer and p-type contact layer.
Wherein, multiple quantum well layer includes the trap barrier layer of several stackings, and trap barrier layer includes quantum well layer and quantum barrier layer, quantum
Well layer includes the first InGaN layer, and quantum barrier layer includes the first AlInGaN layers of stacked above one another, GaN layer and the 2nd AlInGaN
Layer, the quantum well layer in the trap barrier layer of low temperature stress release layer are contacted with low temperature stress release layer.
LED epitaxial slice shown in fig. 1 can be prepared using the method shown in Fig. 6.
The embodiment of the present invention includes the trap barrier layer of several stackings by multiple quantum well layer, and each trap barrier layer includes Quantum Well
Layer and quantum barrier layer, quantum well layer include the first InGaN layer, and quantum barrier layer includes the first AlInGaN layers, GaN of stacked above one another
Layer and the 2nd AlInGaN layers；In this way, GaN layer is located at the first AlInGaN layers and the 2nd between AlInGaN layers, first
AlInGaN layers and the 2nd AlInGaN layers contacted respectively with the first InGaN layer in quantum well layer；Due to quaternary alloy AlInGaN
Lattice between the lattice of InGaN and the lattice of GaN, therefore, quaternary alloy is introduced between InGaN and GaN
AlInGaN can reduce trap caused by even being eliminated because of traditional InGaN/GaN lattice mismatch and build the stress that interface is formed, drop
Low stress bring piezoelectric polarization keeps normal energy band to reduce built in field effect, improves electron wave function and hole
The overlapping of wave function improves the radiation recombination efficiency of electrons and holes.
Fig. 7 shows a kind of preparation method of GaN base light emitting epitaxial wafer provided in an embodiment of the present invention.It can adopt
LED epitaxial slice shown in fig. 1 is prepared in the method shown in Fig. 7.Referring to Fig. 7, this method process includes following step
Suddenly.
Step 201 provides substrate.
Illustratively, substrate can be (0001) crystal orientation Sapphire Substrate (Al2O3)。
Step 202 makes annealing treatment substrate.
Wherein, annealing mode depends on the growth pattern of buffer layer.When using PVD (Physical
VaporDeposition, physical vapour deposition (PVD)) method buffer layer when, annealing mode includes: to be placed into substrate
In the reaction chamber of PVD equipment, and reaction chamber is vacuumized, starts to carry out Sapphire Substrate heating liter while vacuumizing
Temperature.When base vacuum is evacuated to lower than 1*10-7When Torr, heating temperature is stablized at 350~750 DEG C, Sapphire Substrate is carried out
Baking, baking time are 2~12 minutes.When using MOCVD (Metal-organic Chemical Vapor Deposition,
Metallo-organic compound chemical gaseous phase deposition) method buffer layer when, annealing mode includes: to be placed into substrate
It in the reaction chamber of MOCVD device, is then made annealing treatment 10 minutes in hydrogen atmosphere, cleans substrate surface, annealing temperature exists
Between 1000 DEG C and 1100 DEG C, then pressure carries out nitrogen treatment between 200torr-500torr.
Step 203, on substrate buffer layer.
Wherein, buffer layer can be GaN buffer layer, be also possible to AlN buffer layer.
When buffer layer is GaN buffer layer, using MOCVD method grown buffer layer, comprising: firstly, by MOCVD device
Reaction cavity temperature is adjusted to 400 DEG C -600 DEG C, and the thick GaN buffer layer of growth 15 to 35nm, growth pressure section is
200Torr-600Torr.Secondly, buffer layer in-situ annealing is handled, temperature is at 1000 DEG C -1200 DEG C, and the time was at 5 minutes to 10 points
Between clock, pressure 400Torr-600Torr.
When buffer layer is AlN buffer layer, using PVD method grown buffer layer, comprising: will be in the reaction chamber of PVD equipment
Temperature is adjusted to 400-700 DEG C, adjustment sputtering power be 3000~5000W, adjustment pressure be 1~10torr, grow 15 to
The AlN buffer layer of 35nm thickness.
It should be noted that undoped GaN layer, n-type doping GaN layer in epitaxial layer, low temperature stress release layer, Multiple-quantum
Well layer, low temperature p-type GaN layer, electronic barrier layer, high temperature p-type GaN layer and p-type contact layer can be raw using MOCVD method
It is long.It in specific implementation, is usually to place the substrate on graphite pallet in the reaction chamber for being sent into MOCVD device to carry out epitaxial material
Growth, therefore the temperature and pressure controlled in above-mentioned growth course actually refers to the temperature and pressure in reaction chamber.Specifically
Ground, using trimethyl gallium or trimethyl second as gallium source, high pure nitrogen is as nitrogen source, and trimethyl indium is as indium source, trimethyl aluminium
As silicon source, N type dopant selects silane, and P-type dopant selects two luxuriant magnesium.
Step 204 deposits undoped GaN layer on the buffer layer.
Illustratively, the growth temperature of undoped GaN layer be 1000 DEG C -1150 DEG C, growth thickness between 1 to 3 micron,
Growth pressure is in 100Torr between 200Torr.
Step 205, the deposited n-type doped gan layer in undoped GaN layer.
Illustratively, the thickness of N-type GaN layer is between 1-2 microns, and growth temperature is at 1100 DEG C -1150 DEG C, growth pressure
In 200Torr or so, Si doping concentration is 1 × 1018cm-3-5×1019cm-3Between.
Step 206, the deposit low temperature stress release layer in n-type doping GaN layer.
Illustratively, low temperature stress release layer includes the first N-type GaN sublayer successively grown, 2~10 periods
InGaN/GaN periodic structure and the second N-type GaN sublayer.Wherein, the first N-type GaN sublayer, 2~10 periods
The thickness of InGaN/GaN periodic structure and the second N-type GaN sublayer is followed successively by 50nm, 2nm/20nm, 40nm.Growth temperature
It is 800-900 DEG C, growth pressure 100-500Torr.
Step 207 deposits multiple quantum well layer on low temperature stress release layer.
Wherein, multiple quantum well layer includes the trap barrier layer of several stackings, and trap barrier layer includes quantum well layer and quantum barrier layer, quantum
Well layer includes the first InGaN layer, and quantum barrier layer includes the first AlInGaN layers of stacked above one another, GaN layer and the 2nd AlInGaN
Layer, the quantum well layer in the trap barrier layer of low temperature stress release layer are contacted with low temperature stress release layer.
Illustratively, quantum well layer, the first AlInGaN layers with the 2nd AlInGaN layers growth temperature it is identical, for example, amount
Sub- well layer, the first AlInGaN layers and the 2nd AlInGaN layers of growth temperature may each be 700~800 DEG C.The growth temperature of GaN layer
It spends 100~150 DEG C higher than the growth temperature of quantum well layer.The flood growth pressure of multiple quantum well layer can be 100~
200torr。
Illustratively, quantum well layer further includes InN layers and the second InGaN layer, and InN layers are located at the first InGaN layer and second
Between InGaN layer.The first InGaN layer in the quantum well layer contacted with low temperature stress release layer connects with low temperature stress release layer
Touching.
Illustratively, the growth course for multiple quantum well layer being grown on low temperature stress release layer includes: to be in growth temperature
750 DEG C, under conditions of growth pressure is 150torr, it is continually fed into appropriate NH3Under, it is passed through a certain amount of trimethyl indium and front three
One InGaN layer of base gallium growth regulation, keep growth temperature and growth pressure it is constant, close trimethyl gallium, grow InN layers, then after
It is continuous to open TMGa, two InGaN layer of growth regulation；And then it keeps under mutually synthermal uniform pressure, continues to be passed through appropriate trimethyl indium
With trimethyl gallium and be passed through one AlInGaN layers of trimethyl aluminium growth regulation, and then close all MO (Metallo-organic
Compound, metallo-organic compound) opening trimethyl gallium grows GaN layer to 100 degree of temperature of source raising later, and it finally closes and owns
The source MO simultaneously reduces and is passed through trimethyl indium and trimethyl gallium after 100 degree of growth temperature and is passed through trimethyl aluminium growth barrier layer second
AlInGaN layers, complete the growth of first trap barrier layer.Remaining trap barrier layer is grown as procedure described above, until multiple quantum well layer is raw
Length terminates.
Illustratively, the first InGaN layer and the second InGaN layer are Inx1Ga1-x1N layers, the first AlInGaN layers and second
AlInGaN layers are AlyInx2Ga1-x2-yN layers, 0.1≤y≤0.8,0.1≤x1≤0.3,0.05≤x2≤0.2.
Illustratively, the thickness of the first InGaN layer and the second InGaN layer isInN layers of volume with a thickness ofFirst AlInGaN layers and the 2nd AlInGaN layers of thickness isGaN layer with a thickness ofThe quantity of trap barrier layer is 6~10.
Illustratively, the thickness of multiple quantum well layer can be 100nm~150nm.
Step 208, the growing low temperature p-type GaN layer on multiple quantum well layer.
Illustratively, low temperature p-type GaN layer with a thickness of 200-400nm, growth temperature is 700-800 DEG C, and growth pressure exists
200Torr。
Step 209 deposits electronic barrier layer in low temperature p-type GaN layer.
Illustratively, electronic barrier layer is p-type AlGaN layer, the growth temperature of electronic barrier layer 800 DEG C with 1000 DEG C it
Between, growth pressure is between 50Torr and 500Torr.The thickness of electronic barrier layer is in 20nm between 100nm.
Step 210, the depositing high temperature p-type GaN layer on electronic barrier layer.
Illustratively, the growth temperature of high temperature p-type GaN layer is 950 DEG C~1000 DEG C, growth pressure 200torr, high temperature
The thickness of p-type GaN layer 9 can be 100nm~300nm.
Step 211 deposits p-type contact layer in high temperature p-type GaN layer.
Illustratively, p-type contact layer is GaN or InGaN layer, with a thickness of 50nm between 100nm, growth temperature area
Between be 850 DEG C -950 DEG C, growth pressure section be 200Torr-500Torr.
Illustratively, after the growth of p-type contact layer, the reaction cavity temperature of MOCVD device is reduced, in nitrogen atmosphere
Middle annealing, annealing temperature section are 650 DEG C -850 DEG C, make annealing treatment 5 to 15 minutes, are down to room temperature, complete epitaxial growth.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of GaN base light emitting epitaxial wafer, which is characterized in that the LED epitaxial slice includes:
Substrate, the buffer layer being sequentially deposited over the substrate, undoped GaN layer, n-type doping GaN layer, low temperature stress release
Layer, multiple quantum well layer, low temperature p-type GaN layer, electronic barrier layer, high temperature p-type GaN layer and p-type contact layer,
The multiple quantum well layer includes the trap barrier layer of several stackings, and the trap barrier layer includes quantum well layer and quantum barrier layer, described
Quantum well layer includes the first InGaN layer, and the quantum barrier layer includes the first AlInGaN layers, GaN layer, Yi Ji of stacked above one another
Two AlInGaN layers, the quantum well layer in the trap barrier layer of the low temperature stress release layer connects with the low temperature stress release layer
Touching.
2. epitaxial wafer according to claim 1, which is characterized in that the quantum well layer is low temperature quantum well layer, described the
One AlInGaN layers and the described 2nd AlInGaN layer be low temperature AI InGaN layer, the GaN layer be high-temperature gan layer.
3. epitaxial wafer according to claim 2, which is characterized in that the quantum well layer further includes InN layers and the 2nd InGaN
Layer, described InN layers between first InGaN layer and second InGaN layer, contacts with the low temperature stress release layer
Quantum well layer in the first InGaN layer contacted with the low temperature stress release layer.
4. epitaxial wafer according to claim 3, which is characterized in that first InGaN layer and second InGaN layer are equal
For Inx1Ga1-x1N layers, the described first AlInGaN layers and the described 2nd AlInGaN layers be AlyInx2Ga1-x2-yN layers, 0.1≤y
≤ 0.8,0.1≤x1≤0.3,0.05≤x2≤0.2.
5. epitaxial wafer according to claim 4, which is characterized in that first InGaN layer and second InGaN layer
Thickness isDescribed InN layers with a thickness ofDescribed first AlInGaN layers and described second
AlInGaN layers of thickness isThe GaN layer with a thickness ofThe quantity of the trap barrier layer
It is 6~10.
6. a kind of preparation method of GaN base light emitting epitaxial wafer, which is characterized in that the described method includes:
Substrate is provided；
It is sequentially deposited buffer layer, undoped GaN layer, n-type doping GaN layer, low temperature stress release layer, Multiple-quantum over the substrate
Well layer, low temperature p-type GaN layer, electronic barrier layer, high temperature p-type GaN layer and p-type contact layer, if the multiple quantum well layer includes
The folded trap barrier layer of dried layer, the trap barrier layer include quantum well layer and quantum barrier layer, and the quantum well layer includes the first InGaN layer,
The quantum barrier layer includes the first AlInGaN layers of stacked above one another, GaN layer and the 2nd AlInGaN layers, close to the low temperature
Quantum well layer in the trap barrier layer of stress release layer is contacted with the low temperature stress release layer.
7. according to the method described in claim 6, it is characterized in that, the quantum well layer, the described first AlInGaN layers and described
2nd AlInGaN layers growth temperature it is identical, the growth temperature of the GaN layer is higher than the growth temperature of the quantum well layer by 100
~150 DEG C.
8. the method according to the description of claim 7 is characterized in that the quantum well layer further includes InN layers and the 2nd InGaN
Layer, described InN layers between first InGaN layer and second InGaN layer, contacts with the low temperature stress release layer
Quantum well layer in the first InGaN layer contacted with the low temperature stress release layer.
9. according to the method described in claim 8, it is characterized in that, first InGaN layer and second InGaN layer are
Inx1Ga1-x1N layers, the described first AlInGaN layers and the described 2nd AlInGaN layers be AlyInx2Ga1-x2-yN layers, 0.1≤y≤
0.8,0.1≤x1≤0.3,0.05≤x2≤0.2.
10. according to the method described in claim 9, it is characterized in that, first InGaN layer and second InGaN layer
Thickness isDescribed InN layers with a thickness ofDescribed first AlInGaN layers and described second
AlInGaN layers of thickness isThe GaN layer with a thickness ofThe quantity of the trap barrier layer
It is 6~10.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113097353A (en) * | 2021-04-02 | 2021-07-09 | 厦门乾照光电股份有限公司 | Ultraviolet LED and manufacturing method thereof |
| CN113555475A (en) * | 2021-07-20 | 2021-10-26 | 圆融光电科技股份有限公司 | UVLED epitaxial structure, preparation method thereof and UVLED chip |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105023979A (en) * | 2015-06-03 | 2015-11-04 | 华灿光电(苏州）有限公司 | A GaN-based LED epitaxial wafer and a manufacturing method thereof |
| CN105161586A (en) * | 2015-09-29 | 2015-12-16 | 山东浪潮华光光电子股份有限公司 | LED epitaxial structure having combination barrier multi-quantum well and preparation method |
| CN106057996A (en) * | 2016-06-22 | 2016-10-26 | 华灿光电(苏州）有限公司 | Epitaxial wafer of light-emitting diode and growing method thereof |
-
2018
- 2018-11-19 CN CN201811376957.0A patent/CN109860356A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105023979A (en) * | 2015-06-03 | 2015-11-04 | 华灿光电(苏州）有限公司 | A GaN-based LED epitaxial wafer and a manufacturing method thereof |
| CN105161586A (en) * | 2015-09-29 | 2015-12-16 | 山东浪潮华光光电子股份有限公司 | LED epitaxial structure having combination barrier multi-quantum well and preparation method |
| CN106057996A (en) * | 2016-06-22 | 2016-10-26 | 华灿光电(苏州）有限公司 | Epitaxial wafer of light-emitting diode and growing method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113097353A (en) * | 2021-04-02 | 2021-07-09 | 厦门乾照光电股份有限公司 | Ultraviolet LED and manufacturing method thereof |
| CN113555475A (en) * | 2021-07-20 | 2021-10-26 | 圆融光电科技股份有限公司 | UVLED epitaxial structure, preparation method thereof and UVLED chip |
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Application publication date: 20190607 |