CN110518096A - The preparation method of LED epitaxial slice - Google Patents
The preparation method of LED epitaxial slice Download PDFInfo
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- CN110518096A CN110518096A CN201910604905.2A CN201910604905A CN110518096A CN 110518096 A CN110518096 A CN 110518096A CN 201910604905 A CN201910604905 A CN 201910604905A CN 110518096 A CN110518096 A CN 110518096A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
Abstract
The invention discloses the preparation methods of LED epitaxial slice, belong to light emitting diode production field.Insertion includes the GaN insert layer of n sublayer between the InGaN well layer and GaN barrier layer of multiple quantum well layer.And the growth temperature for controlling the sublayer to connect in GaN insert layer with InGaN well layer is greater than or equal to the growth temperature of InGaN well layer, the growth temperature of the sublayer to connect with GaN barrier layer is less than the growth temperature of GaN barrier layer, low temperature can avoid GaN insert layer when growing in InGaN well layer, there is biggish In precipitation phenomenon in the surface of InGaN well layer, the retention of In is more uniform in InGaN well layer, the retention of In and distribution are more uniform in InGaN well layer, and the Luminescence Uniformity of diode is improved.The In of precipitation enters GaN insert layer rather than GaN barrier layer, and the quality of GaN barrier layer can be improved.The growth temperature of n sublayer gradually rises along the stacking direction of n sublayer, and the total quality of last light emitting diode is still preferable, and the light emitting diode Integral luminous uniformity is improved.
Description
Technical field
The present invention relates to light emitting diode production field, in particular to a kind of preparation method of LED epitaxial slice.
Background technique
LEDLight Emitting Diode, light emitting diode are a kind of semiconductor electronic components that can be luminous.As one
Efficient, environmental protection, green New Solid lighting source are planted, is widely applied rapidly, in traffic lights, automobile
Outer lamp, landscape light in city, cell phone back light source etc., improving chip light emitting efficiency is the target that LED is constantly pursued.
The epitaxial wafer of current light emitting diode generally include substrate and successively grow on substrate n-layer, Multiple-quantum
Well layer and p-type layer, multiple quantum well layer include alternately stacked InGaN well layer and GaN barrier layer.And usually GaN barrier layer need compared with
The growth quality to guarantee multiple quantum well layer entirety is grown at a temperature of high, GaN barrier layer is with higher growth temperature in InGaN trap
When the surface growth of layer, the surface of InGaN well layer can be made to be precipitated in a large amount of In to GaN barrier layer at high temperature, GaN barrier layer
Quality is affected, while also will appear In in InGaN well layer and being unevenly distributed, the situation of InGaN well layer emission wavelength unevenness, most
The luminous efficiency of light emitting diode is influenced eventually.
Summary of the invention
The embodiment of the invention provides the preparation methods of LED epitaxial slice, can be improved shining for light emitting diode
Efficiency.The technical solution is as follows:
The embodiment of the invention provides a kind of preparation method of the epitaxial wafer of light emitting diode, the preparation method includes:
One substrate is provided；
Successively growing n-type layer, multiple quantum well layer and p-type layer over the substrate,
The multiple quantum well layer includes the composite construction of multiple loop cycles, and each composite construction includes successively layer
Folded InGaN well layer, GaN insert layer and GaN barrier layer, the GaN insert layer include n sublayer, wherein 2≤n and n are integer,
The n sublayer is sequentially laminated in the InGaN well layer,
The growth temperature of the sublayer to connect with the InGaN well layer is greater than or equal to the growth of the InGaN well layer
Temperature, the growth temperature of the sublayer to connect with the GaN barrier layer are less than the growth temperature of the GaN barrier layer, the n son
The growth temperature of layer gradually rises along the stacking direction of the n sublayer.
Optionally, the difference of the growth temperature of two sublayers to connect is 10~25 DEG C.
Optionally, the growth temperature of the growth temperature of the sublayer to connect with the InGaN well layer and the InGaN well layer
It spends equal.
Optionally, the growth thickness of the n sublayer is gradually reduced along the stacking direction of the n sublayer.
Optionally, the growth thickness of the sublayer to connect with the InGaN well layer is 0.1~0.8nm.
Optionally, the difference of the growth thickness of two sublayers to connect is 0.1~0.3nm.
Optionally, the growth thickness of the GaN insert layer is less than the growth thickness of the InGaN well layer.
Optionally, the growth thickness of the GaN insert layer is 1~2.5nm.
Optionally, the growth temperature of a sublayer of the growth temperature of the GaN barrier layer than connecting with the GaN barrier layer is high
50~100 DEG C.
Optionally, 2≤n≤5.
Technical solution provided in an embodiment of the present invention have the benefit that InGaN well layer in multiple quantum well layer with
Insertion includes the GaN insert layer of n sublayer between GaN barrier layer.And control one to connect in GaN insert layer with InGaN well layer
The growth temperature of sublayer is greater than or equal to the growth temperature of InGaN well layer, the growth temperature of the sublayer to connect with GaN barrier layer
Less than the growth temperature of GaN barrier layer, the growth temperature lower than GaN barrier layer can reduce GaN insert layer and grow in InGaN well layer
When, the In precipitation phenomenon that the surface of InGaN well layer will appear, the retention of In is more uniform in InGaN well layer, subsequent GaN insertion
Although temperature is higher when the sublayer of layer is grown with GaN barrier layer, since the sublayer of subsequent GaN insert layer is not directly in InGaN
It is grown on the surface of well layer, so the In evolution reaction on the surface of InGaN well layer is more slight, less, InGaN well layer is precipitated in In
The retention of middle In and distribution are more uniform, and the Luminescence Uniformity of diode is improved.The In of precipitation enter GaN insert layer rather than
The quality of GaN barrier layer can be improved in GaN barrier layer.It is gradually risen in conjunction with the growth temperature of n sublayer along the stacking direction of n sublayer
Height can guarantee the growth quality of GaN insert layer itself to a certain extent, offset In and precipitate into GaN insert layer to GaN insert layer
Caused by influence, the total quality of the multiple quantum well layer of last light emitting diode is still improved, and light emitting diode Integral luminous is equal
Evenness is improved, and can be improved the luminous efficiency of light emitting diode.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is the preparation method flow chart of LED epitaxial slice provided in an embodiment of the present invention；
Fig. 2 is another preparation method flow chart of LED epitaxial slice provided in an embodiment of the present invention；
Fig. 3 is a kind of structural schematic diagram of LED epitaxial slice provided in an embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
Fig. 1 is the preparation method flow chart of LED epitaxial slice provided in an embodiment of the present invention, as shown in Figure 1, should
Preparation method includes:
S101: a substrate is provided.
S102: successively growing n-type layer, multiple quantum well layer and p-type layer on substrate.Multiple quantum well layer includes following in multiple periods
The composite construction of ring, each composite construction include the InGaN well layer, GaN insert layer and GaN barrier layer stacked gradually, GaN insertion
Layer includes n sublayer, wherein 2≤n and n are integer, n sublayer is sequentially laminated in InGaN well layer.
The growth temperature of the sublayer to connect with InGaN well layer is greater than or equal to the growth temperature of InGaN well layer, with
The growth temperature for the sublayer that GaN barrier layer connects is less than the growth temperature of GaN barrier layer, and the growth temperature of n sublayer is along n son
The stacking direction of layer gradually rises.
Insertion includes the GaN insert layer of n sublayer between the InGaN well layer and GaN barrier layer of multiple quantum well layer.And it controls
The growth temperature of the sublayer to connect in GaN insert layer with InGaN well layer is greater than or equal to the growth temperature of InGaN well layer,
The growth temperature of the sublayer to connect with GaN barrier layer is less than the growth temperature of GaN barrier layer, the growth temperature lower than GaN barrier layer
GaN insert layer can be reduced when growing in InGaN well layer, the In precipitation phenomenon that the surface of InGaN well layer will appear, InGaN trap
The retention of In is more uniform in layer, although temperature is higher when the sublayer of subsequent GaN insert layer is grown with GaN barrier layer, due to rear
The sublayer of continuous GaN insert layer is not directly to grow on the surface of InGaN well layer, so the In on the surface of InGaN well layer is precipitated
React more slight, less, the retention of In and more uniform, the Luminescence Uniformity of diode of distribution in InGaN well layer is precipitated in In
It is improved.The In of precipitation enters GaN insert layer rather than GaN barrier layer, and the quality of GaN barrier layer can be improved.In conjunction with n sublayer
Growth temperature gradually rises along the stacking direction of n sublayer, can guarantee the growth matter of GaN insert layer itself to a certain extent
Amount offsets In and precipitate into the influence caused by GaN insert layer of GaN insert layer, the multiple quantum well layer of last light emitting diode it is whole
Weight is still improved, and the light emitting diode Integral luminous uniformity is improved, and can be improved the luminous efficiency of light emitting diode.
Fig. 2 is another preparation method flow chart of LED epitaxial slice provided in an embodiment of the present invention, such as Fig. 2 institute
Show, which includes:
S201: a substrate is provided.
Optionally, substrate can be sapphire.
Illustratively, step S201 can include:
In a hydrogen atmosphere, 5~6min of high-temperature process substrate.Wherein, handle substrate when reaction chamber temperature be 1000~
1100 DEG C, chamber pressure is controlled in 200~500torr.The step for can remove the impurity of some substrate surfaces, guarantee serving as a contrast
The quality of the epitaxial wafer directly grown on bottom.
S202: growing n-type layer on substrate.
Step S202 can include: successively growing low temperature GaN buffer layer, high temperature GaN buffer layer and n-type GaN layer on substrate.
Wherein, low temperature GaN buffer can be grown on [0001] face of Sapphire Substrate.The quality of obtained epitaxial wafer compared with
It is good.
Illustratively, when growing low temperature GaN buffer layer, the pressure of reaction chamber can be 200~500torr, the temperature of reaction chamber
Degree can be 530~560 DEG C.
The thickness of low temperature GaN buffer can be 15~30nm.
High temperature GaN buffer layer can be the GaN layer to undope, and the thickness of high temperature GaN buffer layer can be 2~3.5um.Growth
When high temperature GaN buffer layer, reaction chamber temperature can be 1000~1100 DEG C, and chamber pressure is controlled in 200~600torr.At this time
The quality of finally obtained epitaxial wafer is preferable.
N-type GaN layer can be to mix the GaN layer of Si, and the thickness of n-type GaN layer can be 2~3um.When growing n-type GaN layer, instead
Answering room temperature can be 1000~1100 DEG C, and chamber pressure can be controlled in 200~300torr.
It should be noted that the merely illustrative use of the structure of n-layer described herein, in the other embodiment of the present invention
In, n-layer may also comprise AlN buffer layer and n-type GaN layer or other structures, and the present invention is without limitation.
S203: multiple quantum well layer is grown in n-layer.Multiple quantum well layer includes the composite construction of multiple loop cycles, often
A composite construction includes the InGaN well layer, GaN insert layer and GaN barrier layer stacked gradually, and GaN insert layer includes n sublayer,
Wherein 2≤n and n are integer, and n sublayer is sequentially laminated in InGaN well layer.
The growth temperature of the sublayer to connect with InGaN well layer is greater than or equal to the growth temperature of InGaN well layer, with
The growth temperature for the sublayer that GaN barrier layer connects is less than the growth temperature of GaN barrier layer, and the growth temperature of n sublayer is along n son
The stacking direction of layer gradually rises.
Optionally, equal with the growth temperature of InGaN well layer with the growth temperature for the sublayer that InGaN well layer connects.
The amount of precipitation for the In that will appear in InGaN well layer at this time is less, and the total quality of obtained multiple quantum wells is preferable.
Optionally, the difference of the growth temperature of two sublayers to connect can be 10~25 DEG C.
When the difference of the growth temperature of two sublayers to connect is 10~25 DEG C, the In component that GaN insert layer integrally plays is steady
Fixed and uniform effect preferably, and will not cause excessive In that situation is precipitated, and the total quality of obtained multiple quantum wells is preferable.
Optionally, the growth thickness of n sublayer can be gradually reduced along the stacking direction of n sublayer.
The growth thickness of n sublayer can be gradually reduced along the stacking direction of n sublayer, and this set can reduce n son
It is gradually warmed up when layer growth on the possible influence of InGaN well layer, reduces the possibility that In is precipitated, while also can effectively avoid
The In being precipitated in InGaN well layer penetrates into GaN barrier layer, and the quality of the light emitting diode finally integrally obtained is preferable.
Illustratively, the growth thickness of the sublayer to connect with InGaN well layer can be 0.1~0.8nm.
The sublayer to connect at this time with InGaN well layer can effectively play the effect of In component in stable InGaN well layer, subtract
The sublayer of small subsequent growth impacts InGaN well layer, and the In being precipitated can also effectively be prevented to enter subsequent sublayer, improves volume
The quality of sub- well layer.
Optionally, the difference of the growth thickness of two sublayers to connect can be 0.1~0.3nm.
The difference of the growth thickness of two sublayers to connect within this range when, the quality of obtained multiple quantum well layer is preferable.
Illustratively, the growth thickness of GaN insert layer is smaller than the growth thickness of InGaN well layer.
The growth thickness of GaN insert layer is less than the growth thickness of InGaN well layer, has on the one hand saved production cost, another
The growth thickness of aspect GaN insert layer at this time is relatively reasonable, and the promotion of the luminous efficiency of light emitting diode is also very fast.
Optionally, the growth thickness of GaN insert layer can be 1~2.5nm.
The growth thickness of GaN insert layer within this range when the obtained quality of epitaxial wafer it is relatively preferable.
Illustratively, the n in GaN insert layer can meet: 2≤n≤5.
2≤n≤5, which can guarantee, plays the role of protecting InGaN well layer and GaN barrier layer, and not will increase more be produced into
This.
Illustratively, the growth temperature of the GaN barrier layer in the multiple quantum well layer comparable sublayer to connect with GaN barrier layer
Growth temperature is 50~100 DEG C high.
The growth temperature of a sublayer of the growth temperature of GaN barrier layer than connecting with GaN barrier layer is 50~100 DEG C high, can be with
Guarantee that the growth quality of GaN barrier layer, the total quality of multiple quantum well layer are also preferable.
S204: p-type layer is grown on multiple quantum well layer.
Step S204 can include: electronic barrier layer and p-type GaN layer are successively grown on multiple quantum well layer.
Wherein, electronic barrier layer can be the Al for mixing Al, mixing MgyGa1~yN (y=0.15~0.25), the thickness of electronic barrier layer
Degree can be 30~50nm.
Optionally, reaction chamber temperature can be 930~970 DEG C when growing electronic barrier layer, and chamber pressure is can be controlled in
100torr.The total quality of obtained epitaxial wafer is preferable.
Optionally, the thickness of p-type GaN layer can be 50~80nm.
Illustratively, when growing p-type GaN layer, reaction chamber temperature can be 940~980 DEG C, and chamber pressure is can be controlled in
200~600torr.
It should be noted that in the present embodiment, Veeco K465i or C4 MOCVD (Metal Organic can be used
Chemical Vapor Deposition, metallo-organic compound chemical gaseous phase deposition) equipment realizes above-mentioned light emitting diode
Growing method.Using high-purity H2(hydrogen) or high-purity N2(nitrogen) or high-purity H2And high-purity N2Mixed gas as carrier gas, it is high-purity
NH3As the source N, trimethyl gallium (TMGa) and triethyl-gallium (TEGa) are used as gallium source, and trimethyl indium (TMIn) is used as indium source, silane
(SiH4) it is used as N type dopant, trimethyl aluminium (TMAl) is used as silicon source, two luxuriant magnesium (CP2Mg) it is used as P-type dopant.
Fig. 3 is a kind of structural schematic diagram of LED epitaxial slice provided in an embodiment of the present invention, is executed the step
Epitaxial wafer after S204 can be as shown in figure 3, successively growth has n-layer 2, multiple quantum well layer 3 and p-type layer 4 on substrate 1.N-layer
2 include low temperature GaN buffer 21, high temperature GaN buffer layer 22 and n-type GaN layer 23, and multiple quantum well layer 3 includes multiple composite constructions
31, each composite construction 31 includes InGaN well layer 311, GaN insert layer 312 and GaN barrier layer 313, and GaN insert layer 312 includes
N sublayer 312a.
P-type layer 4 may include electronic barrier layer 41 and p-type GaN layer 42.
It should be noted that the merely illustrative use of the structure of light emitting diode shown in Fig. 3, is convenient for those skilled in the art
It further appreciates that the present invention, is not used to limit the invention.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of preparation method of the epitaxial wafer of light emitting diode, the preparation method include:
One substrate is provided；
Successively growing n-type layer, multiple quantum well layer and p-type layer over the substrate,
It is characterized in that, the multiple quantum well layer includes the composite construction of multiple loop cycles, each composite construction is wrapped
The InGaN well layer, GaN insert layer and GaN barrier layer stacked gradually is included, the GaN insert layer includes n sublayer, wherein 2≤n and n
For integer, the n sublayer is sequentially laminated in the InGaN well layer,
The growth temperature of the sublayer to connect with the InGaN well layer is greater than or equal to the growth temperature of the InGaN well layer,
The growth temperature of the sublayer to connect with the GaN barrier layer is less than the growth temperature of the GaN barrier layer, the n sublayer
Growth temperature gradually rises along the stacking direction of the n sublayer.
2. preparation method according to claim 1, which is characterized in that the difference of the growth temperature of two sublayers to connect
It is 10~25 DEG C.
3. preparation method according to claim 1, which is characterized in that the sublayer to connect with the InGaN well layer
Growth temperature is equal with the growth temperature of the InGaN well layer.
4. described in any item preparation methods according to claim 1~3, which is characterized in that the growth thickness edge of the n sublayer
The stacking direction of the n sublayer is gradually reduced.
5. the preparation method according to claim 4, which is characterized in that the sublayer to connect with the InGaN well layer
Growth thickness is 0.1~0.8nm.
6. the preparation method according to claim 4, which is characterized in that the difference of the growth thickness of two sublayers to connect
For 0.1~0.3nm.
7. described in any item preparation methods according to claim 1~3, which is characterized in that the growth thickness of the GaN insert layer
Less than the growth thickness of the InGaN well layer.
8. preparation method according to claim 7, which is characterized in that the growth thickness of the GaN insert layer be 1~
2.5nm。
9. described in any item preparation methods according to claim 1~3, which is characterized in that the growth temperature ratio of the GaN barrier layer
The growth temperature of the sublayer to connect with the GaN barrier layer is 50~100 DEG C high.
10. described in any item preparation methods according to claim 1~3, which is characterized in that 2≤n≤5.
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| CN112993099A (en) * | 2021-02-09 | 2021-06-18 | 厦门乾照光电股份有限公司 | Manufacturing method of LED chip with protective layer |
| CN113284986A (en) * | 2021-03-29 | 2021-08-20 | 华灿光电（浙江）有限公司 | Preparation method of light-emitting diode epitaxial wafer |
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