CN109671813B - GaN-based light emitting diode epitaxial wafer and preparation method thereof - Google Patents
GaN-based light emitting diode epitaxial wafer and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
Abstract
The invention discloses a GaN-based light emitting diode epitaxial wafer and a preparation method thereof, and belongs to the technical field of GaN-based light emitting diodes. The light emitting diode epitaxial wafer comprises: the LED light-emitting diode comprises a substrate, and a buffer layer, a non-doped GaN layer, an N-type GaN layer, a low-temperature stress release layer, a multi-quantum well layer, an electronic barrier layer, a P-type GaN layer and a P-type ohmic contact layer which are sequentially deposited on the substrate, wherein the multi-quantum well layer comprises a plurality of stacked well barrier layers, each well barrier layer comprises an InGaN light-emitting well layer, a light-emitting well protective layer and a GaN barrier layer which are sequentially stacked, the GaN barrier layer in the well barrier layer close to the electronic barrier layer is in contact with the electronic barrier layer, each light-emitting well protective layer comprises an AlInN layer, the InGaN light-emitting well layer is a low-temperature InGaN light-emitting well layer, the light-emitting well protective layer is a medium.
Description
Technical Field
The invention relates to the field of GaN-based light emitting diodes, in particular to a GaN-based light emitting diode epitaxial wafer and a preparation method thereof.
Background
A GaN (gallium nitride) -based LED (Light Emitting Diode) generally includes an epitaxial wafer and an electrode prepared on the epitaxial wafer. The epitaxial wafer generally comprises: the semiconductor device includes a substrate, and a buffer layer, an undoped GaN layer, an N-type GaN layer, an MQW (Multiple Quantum Well) layer, an electron blocking layer, a P-type GaN layer, and an ohmic contact layer sequentially stacked on the substrate. When current flows, electrons in an N-type region such as an N-type GaN layer and holes in a P-type region such as a P-type GaN layer enter the MQW active region and recombine to emit visible light. The conventional structure of the MQW layer is a superlattice structure composed of InGaN quantum wells/GaN quantum barriers.
In the process of implementing the invention, the inventor finds that the prior art has at least the following problems: the growth temperature of the InGaN quantum well is about 100 ℃ lower than that of the GaN quantum barrier, on one hand, the larger temperature difference between the InGaN quantum well and the GaN quantum barrier enables an obvious interface to exist between the InGaN quantum well and the GaN quantum barrier due to the difference of crystal quality, and the carrier is influenced to rapidly pass through the interface and migrate to the quantum well; on the other hand, the growth temperature of the GaN quantum barrier is higher, so that a large amount of In the InGaN quantum well is precipitated, the incorporation quality of an In component In the quantum well is reduced, and the reduction of the In component content affects the recombination efficiency of carriers.
Disclosure of Invention
The embodiment of the invention provides a GaN-based light emitting diode epitaxial wafer and a preparation method thereof, which can improve the crystal quality of an interface between well barriers and reduce the large-amount precipitation of In an InGaN quantum well. The technical scheme is as follows:
in a first aspect, a GaN-based light emitting diode epitaxial wafer is provided, the light emitting diode epitaxial wafer comprising:
the LED light-emitting diode comprises a substrate, and a buffer layer, a non-doped GaN layer, an N-type GaN layer, a low-temperature stress release layer, a multi-quantum well layer, an electronic barrier layer, a P-type GaN layer and a P-type ohmic contact layer which are sequentially deposited on the substrate, wherein the multi-quantum well layer comprises a plurality of stacked well barrier layers, each well barrier layer comprises an InGaN light-emitting well layer, a light-emitting well protective layer and a GaN barrier layer which are sequentially stacked, the GaN barrier layer in the well barrier layer close to the electronic barrier layer is in contact with the electronic barrier layer, each light-emitting well protective layer comprises an AlInN layer, the InGaN light-emitting well layer is a low-temperature InGaN light-emitting well layer, the light-emitting well protective layer is a medium.
Optionally, the AlInN layer is Al1-xInxN layer, 0.1<x<0.5。
Optionally, the thickness of the InGaN light emitting well layer is 2-4 nm, the thickness of the AlInN layer is 0.5-2 nm, and the thickness of the GaN barrier layer is 6-12 nm.
Optionally, the light emitting well protection layer further includes an AlN layer, the AlN layer is located between the AlInN layer and the GaN barrier layer, and the AlN layer is an intermediate-temperature AlN layer.
Optionally, the AlN layer has a thickness of 0.5 to 2 nm.
Optionally, the well barrier layer further includes a light emitting well transition layer, the InGaN light emitting well layer is located between the light emitting well transition layer and the light emitting well protective layer, the light emitting well transition layer in the well barrier layer close to the low temperature stress release layer is in contact with the low temperature stress release layer, and the light emitting well transition layer is a GaN light emitting well transition layer or an AlInN light emitting well transition layer.
Optionally, when the light emitting well transition layer is an AlInN light emitting well transition layer, the light emitting well transition layer is Al1- yInyN layer, 0.1<y<0.5。
Optionally, the growth thickness of the light emitting well transition layer is 0.5-2 nm.
In a second aspect, a method for preparing a GaN-based light emitting diode epitaxial wafer is provided, the method comprising:
providing a substrate;
depositing a buffer layer, a non-doped GaN layer, an N-type GaN layer, a low-temperature stress release layer, a multi-quantum well layer, an electronic barrier layer, a P-type GaN layer and a P-type ohmic contact layer on the substrate in sequence;
the multiple quantum well layer comprises a plurality of laminated well barrier layers, each well barrier layer comprises an InGaN light-emitting well layer, a light-emitting well protective layer and a GaN barrier layer which are sequentially laminated, the GaN barrier layer in the well barrier layer close to the electronic barrier layer is in contact with the electronic barrier layer, each light-emitting well protective layer comprises an AlInN layer, the growth temperature of the InGaN light-emitting well layer is lower than the growth temperature of the light-emitting well protective layer, and the growth temperature of the light-emitting well protective layer is lower than the growth temperature of the GaN barrier layer.
Optionally, the growth temperature of the InGaN light emitting well layer is 700-800 ℃, the growth temperature of the AlInN layer is 750-850 ℃, and the growth temperature of the GaN barrier layer is 850-950 ℃.
The technical scheme provided by the embodiment of the invention has the following beneficial effects: the multiple quantum well layer comprises a plurality of laminated well barrier layers, each well barrier layer comprises an InGaN light emitting well layer, a light emitting well protective layer and a GaN barrier layer which are sequentially laminated, the InGaN light emitting well layer is a low-temperature InGaN light emitting well layer, the light emitting well protective layer is an intermediate-temperature light emitting well protective layer, the GaN barrier layer is a high-temperature GaN barrier layer, namely the growth temperature of the InGaN light emitting well layer is lower than the growth temperature of the light emitting well protective layer, the growth temperature of the light emitting well protective layer is lower than the growth temperature of the GaN barrier layer, the growth temperature of the light emitting well protective layer is between the growth temperatures of the InGaN light emitting well layer and the GaN barrier layer, in the growth process, the low temperature of the InGaN light emitting well layer can be gradually transited to the high temperature of the GaN barrier layer, the light emitting well protective layer comprises an AlInN layer, the lattice constant of the AlInN is between the lattice constants of the InGaN and, this is advantageous for improving the crystal quality of the interface between the well barriers; and under the protection of the light-emitting well protective layer, In the InGaN quantum well can be reduced or avoided being separated out, the incorporation content of In components In the quantum well is improved, and the recombination efficiency of carriers is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a flow chart of a method for fabricating an epitaxial wafer of a GaN-based light emitting diode according to an embodiment of the invention;
FIG. 2 is a flow chart of a method for fabricating an epitaxial wafer of a GaN-based light emitting diode according to an embodiment of the invention;
FIG. 3 is a schematic structural diagram of an epitaxial wafer of a GaN-based light emitting diode according to an embodiment of the invention;
fig. 4 is a schematic structural diagram of a well barrier layer of a first structure according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a well barrier layer of a second structure according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Fig. 1 illustrates a method for preparing an epitaxial wafer of a GaN-based light emitting diode according to an embodiment of the invention. Referring to fig. 1, the process flow includes the following steps.
And 102, sequentially depositing a buffer layer, an undoped GaN layer, an N-type GaN layer, a low-temperature stress release layer, a multi-quantum well layer, an electronic barrier layer, a P-type GaN layer and a P-type ohmic contact layer on the substrate.
The multiple quantum well layer comprises a plurality of laminated well barrier layers. The well barrier layer comprises an InGaN light emitting well layer, a light emitting well protection layer and a GaN barrier layer which are sequentially stacked. And the GaN barrier layer in the well barrier layer close to the electron barrier layer is in contact with the electron barrier layer. The light emitting well protection layer includes an AlInN layer. The growth temperature of the InGaN light-emitting well layer is lower than that of the light-emitting well protection layer, and the growth temperature of the light-emitting well protection layer is lower than that of the GaN barrier layer.
In the embodiment of the invention, the multiple quantum well layer comprises a plurality of laminated well barrier layers, each well barrier layer comprises an InGaN light-emitting well layer, a light-emitting well protective layer and a GaN barrier layer which are sequentially laminated, the growth temperature of the InGaN light-emitting well layer is lower than that of the light-emitting well protective layer, and the growth temperature of the light-emitting well protective layer is lower than that of the GaN barrier layer, so that the growth temperature of the light-emitting well protective layer is between that of the InGaN light-emitting well layer and that of the GaN barrier layer, in the growth process, the low temperature of the InGaN light-emitting well layer can be gradually transited to the high temperature of the GaN barrier layer, and the light-emitting well protective layer comprises the AlInN layer, the lattice constant of the AlInN is between that of InGaN and the lattice constant of GaN, and the AlInN can obtain higher crystal quality at a lower growth temperature, so that; and under the protection of the light-emitting well protective layer, In the InGaN quantum well can be reduced or avoided being separated out, the incorporation content of In components In the quantum well is improved, and the recombination efficiency of carriers is improved.
Fig. 2 shows a method for preparing an epitaxial wafer of a GaN-based light emitting diode according to an embodiment of the invention. Referring to fig. 2, the process flow includes the following steps.
Illustratively, the substrate may be a (0001) orientation sapphire substrate (Al)2O3)。
The annealing treatment mode depends on the growth mode of the buffer layer. When the buffer layer is deposited by a PVD (Physical Vapor Deposition) method, the annealing process includes: and placing the substrate into a reaction cavity of the PVD equipment, vacuumizing the reaction cavity, and starting heating the sapphire substrate while vacuumizing. When the background vacuum is pumped to below 1 x 10-7And when the temperature is Torr, stabilizing the heating temperature at 350-750 ℃, and baking the sapphire substrate for 2-12 minutes. When the buffer layer is deposited by a Metal-organic Chemical Vapor Deposition (MOCVD) method, the annealing process includes: the substrate is placed in a reaction cavity of MOCVD equipment, then annealing treatment is carried out for 10 minutes in a hydrogen atmosphere, the surface of the substrate is cleaned, the annealing temperature is between 1000 ℃ and 1200 ℃, and then nitridation treatment is carried out.
The buffer layer may be a GaN buffer layer or an AlN buffer layer.
When the buffer layer is a GaN buffer layer, growing the buffer layer by using an MOCVD method, comprising the following steps: firstly, the temperature in a reaction cavity of MOCVD equipment is adjusted to 400-600 ℃, a GaN buffer layer with the thickness of 15-35 nm is grown, and the growth pressure interval is 200-600 Torr. And secondly, carrying out in-situ annealing treatment on the buffer layer at the temperature of 1000-1200 ℃, for 5-10 minutes and at the pressure of 200-600 Torr.
When the buffer layer is an AlN buffer layer, growing the buffer layer by adopting a PVD method, and the method comprises the following steps: adjusting the temperature in the reaction chamber of the PVD equipment to 400-.
The undoped GaN layer, the N-type GaN layer, the low-temperature stress relief layer, the multi-quantum well layer, the electron blocking layer, the P-type GaN layer, and the P-type ohmic contact layer in the epitaxial layer may be grown by the MOCVD method.
Illustratively, the undoped GaN layer is grown at a temperature of 1000 deg.C-1100 deg.C to a thickness of 0.8 to 1.2 μm and at a pressure of 100Torr to 450 Torr.
And 205, depositing an N-type GaN layer on the undoped GaN layer.
Illustratively, the thickness of the N-type GaN layer is between 1 and 3 microns, the growth temperature is between 1000 ℃ and 1200 ℃, the growth pressure is between 100Torr and 300Torr, and the doping concentration of Si is between 1018cm-3-1019cm-3In the meantime.
And step 206, depositing a low-temperature stress release layer on the N-type GaN layer.
Illustratively, the low temperature stress release layer can be a GaN layer inserted into InGaN, the thickness of the low temperature stress release layer is 150-300nm, the growth temperature is 800-900 ℃, and the growth pressure is 200-400 Torr.
And step 207, depositing a multi-quantum well layer on the low-temperature stress release layer.
The multiple quantum well layer comprises a plurality of laminated well barrier layers. The embodiment of the invention provides a trap barrier layer with two structures.
In the first structure, the well barrier layer includes an InGaN light emitting well layer, a light emitting well protective layer, and a GaN barrier layer, which are sequentially stacked. And the InGaN light emitting well layer in the well barrier layer close to the low-temperature stress release layer is in contact with the low-temperature stress release layer. And the GaN barrier layer in the well barrier layer close to the electron barrier layer is in contact with the electron barrier layer. The growth temperature of the InGaN light-emitting well layer is lower than that of the light-emitting well protection layer, and the growth temperature of the light-emitting well protection layer is lower than that of the GaN barrier layer.
In the second structure, the well barrier layer includes a light emitting well transition layer, an InGaN light emitting well layer, a light emitting well protection layer, and a GaN barrier layer, which are sequentially stacked. And the light emitting well transition layer in the well barrier layer close to the low-temperature stress release layer is in contact with the low-temperature stress release layer. And the GaN barrier layer in the well barrier layer close to the electron barrier layer is in contact with the electron barrier layer. The growth temperature of the InGaN light-emitting well layer is lower than that of the light-emitting well protection layer, and the growth temperature of the light-emitting well protection layer is lower than that of the GaN barrier layer.
The well barrier layer of the second structure is added with a light emitting well transition layer compared with the well barrier layer of the first structure. The light-emitting well transition layer is used for stress transition from the barrier layer to the well layer, and facilitates incorporation of In the light-emitting well layer. Illustratively, the light emitting well transition layer is a GaN light emitting well transition layer or an AlInN light emitting well transition layer.
Illustratively, when the light emitting well transition layer is an AlInN light emitting well transition layer, the light emitting well transition layer is Al1-yInyN layer, 0.1<y<0.5。
The light emitting well protection layer comprises an AlInN layer. The growth temperature of the InGaN light-emitting well layer is lower than that of the light-emitting well protection layer, the growth temperature of the light-emitting well protection layer is lower than that of the GaN barrier layer, so that the growth temperature of the light-emitting well protection layer is between the growth temperatures of the InGaN light-emitting well layer and the GaN barrier layer, in the growth process, the low temperature of the InGaN light-emitting well layer can be gradually transited to the high temperature of the GaN barrier layer, and the light-emitting well protection layer comprises the AlInN layer, the lattice constant of the AlInN is between those of InGaN and GaN, and the AlInN can obtain higher crystal quality at a lower growth temperature, so that the crystal quality of an interface between well barriers can be improved; and under the protection of the light-emitting well protective layer, In the InGaN quantum well can be reduced or avoided being separated out, the incorporation content of In components In the quantum well is improved, and the recombination efficiency of carriers is improved.
Illustratively, embodiments of the present invention provide two structures of light emitting well protection layers. The light emitting well protection layer with the first structure is an AlInN layer; the light emitting well protection layer with the second structure comprises an AlInN layer and an AlN layer, and the AlN layer is located between the AlInN layer and the GaN barrier layer.
When the light emitting well protection layer only comprises the AlInN layer, the light emitting well protection layer has better crystal quality and a certain content of Al component, and the Al component can be used for improving the crystal quality of the layer and adjusting the energy band width. Compared with the light emitting well protective layer with the first structure, the light emitting well protective layer with the second structure is additionally provided with the AlN layer, the AlN layer can provide higher Al component content, and the interface quality of multiple quantum wells can be further enhanced.
Illustratively, in the light emitting well protection layer, the AlInN layer is Al1-xInxN layer, 0.1<x<0.5. Further, x is in the range of 0.1-0.2. In particular, when x is 0.13, Al is obtained0.87In0.13The lattice constant of N is perfectly matched with that of GaN, and the crystal quality of the layer is optimal.
Due to the obvious difference between the N-P doping efficiency and the electron-hole mobility, the light emitting well transition layers and the light emitting well protective layers which grow on the two sides of the light emitting well layer can improve the forbidden bandwidth on the two sides of the light emitting well layer due to the existence of the AlInN and the AlN layers, namely the incorporation of the Al component, and electrons can be better limited to the light emitting well layer to participate in optical recombination under the drive of LED current.
As for the growth temperature, illustratively, the growth temperature of the light emitting well transition layer is 750 to 900 ℃, the growth temperature of the InGaN light emitting well layer is 700 to 800 ℃, the growth temperature of the AlInN layer is 750 to 850 ℃, the growth temperature of the AlN layer is 800 to 900 ℃, and the growth temperature of the GaN barrier layer is 850 to 950 ℃.
As for the growth pressure, illustratively, the growth pressure of the light emitting well transition layer is 100torr to 500torr, the growth pressure of the InGaN light emitting well layer is 100torr to 500torr, the growth pressure of the AlInN layer is 50torr to 00torr, the growth pressure of the AlN layer is 50torr to 500torr, and the growth pressure of the GaN barrier layer is 100torr to 500 torr.
Regarding the thickness, illustratively, the growth thickness of the light emitting well transition layer is 0.5-2 nm, the thickness of the InGaN light emitting well layer is 2-4 nm, the thickness of the AlInN layer is 0.5-2 nm, the thickness of the AlN layer is 0.5-2 nm, and the thickness of the GaN barrier layer is 6-12 nm.
Illustratively, the total thickness of the light-emitting well protection layer may be less than or equal to 2nm, and the total thickness of the well barrier layer may be 10nm to 18 nm.
And step 208, depositing an electron barrier layer on the multi-quantum well layer.
Illustratively, the electron blocking layer is a P-type AlGaN layer, the growth temperature of the electron blocking layer is between 850 ℃ and 1050 ℃, and the growth pressure is between 100Torr and 500 Torr. The thickness of the electron blocking layer is between 20nm and 100 nm.
Step 209 is depositing a P-type GaN layer on the electron blocking layer.
Illustratively, the growth temperature of the P-type GaN layer is between 750 ℃ and 1080 ℃, the growth pressure is between 200Torr and 600Torr, and the growth thickness is between 50nm and 200 nm.
And step 210, depositing a P-type ohmic contact layer on the P-type GaN layer.
Illustratively, the thickness of the P-type ohmic contact layer is between 0.5nm and 10nm, the growth temperature range is 850 ℃ to 1050 ℃, and the growth pressure range is 100Torr to 600 Torr.
Illustratively, after the growth of the P-type ohmic contact layer is finished, the temperature in a reaction cavity of the MOCVD equipment is reduced, annealing treatment is carried out in a nitrogen atmosphere, the annealing temperature range is 650-850 ℃, the annealing treatment is carried out for 5-15 minutes, and the temperature is reduced to room temperature, so that epitaxial growth is completed.
Fig. 3 shows a GaN-based light emitting diode epitaxial wafer according to an embodiment of the present invention, which can be prepared by the method shown in fig. 1 or fig. 2. Referring to fig. 3, the light emitting diode epitaxial wafer includes: the substrate comprises a substrate 1, and a buffer layer 2, an undoped GaN layer 3, an N-type doped GaN layer 4, a low-temperature stress release layer 5, a multi-quantum well layer 6, an electron barrier layer 7, a P-type GaN layer 8 and a P-type ohmic contact layer 9 which are sequentially deposited on the substrate 1. The multiple quantum well layer 6 includes a plurality of stacked well barrier layers 60, and the well barrier layers 60 include an InGaN light emitting well layer 62, a light emitting well protective layer 63, and a GaN barrier layer 64, which are sequentially stacked. The GaN barrier layer 63 in the well barrier layer 60 adjacent to the electron barrier layer 7 is in contact with the electron barrier layer 7. The light emitting well protection layer 63 includes an AlInN layer 631, the InGaN light emitting well layer 62 is a low-temperature InGaN light emitting well layer, the light emitting well protection layer 63 is a medium-temperature light emitting well protection layer, and the GaN barrier layer 64 is a high-temperature GaN barrier layer.
Illustratively, embodiments of the present invention provide two configurations of the well barrier layer 60.
In the first structure, referring to fig. 4, the well barrier layer 60 includes an InGaN light emitting well layer 62, a light emitting well protective layer 63, and a GaN barrier layer 64, which are sequentially stacked. The InGaN light emitting well layer 62 in the well barrier layer 60 near the low temperature stress relief layer 5 is in contact with the low temperature stress relief layer 5. The GaN barrier layer 64 in the well barrier layer 60 near the electron barrier layer 7 is in contact with the electron barrier layer 7. The growth temperature of the InGaN light emitting well layer 62 is lower than that of the light emitting well protective layer 63, and the growth temperature of the light emitting well protective layer 63 is lower than that of the GaN barrier layer 64.
In the second structure, referring to fig. 5, the well barrier layer 60 includes a light emitting well transition layer 61, an InGaN light emitting well layer 62, a light emitting well protective layer 63, and a GaN barrier layer 64, which are sequentially stacked. The light emitting well transition layer 61 in the well barrier layer 60 close to the low temperature stress release layer 5 is in contact with the low temperature stress release layer 5. The GaN barrier layer 64 in the well barrier layer 60 near the electron barrier layer 7 is in contact with the electron barrier layer 7. The growth temperature of the InGaN light emitting well layer 62 is lower than that of the light emitting well protective layer 63, and the growth temperature of the light emitting well protective layer 63 is lower than that of the GaN barrier layer 64.
The well barrier layer 60 of the second structure is added with a light emitting well transition layer 61 than the well barrier layer 60 of the first structure. The light emitting well transition layer 61 is used for stress transition from the barrier layer to the well layer, facilitating incorporation of In the light emitting well layer. Illustratively, light emitting well transition layer 61 is a GaN light emitting well transition layer or an AlInN light emitting well transition layer.
Illustratively, when light emitting well transition layer 61 is an AlInN light emitting well transition layer, light emitting well transition layer 61 is Al1- yInyN layer, 0.1<y<0.5. For example, y is 0.2.
The light emitting well protective layer 63 includes an AlInN layer 631. Because the growth temperature of the InGaN light emitting well layer 62 is lower than the growth temperature of the light emitting well protection layer 63, and the growth temperature of the light emitting well protection layer 63 is lower than the growth temperature of the GaN barrier layer 64, the growth temperature of the light emitting well protection layer 63 is between the growth temperatures of the InGaN light emitting well layer 62 and the GaN barrier layer 64, and in the growth process, the low temperature of the InGaN light emitting well layer 62 can be gradually transited to the high temperature of the GaN barrier layer 64, and because the light emitting well protection layer 63 comprises the AlInN layer 631, the lattice constant of the AlInN is between the lattice constants of InGaN and GaN, and the AlInN can obtain higher crystal quality at a lower growth temperature, the crystal quality of an interface between wells can be improved; in addition, under the protection of the light-emitting well protection layer 63, In the InGaN quantum well 62 can be reduced or prevented from being separated out, the incorporation content of In components In the quantum well is improved, and the recombination efficiency of carriers is improved.
Illustratively, the embodiment of the present invention provides two structures of the light emitting well protective layer 63. Referring to fig. 3, the light emitting well protective layer 63 of the first structure is an AlInN layer 631; referring to fig. 5, the light emitting well protective layer 63 of the second structure includes an AlInN layer 631 and an AlN layer 632, the AlN layer 632 being located between the AlInN layer 631 and the GaN barrier layer 64. AlN layer 632 and AlInN layer 631 are medium temperature AlN and AlInN layers, respectively.
When the light emitting well protective layer 63 includes only the AlInN layer 631, it has a better crystal quality and a certain content of Al component, which can be used to improve the crystal quality of the layer and adjust the energy band width. Compared with the light emitting well protection layer 63 with the first structure, the light emitting well protection layer 63 with the second structure is added with the AlN layer 632, and the AlN layer 632 can provide higher content of Al component and can further enhance interface quality of multiple quantum wells.
Illustratively, in light-emitting well protective layer 63, AlInN layer 631 is Al1-xInxN layer, 0.1<x<0.5. Such as x ═ 0.2. Further, x is in the range of 0.1-0.2. In particular, when x is 0.13, Al is obtained0.87In0.13The lattice constant of N is perfectly matched with that of GaN, and the crystal quality of the layer is optimal.
Due to the obvious difference between the N-P doping efficiency and the electron-hole mobility, the light emitting well transition layers and the light emitting well protective layers which grow on the two sides of the light emitting well layer can improve the forbidden bandwidth on the two sides of the light emitting well layer due to the existence of the AlInN and the AlN layers, namely the incorporation of the Al component, and electrons can be better limited to the light emitting well layer to participate in optical recombination under the drive of LED current.
As for the growth temperature, illustratively, the growth temperature of the light emitting well transition layer 61 is 750 to 900 ℃, the growth temperature of the InGaN light emitting well layer 62 is 700 to 800 ℃, the growth temperature of the AlInN layer 631 is 750 to 850 ℃, the growth temperature of the AlN layer 632 is 800 to 900 ℃, and the growth temperature of the GaN barrier layer 64 is 850 to 950 ℃.
Regarding the thickness, illustratively, the growth thickness of the light emitting well transition layer 61 is 0.5 to 2nm, the thickness of the InGaN light emitting well layer 62 is 2 to 4nm, the thickness of the AlInN layer 631 is 0.5 to 2nm, the thickness of the AlN layer 632 is 0.5 to 2nm, and the thickness of the GaN barrier layer 64 is 6 to 12 nm.
Since the forbidden band width of the light emitting well protection layer 63 is higher than that of the GaN barrier layer 64, the injection efficiency of electrons and holes of the multiple quantum wells is reduced if the light emitting well protection layer 63 is too thick, and the well layer is not covered sufficiently if the light emitting well protection layer 63 is too thin. Illustratively, the total thickness of the light emitting well protective layer 63 may be less than or equal to 2 nm.
Illustratively, the total thickness of the well barrier layer 60 is 10nm to 18 nm. For example, the thickness of the light emitting well transition layer 61 is 1.0nm, the thickness of the InGaN light emitting well layer 62 may be 3.0nm, the thickness of the AlInN layer 631 in the light emitting well protection layer 63 is 1.5nm, the thickness of the AlN layer 632 is 1.0nm, and the thickness of the GaN barrier layer 64 is 8 nm.
In the embodiment of the invention, the multi-quantum well layer comprises a plurality of laminated well barrier layers, each well barrier layer comprises an InGaN light-emitting well layer, a light-emitting well protective layer and a GaN barrier layer which are sequentially laminated, the InGaN light-emitting well layer is a low-temperature InGaN light-emitting well layer, the light-emitting well protective layer is an intermediate-temperature light-emitting well protective layer, and the GaN barrier layer is a high-temperature GaN barrier layer, namely the growth temperature of the InGaN light-emitting well layer is lower than the growth temperature of the light-emitting well protective layer, the growth temperature of the light-emitting well protective layer is lower than the growth temperature of the GaN barrier layer, so that the growth temperature of the light-emitting well protective layer is between the growth temperatures of the InGaN light-emitting well layer and the GaN barrier layer, in the growth process, the low temperature of the InGaN light-emitting well layer can be gradually transited to the high temperature of the GaN barrier layer, and the light-emitting well protective layer comprises an, therefore, this is advantageous in improving the crystal quality of the interface between the well barriers; and under the protection of the light-emitting well protective layer, In the InGaN quantum well can be reduced or avoided being separated out, the incorporation content of In components In the quantum well is improved, and the recombination efficiency of carriers is improved.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (8)
1. A GaN-based light emitting diode epitaxial wafer, comprising:
the LED light-emitting device comprises a substrate, a buffer layer, a non-doped GaN layer, an N-type GaN layer, a low-temperature stress release layer, a multi-quantum well layer, an electronic barrier layer, a P-type GaN layer and a P-type ohmic contact layer, wherein the buffer layer, the non-doped GaN layer, the N-type GaN layer, the low-temperature stress release layer and the multi-quantum well layer are sequentially deposited on the substrate, the low-temperature stress release layer is a GaN layer inserted into InGaN, the multi-quantum well layer comprises a plurality of laminated well barrier layers, each well barrier layer comprises an InGaN light-emitting well layer, a medium-temperature light-emitting well protective layer and a GaN barrier layer which are sequentially laminated, the GaN barrier layer in the well barrier layer close to the electronic barrier layer is in contact with the electronic barrier layer, the medium-temperature light-emitting well protective layer comprises an AlInN layer, the InGaN light-emitting well layer is a low-temperature InGaN light,
the well barrier layer further comprises a light emitting well transition layer, the InGaN light emitting well layer is located between the light emitting well transition layer and the medium-temperature light emitting well protection layer, the light emitting well transition layer in the well barrier layer close to the low-temperature stress release layer is in contact with the low-temperature stress release layer, and the light emitting well transition layer is an AlInN light emitting well transition layer.
2. The epitaxial wafer of claim 1, wherein the AlInN layer is Al1-xInxN layer, 0.1<x<0.5。
3. The epitaxial wafer of claim 2, wherein the thickness of the InGaN light emitting well layer is 2-4 nm, the thickness of the AlInN layer is 0.5-2 nm, and the thickness of the GaN barrier layer is 6-12 nm.
4. The epitaxial wafer according to claim 1, wherein the AlN layer has a thickness of 0.5 to 2 nm.
5. The epitaxial wafer of claim 1, wherein the light emitting well transition layer is Al1-yInyN layer, 0.1<y<0.5。
6. The epitaxial wafer of claim 5, wherein the growth thickness of the light emitting well transition layer is 0.5-2 nm.
7. A preparation method of a GaN-based light emitting diode epitaxial wafer is characterized by comprising the following steps:
providing a substrate;
depositing a buffer layer, a non-doped GaN layer, an N-type GaN layer, a low-temperature stress release layer, a multi-quantum well layer, an electronic barrier layer, a P-type GaN layer and a P-type ohmic contact layer on the substrate in sequence, wherein the low-temperature stress release layer is a GaN layer inserted into InGaN;
the multiple quantum well layer comprises a plurality of stacked well barrier layers, each well barrier layer comprises an InGaN light-emitting well layer, a medium-temperature light-emitting well protective layer and a GaN barrier layer which are sequentially stacked, the GaN barrier layer in the well barrier layer close to the electron barrier layer is in contact with the electron barrier layer, the medium-temperature light-emitting well protective layer comprises an AlInN layer, the growth temperature of the InGaN light-emitting well layer is lower than that of the medium-temperature light-emitting well protective layer, the growth temperature of the medium-temperature light-emitting well protective layer is lower than that of the GaN barrier layer, the medium-temperature light-emitting well protective layer further comprises an AlN layer, the AlN layer is located between the AlInN layer and the GaN barrier layer, the AlN layer is a medium-temperature AlN layer, the well barrier layer further comprises a light-emitting well transition layer, the InGaN light-emitting well layer is located between the light-emitting well transition layer and the medium-temperature light-emitting well protective layer, and the light-emitting well transition layer in the, the light emitting well transition layer is an AlInN light emitting well transition layer.
8. The method according to claim 7, wherein the InGaN light emitting well layer is grown at a temperature of 700 ℃ to 800 ℃, the AlInN layer is grown at a temperature of 750 ℃ to 850 ℃, and the GaN barrier layer is grown at a temperature of 850 ℃ to 950 ℃.
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| CN110629197B (en) * | 2019-09-24 | 2021-09-07 | 湘能华磊光电股份有限公司 | LED epitaxial structure growth method |
| CN111900237A (en) * | 2020-08-13 | 2020-11-06 | 厦门乾照光电股份有限公司 | Ultraviolet LED chip and manufacturing method thereof |
| CN113451460B (en) * | 2020-11-20 | 2022-07-22 | 重庆康佳光电技术研究院有限公司 | Light emitting device and method of manufacturing the same |
| CN112993099B (en) * | 2021-02-09 | 2022-06-10 | 厦门乾照光电股份有限公司 | Manufacturing method of LED chip with protective layer |
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