CN109104204B - 用于混合定时恢复的装置、***和方法 - Google Patents

用于混合定时恢复的装置、***和方法 Download PDF

Info

Publication number
CN109104204B
CN109104204B CN201810635583.3A CN201810635583A CN109104204B CN 109104204 B CN109104204 B CN 109104204B CN 201810635583 A CN201810635583 A CN 201810635583A CN 109104204 B CN109104204 B CN 109104204B
Authority
CN
China
Prior art keywords
phase
digital
value
interpolator
control signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810635583.3A
Other languages
English (en)
Other versions
CN109104204A (zh
Inventor
J·贝洛拉多
M·马罗
吴征
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seagate Technology LLC
Original Assignee
Seagate Technology LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seagate Technology LLC filed Critical Seagate Technology LLC
Publication of CN109104204A publication Critical patent/CN109104204A/zh
Application granted granted Critical
Publication of CN109104204B publication Critical patent/CN109104204B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10037—A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03878—Line equalisers; line build-out devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/3707—Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
    • G11B5/48—Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed
    • G11B5/58—Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed with provision for moving the head for the purpose of maintaining alignment of the head relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track following
    • G11B5/596—Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed with provision for moving the head for the purpose of maintaining alignment of the head relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track following for track following on disks
    • G11B5/59633—Servo formatting
    • G11B5/59666—Self servo writing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/102—Program control for peripheral devices where the programme performs an interfacing function, e.g. device driver
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10046—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter
    • G11B20/10055—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter using partial response filtering when writing the signal to the medium or reading it therefrom
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10222—Improvement or modification of read or write signals clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10222—Improvement or modification of read or write signals clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation
    • G11B20/1024—Improvement or modification of read or write signals clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation wherein a phase-locked loop [PLL] is used
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
    • G11B5/48—Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed
    • G11B5/58—Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed with provision for moving the head for the purpose of maintaining alignment of the head relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track following
    • G11B5/596—Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed with provision for moving the head for the purpose of maintaining alignment of the head relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track following for track following on disks
    • G11B5/59633—Servo formatting
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/001—Analogue/digital/analogue conversion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4138—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors soft-output Viterbi algorithm based decoding, i.e. Viterbi decoding with weighted decisions
    • H03M13/4146—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors soft-output Viterbi algorithm based decoding, i.e. Viterbi decoding with weighted decisions soft-output Viterbi decoding according to Battail and Hagenauer in which the soft-output is determined using path metric differences along the maximum-likelihood path, i.e. "SOVA" decoding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used
    • H04J3/0617—Systems characterised by the synchronising information used the synchronising signal being characterised by the frequency or phase
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/20—Automatic control
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2948—Iterative decoding
    • H03M13/2951—Iterative decoding using iteration stopping criteria
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7097—Interference-related aspects
    • H04B1/7103—Interference-related aspects the interference being multiple access interference
    • H04B1/7105—Joint detection techniques, e.g. linear detectors
    • H04B1/71055—Joint detection techniques, e.g. linear detectors using minimum mean squared error [MMSE] detector
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
    • H04L7/0025—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of clock signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
    • H04L7/0029—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of received data signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Signal Processing (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Probability & Statistics with Applications (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Error Detection And Correction (AREA)
  • Digital Magnetic Recording (AREA)
  • Moving Of The Head To Find And Align With The Track (AREA)
  • Analogue/Digital Conversion (AREA)
  • Manipulation Of Pulses (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Lubricants (AREA)

Abstract

本发明题为“用于混合定时恢复的装置、***和方法”。本主题申请涉及用于混合定时恢复的装置、***和方法。本发明提供了一种装置，所述装置可包括电路，所述电路被配置为接收相位控制值信号的第一相位控制值，生成相位内插器控制信号的第一相位内插器控制信号值，并且生成数字内插器控制信号的第一数字内插器控制信号值。所述装置能够进一步被配置为基于所述第一相位内插器控制信号值对时钟信号进行相位内插以产生相移时钟信号，并且基于所述第一数字内插器信号值对数字样本进行数字内插，以基于所述第一相位控制值产生具有有效相位的相移数字样本，所述数字样本使用所述相移时钟信号作为采样时钟生成。

Description

用于混合定时恢复的装置、***和方法
技术领域
本发明涉及混合定时恢复，并且具体地涉及用于混合定时恢复的装置、***和方法。
背景技术
本发明涉及混合定时恢复。
发明内容
在某些实施方案中，一种装置可包括电路，所述电路被配置为接收相位控制值信号的第一相位控制值，生成相位内插器控制信号的第一相位内插器控制信号值，并且生成数字内插器控制信号的第一数字内插器控制信号值。该装置可以进一步被配置为基于第一相位内插器控制信号值对时钟信号进行相位内插以产生相移时钟信号，并且基于第一数字内插器信号值对数字样本进行数字内插，以基于第一相位控制值产生具有有效相位的相移数字样本，所述数字样本使用相移时钟信号作为采样时钟来生成。
在某些实施方案中，***可包括定时控制电路，该定时控制电路被配置为接收相位控制信号的第一相位控制值，基于相位控制信号生成相位内插器控制信号，并且基于相位控制信号生成数字内插器控制信号的第一数字内插器控制信号值。该***还可包括相位内插器，该相位内插器基于相位内插器控制信号来对时钟信号进行相位内插以产生相移时钟信号，以及数字内插器，该数字内插器基于数字内插器信号对数字样本进行数字内插以产生相移数字样本；基于数字内插器控制信号的第一数字内插器控制值对数字样本的第一数字样本进行内插，以基于第一相位控制值产生具有有效相位的第一相移数字样本，所述数字样本使用相移时钟信号作为采样时钟来生成。
在某些实施方案中，方法可包括由定时控制电路接收相位控制值信号的第一相位控制值，由定时控制电路生成相位内插器控制信号的第一相位内插器控制信号值，以及由定时控制电路生成数字内插器控制信号的第一数字内插器控制信号值。该方法还可包括基于第一相位内插器控制信号值对时钟信号进行相位内插以产生相移时钟信号，并且基于第一数字内插器信号对数字样本进行数字内插，以基于第一相位控制值产生具有有效相位的相移数字样本，所述数字样本使用相移时钟信号作为采样时钟来生成。
附图说明
图1是根据本公开的某些实施方案的可以包括混合定时恢复功能的通信信道的框图；
图2是根据本公开的某些实施方案的用于包括混合定时恢复功能的通信信道的采样电路的框图；
图3示出了根据本公开的某些实施方案的定时恢复过程中的定时控制电路的示例性操作；
图4是根据本公开的某些实施方案的混合定时恢复功能的方法的流程图；
图5是根据本公开的某些实施方案的混合定时恢复功能的方法的流程图；
图6是根据本公开的某些实施方案的包括混合定时恢复功能的***的框图。
具体实施方式
在下面对实施方案的详细描述中，参考了形成其一部分的附图，并且其中通过例示示出。应当理解，所述的各种实施方案的特征可以组合，可使用其他实施方案，并且可在不脱离本公开的范围的情况下进行结构变化。还应当理解，在不脱离本公开的范围的情况下，本文的各种实施方案和示例的特征可以组合、交换或移除。
根据各种实施方案，本文所述的方法和功能可被实现为在计算机处理器或控制器上运行的一个或多个软件程序。根据另一个实施方案，本文所述的方法和功能可被实现为在计算设备(例如，使用磁盘驱动器的个人计算机)上运行的一个或多个软件程序。包括但不限于专用集成电路、可编程逻辑阵列和其他硬件设备的专用硬件具体实施同样可被构造为实现本文所述的方法和功能。此外，本文所述的方法可被实现为包括指令的计算机可读存储介质或设备，所述指令在被执行时使得处理器执行所述方法。
本公开整体涉及同步数字***，并且在一些实施方案中，本公开可涉及结合时钟控制定时恢复和内插定时恢复两者的混合定时恢复方法。
一些***诸如电***、电子***、马达驱动***、处理***或其他***可接收所关注的信号并处理该信号。例如，通信***或磁性记录存储***的读取信道可接收模拟输入信号并对输入信号进行采样以生成数字化样本。在一些***中，数字化信号的采样可在施加到数字接收机之前与输入信号的相位同步。例如，数字接收机可以是检测器、解码器、滤波器或其他数字***。
如上所述，一些实施方案可包括混合定时恢复部件，其可结合时钟控制定时恢复功能和内插定时恢复功能。
在一些示例中，时钟控制的定时恢复功能可改变时钟信号的相位，以基于相位控制值来生成相移时钟信号。然后，相移时钟信号可用于对数字接收机的逻辑(例如，通过模数转换器(ADC))进行采样和计时。相位控制值可以是来自目标相的时钟信号相位偏差的估计。当相位控制值大于相位步长时，时钟信号的相移可操作以将时钟信号的相位移动相位步长(例如，在每个样本基础上或在每多个样本基础上)。在一些实施方案中，相位步长或步长可为该采样时钟相位的瞬时变化的量值受限的最大值。可选择相位步长，以便在数字逻辑上闭合定时时固定到最小长度时钟周期。如果时钟相位的期望变化超过此值，则可通过调节多个周期的相位来实现，其中时钟相位中的每个变化(或步骤)不超过指定的最大值。
此外，内插定时恢复功能可对使用相移时钟信号生成的样本(例如，使用内插滤波器)进行相位调节。例如，当相位控制值大于相位步长时，内插定时恢复功能可以以相位控制值超过相位步长的量执行样本的相位调节。
这种***的一个示例将在下文参照图1进行论述。
参考图1，示出了可包括混合定时恢复功能的通信信道的框图，并且其通常被指定为100。***100可包括可以耦接至采样电路104的模拟前端(AFE)102。采样电路104可耦接至数字接收机106，该数字接收机可又耦接至采样电路104。另外，***100可以包括可耦接至采样电路104的锁相环(PLL)108。
AFE 102、采样电路104、数字接收机106和PLL 108中的每一者可以是单独的电路、片上***(SOC)、固件、处理器或未列出的其他***，或其任何组合。
在操作中，AFE 102可以接收连续时间信号(z(t))110并且执行处理诸如模拟滤波和施加增益以产生连续时间信号x(t)112。此外，PLL 108可操作以产生时钟信号(c)116。
采样电路104可以接收连续时间信号x(t)112、PLL时钟信号(c)116和相位控制值120。采样电路还可以使用混合定时恢复方法来生成相移样本序列xk 114和相移时钟信号
Figure BDA0001701441490000041
118。下文相对于图2提供采样电路104的示例性实施方案的操作的附加细节。
数字接收机106可以接收相移样本序列xk 114和相移时钟信号
Figure BDA0001701441490000043
118。数字接收机106然后可以使用相移时钟信号
Figure BDA0001701441490000042
118来处理相移样本序列xk 114。此外，数字接收机106可确定或估计时钟信号的相位与目标相位的偏差，并且可使用该偏差来调节所需的相位，并将所需的相位返回到采样电路104作为相位控制值120。在一些实施方案中，数字接收机106可不限于采样电路104的混合定时恢复方法，并且对于允许的相位控制值120的变化可能没有限制。
参见图2，示出了可包括混合定时恢复功能的通信信道***100的采样电路104的框图，并且其通常被指定为200。图2的采样电路104可包括模数转换器(ADC)202，该模数转换器可耦接至数字内插器204。采样电路104还可包括可耦接至ADC 202的相位内插器206。此外，采样电路104可包括定时控制电路208，该定时控制电路可耦接至数字内插器204和相位内插器206。
ADC 202、数字内插器204、相位内插器206和时序控制电路208中的每一者可以是单独的电路、片上***(SOC)、固件、处理器或未列出的其他***，或其任何组合。
一般来讲，采样电路104的部件可如下操作。
定时控制电路208可以基于相位控制120产生控制信号p0,k 210和p1,k 212，并且将控制信号p0,k 210和p1,k 212输出至数字内插器204和相位内插器206。
相位内插器206可接收来自PLL 108的时钟信号c 116和相位内插器控制信号p0,k，并且基于此生成相移时钟信号
Figure BDA0001701441490000051
118。在一些示例中，相位内插器206可以是可以调节输入时钟信号的相位的电路。
ADC 202可以接收连续时间信号x(t)112和相移时钟信号
Figure BDA0001701441490000053
118。ADC 202可以基于相移时钟信号
Figure BDA0001701441490000052
118以间隔对连续时间信号x(t)112进行采样和量化以产生数字化的样本序列xADC 214。
数字内插器204可以接收数字化的样本序列xADC 214和数字内插器控制信号p1,k212。数字内插器204可以基于数字内插器控制信号p1,k 212来执行数字化的样本序列xADC214的数字内插以生成相移样本序列xk 114。在一些示例中，数字内插器206可以是可以对样本进行数字相移的电路。
如上所述，定时控制电路208可以控制相位内插器206以将ADC的采样时钟(例如，相移时钟信号
Figure BDA0001701441490000054
118)的步长改变为相位控制值120(例如，在多个样本上)，同时控制数字内插器204对由ADC输出的样本xADC214的数字化序列进行数字内插，以恢复相位步长和相位控制值120之间的其余相位差。如上所述，相位移位时钟信号
Figure BDA0001701441490000055
118可按相位步长的増量改变，因为可能存在可施加于相位内插器206的最大相位变化，而不会导致数字接收机106的逻辑中的定时问题。在一些此类示例中，相位步长可以是大于零(0)，并且小于或等于可通过相位内插器206施加的最大相变的任何值，而不会导致数字接收机逻辑中的定时问题。
此外，在一些示例中，定时控制电路208可补偿在相位内插器控制信号p0,k被改变时以及当该改变被反映在数字化的样本序列xADC 214中时的延迟(D)。具体地讲，数字内插器控制信号p1,k 212的产生可以补偿延迟(D)。具体地讲，因为数字内插器控制信号p1,k可以没有延迟地改变相移样本序列xk 114的相位，定时控制电路208可以生成数字内插器控制信号p1,k，以消除相位内插器控制信号p0,k的影响中的延迟的影响。图3中示出了这种实施方案中的定时控制模块的操作的示例。
图3示出了根据本公开的某些实施方案的定时恢复过程中的定时控制电路208的示例性操作。具体地讲，图3示出了定时控制电路208的输入值，具体地讲是相位控制值120和定时控制电路208的输出(即控制信号p0,k 210和p1,k 212)的时序图。在根据图3的一些示例中，相位控制可以被假定为指定期望的采样相位，其可以以采样率来最大化信号折叠。提供最大信号折叠的相位可为采样的最佳相位。换句话讲，当p0,k 210等于相位控制值120时，可提供最佳样本。然而，由于ADC的延迟以及相位内插器控制信号p0,k 210的最大变化的限制，但在数字逻辑中未引起误差的情况下，***可能无法立即将p0,k 210改变为相位控制值。在此类情况下，根据图3的一些示例可在多个周期内将相位内插器控制信号p0,k 210移步到相位控制值120，并且可利用数字内插器对相位控制值120的相位进行数字内插而没有延迟。
如图所示，相位控制值120可在时间t1处从值x变化为值y。在例示的示例中，相位控制值120可由y-x改变，其中(y-x)大于相位内插器控制信号p0,k 210的相位步长DMAX 302。此外，在例示的示例中，在时间t1之前，p0,k＝x且p1,k＝0，因此，连续输入信号可在相位x处采样。在时间t1处，由数字接收机生成的相位控制值120从x变为y。作为响应，定时控制电路208可立即改变数字内插器控制信号p1,k 212为(y-x)，并且可以以每采样周期(T)306为DMAX302的速率(例如，相位步长)开始摆动或步移相位内插器控制信号p0,k 210。在一些示例中，每个样本周期可对应于相移时钟信号
Figure BDA0001701441490000061
118的时钟周期。在其他示例中，相位可以按照可以包括每周期多个样本的每个周期步移(例如，以每周期四个样本)。在图3中，在p0,k时序图中示出了两条线。具体地讲，p0,k时序图中的实线可以示出相位内插器控制信号p0,k 210的值，并且虚线可以示出相位内插器控制信号p0,k 210对ADC输出(例如，在样本xADC 214上)的影响。还如图所示，相位内插器控制信号p0,k 210对样本xADC 214的影响从相位内插器控制信号p0,k 210改变的时间延迟了延迟(D)304。这样，在时间或采样周期(t1+D)，相位内插器控制信号p0,k 210的变化可以开始对样本xADC 214起作用。
另外，随着相位内插器控制信号p0,k 210的变化开始对样本xADC 214起作用，并且假设相位控制值120不改变，定时控制电路208可以开始对数字内插器控制信号p1,k 212向下步移，以确保相移采样序列xk 114中的总有效相移等于相位控制值120。到时间t2时，相位内插器控制信号p0,k 210的值可以等于相位控制值120，具体为y，并且p1,k 212可以等于零。
如图3的示例所示，定时控制电路208可以在相位步长的限制内以及在应用p0,k210及其对ADC输出(例如，xADC 214)的影响之间的任何延迟(D)内，尽可能快地驱动相位内插器控制信号p0,k 210以及通过扩展驱动ADC的采样相位至结构性折叠的点。在一些情况下，由于p0,k 210的变化与其对ADC输出(例如，xADC 214)的影响之间的延迟(D)，即使当相位控制值120的变化小于DMAX时，p1,k 212的值也可以是非零的。这可确保相位控制值120的值的变化可即时反映在生成用于向数字接收机106施加的相移样本序列xk的值中。
如图3中的示例所示，定时控制电路208可操作以将在下面的时间k处由Pk表示的相位控制值120分配到两个相位控制信号p0,k和p1,k之间。在一些实施方案中，因为时钟边缘可以及时前进，因此Pk可以具有相位集合{0,1,…,N-1}中的值并且可以包入值中。例如，当Pk＝N-1和Pk+1＝0时，时钟边缘可通过(1+1/N)T)分开。
如上所述，时序控制电路208可以操作，使得在每个时间或采样周期k，用于生成采样(xk)的有效相位等于相位控制值(Pk)和采样时钟的相位，如由相位内插器控制信号p0,k210给相位内插器所指定的，可以在相位步长DMAX 302内尽可能快地步移到当前相位控制值(Pk)的值。
由于p0,k 210被指定时和其可能在ADC输出xADC 214中被反映时之间的延迟(D)304，并且因为可以使用p1,k 212在数字内插器上施加立即相移，周期或时间k的有效相位(Pk,eff)可以通过下式确定：
Pk,eff＝(p0,k-D+p1,k)。 (1)
其中p0,k-D为来自K之前的D个采样周期的相位内插器控制信号210的值。在一些示例中，如果在采样周期或时钟周期中测量D，则定时控制电路208可包括存储相位内插器控制信号210的前D值的缓冲器(诸如延迟线)。在其他示例中，相位内插器控制信号210的前D值可被存储在定时控制模块208外部的存储器中，并且由该定时控制模块访问。如上所述，定时控制模块208可以确定相位内插器控制信号p0,k 210和数字内插器控制信号p1,k 212，使得有效相位Pk,eff可以等于相位控制值(Pk)。此关系可表示为：
Pk,eff＝Pk＝(p0,k-D+p1,k)， (2)
为了实现这种关系，定时控制模块208可以将数字内插器控制信号p1,k确定为：
p1,k＝(Pk-p0,k-D)。 (3)
在一些实施方案中，当调节相位内插器控制信号p0,k 210的值时，定时控制电路208可首先生成如下误差：
ek＝(Pk-p0,k)。 (4)
接下来，定时控制电路208可以确定对于相位内插器控制信号p0,k 210的调节应当施加哪个方向以在最短时间段内达到Pk。例如，如果相位数为64(例如N＝64)，则相位控制值120为55(例如，Pk＝55)，并且相位内插器控制信号为6(例如，p0,k＝6)，(4)中的误差可以被计算为(55-6)＝49。虽然相位内插器控制信号p0,k可以被调节49来达到相位控制值，但将相位内插器控制信号p0,k移动(49-64)＝-15更快。因此，定时控制电路208可解包误差。例如，如果相位控制值Pk＝10并且相位内插器控制信号p0,k＝63，则误差ek可以被确定为(10-63)＝-53，其可以进而被解包为(64-53)＝11。如果解包误差大于相位步长，那么得到的解包误差将饱和到相位步长。然后可以使用饱和解包误差来调节相位内插器控制信号p0,k210。定时控制模块208然后可以计算由(3)给出的p1,k的下一个值。
图4和图5例示了用于采样电路104和定时控制电路208的操作的示例性过程。
参考图4，示出了混合定时恢复的方法的流程图，并且通常将其指定为400。更具体地讲，流程图400可以是以上相对于图1至图3详述的采样电路104的操作的一般流程。
在操作中，***可在402处接收相位控制值。例如，该***可以从数字接收机接收相位控制值，该数字接收机可以表示由数字接收机最近处理的样本中的定时误差。在404处，定时控制电路可基于相位控制值和延迟D的相位内插器控制信号来确定数字内插控制信号(例如，定时控制模块可以输出相位内插器控制信号的时间与相位内插器控制信号的输出可能影响ADC输出的样本的时间之间的延迟)。在406处，***可基于相位内插器控制信号(由于相位内插器和ADC块的固有延迟，可相对于其当前指定值延迟D)而产生相移时钟信号，并且基于相移时钟信号生成ADC样本。数字内插器然后可以在408处基于数字内插控制信号在ADC样本上执行数字内插。接下来，定时控制电路可以在410处基于相位步长，当前相位内插器控制信号和相位控制值来更新当前时间的相位内插器控制信号。定时控制电路的逻辑的更详细的示例性实施方案由图5提供。
参考图5，示出了混合定时恢复的方法的流程图，并且通常将其指定为500。更具体地讲，流程图500可以是如上面相对于图1至图4所详细描述的定时控制电路的操作流程。
在502处，定时控制电路可确定相位内插器控制信号p0,k是否等于相位控制值Pk。如果是，则该过程可继续至504。否则，该过程可继续至506。在504处，定时控制电路可设定p1,k+1至(Pk-p0,k-D)的值。该过程随后可返回到502以用于下一个Pk。在506处，定时控制电路可确定误差值ek为(Pk-p0,k)并且继续至508。
然后，定时控制电路可执行误差解包。具体地讲，在508处，定时控制电路可确定误差e k是否大于相位总数的一半(例如，ek>N/2？)。如果是，则该过程可继续至510。否则，该过程可继续至512。在510处，定时控制电路可以将误差ek设定为(ek-N)。该过程随后可继续至516。在512处，时序控制电路可以确定误差ek是否小于总相位数的负数的一半(例如，ek<-N/2？)。如果是，则该过程可继续至514。否则，该过程可继续至516。在514处，定时控制电路可以将误差ek设定为(N+ek)。该过程随后可继续至516。
然后，定时控制电路可执行误差饱和。具体地讲，在516处，定时控制电路可以确定误差ek是否大于相位步长DMax(例如，ek>DMax？)。如果是，则该过程可继续至518。否则，该过程可继续至520。在518处，定时控制电路可将误差ek设定为相位步长DMax。该过程然后可继续至524。在520处，定时控制电路可确定误差ek是否小于相位步长DMax的负值(例如，ek<-DMax？)。如果是，则该过程可继续至522。否则，该过程可继续至524。在522处，定时控制电路可以将误差ek设定为相位步长-DMax的负值。该过程然后可继续至524。
在524处，定时控制电路可使用解包和饱和的误差来将p0,k+1确定为p0,k+ek。然后如上文所述，该方法可返回至506。
针对方法400和方法500列出的所有步骤可以应用于同步定时***。根据本公开，许多变型形式将是显而易见的。用于执行该方法中的操作的组件和电路可以是分立的，或者集成到片上***(SOC)或其他电路中。此外，这些步骤可以在处理器(例如，数字信号处理器)中执行、在软件中实现、经由固件实现或通过其他手段来执行。
参考图6，示出了包括混合定时恢复的***的框图，并且其通常被指定为600。***600可以是数据存储设备(DSD)的示例，并且可以是***100的示例性具体实施。DSD 616可以任选地连接至主机设备614并且可从该主机设备移除，该主机设备可以是具有存储数据的设备或***，诸如台式计算机、膝上型计算机、服务器、数字视频录像机、影印机、电话、音乐播放器、未列出的其他电子设备或***，或者它们的任何组合。数据存储设备616可经由基于硬件/固件的主机接口电路612与主机设备614进行通信，该主机接口电路可包括允许DSD 616与主机614物理连接和断开连接的连接器(未示出)。
DSD 616可包括可以是可编程控制器的***处理器602以及相关联的存储器604。***处理器602可以是片上***(SOC)的一部分。缓冲器606可以在读取和写入操作期间临时存储数据，并且可包括命令队列。读取/写入(R/W)信道610可以在对数据存储介质608进行写入操作期间对数据进行编码，并且在从数据存储介质进行读取操作期间对数据进行重构。数据存储介质608被示出和描述为硬盘驱动器，但也可以是其他类型的磁介质，诸如闪存介质、光学介质或其他介质，或者它们的任何组合。
R/W信道610可以一次接收来自多于一个数据存储介质的数据，并且在一些实施方案中，还可以同时接收诸如来自读取头的多于一个输出的多个数据信号。例如，具有二维磁记录(TDMR)***的存储***可具有多个读取或记录元件，并且可以同时或几乎同时从两个轨道进行读取。多维录音(MDR)***可以接收来自多个源的两个或更多个输入(例如，记录头、闪存、光学存储器等)。R/W信道610可组合多个输入并提供单个输出，如本文的示例所述。
框618可以实现***和方法100至500的全部或部分***和功能。在一些实施方案中，框618可以是集成到R/W信道610中的独立电路，被包括在片上***、固件、软件或它们的任何组合中。
本文所述的例示、示例和实施方案旨在提供各种实施方案的结构的一般理解。这些说明并非旨在用作采用本文所述结构或方法的装置和***的所有元件和特征的完整描述。在查看本公开后，许多其他实施方案对于本领域技术人员而言可以是显而易见的。可通过本公开利用并得到其他实施方案，使得可在不脱离本公开的范围的情况下进行结构和逻辑替换和变化。例如，附图和以上描述提供了可改变的架构的示例，诸如***的设计要求。此外，虽然在本文中已说明和描述了具体实施方案，但应当理解，被设计为实现相同或相似目的的任何后续布置可以替代所示的具体实施方案。
本公开旨在覆盖各种实施方案的任何和全部后续改型或变型。在查看说明书后，上述示例的组合以及本文中未具体描述的其他实施方案对于本领域技术人员而言将是显而易见的。此外，图示仅仅是代表性的，可能未按比例绘制。图示中的某些比例可能被放大，而其他比例可能被缩小。因此，本公开和附图被认为是例示性的，而非限制性的。

Claims (20)

1.一种用于混合定时恢复的装置，包括：
电路，所述电路被配置为：
接收相位控制值信号的第一相位控制值；
生成相位内插器控制信号的第一相位内插器控制信号值；
生成数字内插器控制信号的第一数字内插器控制信号值；
基于所述第一相位内插器控制信号值对时钟信号进行相位内插以产生相移时钟信号；并且
基于所述第一数字内插器信号值对数字样本进行数字内插，以基于所述第一相位控制值产生具有有效相位的相移数字样本，所述数字样本是使用所述相移时钟信号作为采样时钟生成的。
2.根据权利要求1所述的装置，还包括所述电路，所述电路还包括模数转换器(ADC)，并且所述ADC被配置为基于所述相移时钟信号对输入信号进行采样以产生包括所述数字样本的数字样本。
3.根据权利要求2所述的装置，还包括所述电路，所述电路进一步被配置为通过逐个周期地将所述相位内插器控制信号朝向当前采样周期的所述相位控制值信号的当前值步移来执行所述相位内插器控制信号的生成。
4.根据权利要求3所述的装置，还包括所述电路，所述电路进一步被配置为通过以下操作来执行所述相位内插器控制信号朝向所述当前相位控制值的所述步移：
确定所述相位内插器控制信号的当前值与所述当前相位控制值之间的差；
对所述差执行误差解包，以产生解包的差；以及
基于相位步长来对所述解包的差执行误差饱和，以产生解包的饱和差；以及
基于所述解包的饱和差和所述相位内插器控制信号的所述当前值来更新所述相位内插器控制信号的当前值。
5.根据权利要求3所述的装置，还包括：
相位内插器，所述相位内插器基于所述相位内插器控制信号来执行所述时钟信号的相位内插以产生所述相移时钟信号；
所述第一相位内插器控制值是基于第二相位控制值生成的，所述第二相位控制值在比其中接收到所述第一相位控制值的第二采样周期早延迟周期的第一采样周期中被接收。
6.根据权利要求3所述的装置，还包括：
缓冲器，所述缓冲器缓冲相位内插器控制信号值达至少一个延迟周期；
数字内插器，所述数字内插器基于所述数字内插器信号来执行由所述ADC生成的数字样本的所述数字内插以产生相移数字样本，所述数字内插器信号是基于当前相位控制值与在比第一当前采样周期早延迟周期的采样周期中生成的相位内插器控制信号值的差生成的。
7.根据权利要求6所述的装置，还包括处理所述相移数字样本的数字接收机，所述数字接收机的逻辑基于所述相移时钟信号计时。
8.根据权利要求1所述的装置，还包括所述数字接收机，所述数字接收机为解码器、滤波器或检测器中的一者。
9.根据权利要求1所述的装置，还包括所述数字接收机，所述数字接收机进一步被配置为生成所述相位控制信号。
10.一种用于混合定时恢复的***，包括：
定时控制电路，所述定时控制电路被配置为：
接收相位控制信号的第一相位控制值；
基于所述相位控制信号生成相位内插器控制信号；
基于所述相位控制信号生成数字内插器控制信号的第一数字内插器控制信号值；相位内插器，所述相位内插器基于所述相位内插器控制信号对时钟信号进行相位内插以产生相移时钟信号；以及
数字内插器，所述数字内插器基于所述数字内插器信号对数字样本进行数字内插，以产生相移数字样本；基于所述数字内插器控制信号的第一数字内插器控制值对所述数字样本的第一数字样本进行内插，以基于所述第一相位控制值产生具有有效相位的第一相移数字样本，所述数字样本使用所述相移时钟信号作为采样时钟来生成。
11.根据权利要求10所述的***，还包括：
模数转换器(ADC)，所述模数转换器被配置为基于所述相移时钟信号对输入信号进行采样以产生所述数字样本。
12.根据权利要求11所述的***，还包括所述定时控制电路，所述定时控制电路被进一步配置为：
通过逐个周期地将所述相位内插器控制信号朝向当前采样周期的所述相位控制值信号的所述当前值步移来执行所述相位内插器控制信号的生成。
13.根据权利要求12所述的***，还包括所述定时控制电路，所述定时控制电路进一步被配置为通过以下操作来执行所述相位内插器控制信号的朝向所述当前相位控制值的所述步移：
确定所述相位内插器控制信号的当前值与所述当前相位控制值之间的差；
对所述差执行误差解包，以产生解包的差；
基于相位步长来对所述解包的差执行误差饱和，以产生解包的饱和差；以及
基于所述解包的饱和差和所述相位内插器控制信号的所述当前值来更新所述相位内插器控制信号的所述当前值。
14.根据权利要求12所述的***，还包括：
第一相位内插器控制值，所述第一相位内插器控制值是基于第二相位控制值生成的，所述第二相位控制值在比其中接收到所述第一相位控制值的第二采样周期早延迟周期的第一采样周期中被接收；以及
第一数字样本，所述第一数字样本是使用所述相移时钟信号作为使用所述第一相位内插器控制值作为采样时钟内插的相位生成的。
15.根据权利要求12所述的***，还包括：
缓冲器，所述缓冲器缓冲所述相位内插器控制信号的值达至少一个延迟周期；以及
所述数字内插器信号，所述数字内插器信号是基于当前相位控制值与比当前采样周期早延迟周期生成的相位内插器控制信号值的差生成的。
16.根据权利要求10所述的***，还包括数字接收机，所述数字接收机处理所述相移数字采样，所述数字接收机的逻辑基于所述相移时钟信号计时，并且所述数字接收机被配置为生成所述相位控制信号。
17.一种用于混合定时恢复的方法，包括：
由定时控制电路接收相位控制值信号的第一相位控制值；
由所述定时控制电路生成相位内插器控制信号的第一相位内插器控制信号值；
由所述定时控制电路生成数字内插器控制信号的第一数字内插器控制信号值；
基于所述第一相位内插器控制信号值对时钟信号进行相位内插以产生相移时钟信号；以及
基于所述第一数字内插器信号对数字样本进行数字内插，以基于所述第一相位控制值产生具有有效相位的相移数字样本，所述数字样本使用所述相移时钟信号作为采样时钟生成。
18.根据权利要求17所述的方法，还包括：
通过以下操作通过逐个周期地将所述相位内插器控制信号朝向当前采样周期的所述相位控制值信号的所述当前值步移来执行所述相位内插器控制信号的生成：
确定所述相位内插器控制信号的当前值与所述当前相位控制值之间的差；
对所述差执行误差解包，以产生解包的差；
对所述解包的差执行误差饱和，以产生解包的饱和差；以及
基于所述解包的饱和差和所述相位内插器控制信号的所述当前值来更新所述相位内插器控制信号的所述当前值。
19.根据权利要求18所述的方法，还包括基于在比所述第一相位控制值早延迟周期的采样周期中接收的第二相位控制值来生成所述第一相位内插器控制值。
20.根据权利要求19所述的方法，还包括基于所述第一相位控制值和所述第一相位内插器控制信号值的差来生成所述数字内插器信号。
CN201810635583.3A 2017-06-20 2018-06-20 用于混合定时恢复的装置、***和方法 Active CN109104204B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201762522248P 2017-06-20 2017-06-20
US62/522,248 2017-06-20
US15/791,190 US10665256B2 (en) 2017-06-20 2017-10-23 Hybrid timing recovery
US15/791,190 2017-10-23

Publications (2)

Publication Number Publication Date
CN109104204A CN109104204A (zh) 2018-12-28
CN109104204B true CN109104204B (zh) 2020-09-22

Family

ID=62683652

Family Applications (3)

Application Number Title Priority Date Filing Date
CN201810616850.2A Active CN109104388B (zh) 2017-06-20 2018-06-15 用于正则化参数自适应的装置、***和方法
CN201810635583.3A Active CN109104204B (zh) 2017-06-20 2018-06-20 用于混合定时恢复的装置、***和方法
CN201810636877.8A Active CN109104200B (zh) 2017-06-20 2018-06-20 近似参数自适应

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN201810616850.2A Active CN109104388B (zh) 2017-06-20 2018-06-15 用于正则化参数自适应的装置、***和方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201810636877.8A Active CN109104200B (zh) 2017-06-20 2018-06-20 近似参数自适应

Country Status (4)

Country Link
US (14) US10014026B1 (zh)
CN (3) CN109104388B (zh)
SG (3) SG10201804852XA (zh)
TW (3) TWI701591B (zh)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2010339584B2 (en) 2009-12-31 2014-06-26 Commvault Systems, Inc. Systems and methods for performing data management operations using snapshots
US9606803B2 (en) * 2013-07-15 2017-03-28 Texas Instruments Incorporated Highly integrated scalable, flexible DSP megamodule architecture
US10152457B1 (en) 2016-10-25 2018-12-11 Seagate Technology Llc Target parameter adaptation
US10382166B1 (en) * 2017-02-22 2019-08-13 Seagate Technology Llc Constrained receiver parameter optimization
US10014026B1 (en) 2017-06-20 2018-07-03 Seagate Technology Llc Head delay calibration and tracking in MSMR systems
GB2566760B (en) * 2017-10-20 2019-10-23 Please Hold Uk Ltd Audio Signal
GB2566759B8 (en) 2017-10-20 2021-12-08 Please Hold Uk Ltd Encoding identifiers to produce audio identifiers from a plurality of audio bitstreams
JP6813474B2 (ja) * 2017-12-26 2021-01-13 株式会社東芝 磁気ディスク装置及びリード／ライトオフセット補正方法
US11022511B2 (en) 2018-04-18 2021-06-01 Aron Kain Sensor commonality platform using multi-discipline adaptable sensors for customizable applications
US10522177B1 (en) 2018-07-31 2019-12-31 Seagate Technology Llc Disc locked clock-based servo timing
US11018842B1 (en) 2018-07-31 2021-05-25 Seagate Technology Llc Dynamic timing recovery bandwidth modulation for phase offset mitigation
US11016681B1 (en) 2018-07-31 2021-05-25 Seagate Technology Llc Multi-threshold parameter adaptation
US10803902B1 (en) 2018-08-19 2020-10-13 Seagate Technology Llc Hardware-based read sample averaging
US10460762B1 (en) * 2018-09-04 2019-10-29 Seagate Technology Llc Cancelling adjacent track interference signal with different data rate
US10468060B1 (en) 2018-09-27 2019-11-05 Seagate Technology Llc Cancelling adjacent track interference
CN110554838B (zh) * 2019-06-27 2020-08-14 中南大学 一种基于联合优化回声状态网络的热数据预测方法
JP7439474B2 (ja) * 2019-11-25 2024-02-28 富士電機株式会社 プログラマブルコントローラシステムおよびモジュール
US11366602B2 (en) 2020-06-23 2022-06-21 Western Digital Technologies, Inc. Data storage device with burn-after-read mode
CN113838484B (zh) * 2020-06-23 2023-03-31 株式会社东芝 磁盘装置以及读处理方法
US11495248B2 (en) * 2020-06-23 2022-11-08 Fujifilm Corporation Signal processing device, magnetic tape cartridge, magnetic tape reading apparatus, processing method of signal processing device, operation method of magnetic tape reading apparatus, and non-transitory computer-readable storage medium
US11595050B2 (en) * 2021-07-16 2023-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Circuits and methods for a cascade phase locked loop
US11456792B1 (en) * 2021-07-30 2022-09-27 Raytheon Company Intermodulation suppression in phased arrays using volterra filters
US11562767B1 (en) 2021-09-08 2023-01-24 Seagate Technology Llc Multi-sector read offset recovery
US11735220B2 (en) 2021-12-27 2023-08-22 Seagate Technology Llc Phase locking multiple clocks of different frequencies
US11694722B1 (en) 2022-02-15 2023-07-04 Western Digital Technologies, Inc. Data timestamp and read counter for magnetic recording devices
US20240022390A1 (en) * 2022-07-15 2024-01-18 Hughes Network Systems Method and Apparatus for Synchronizing Frequency in remote terminals
CN116055928B (zh) * 2023-04-03 2023-06-02 深圳市紫光同创电子有限公司 一种数据采样方法、装置、电子设备以及存储介质

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1695314A (zh) * 2002-11-15 2005-11-09 意大利电信股份公司 减小了定时抖动的早－迟同步器
CN103491036A (zh) * 2012-06-12 2014-01-01 马维尔国际贸易有限公司 用于无线基带处理的装置和方法

Family Cites Families (196)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2508491B2 (ja) 1987-09-28 1996-06-19 ソニー株式会社 デ―タ再生装置
JP2653933B2 (ja) 1991-04-30 1997-09-17 富士通株式会社 磁気ディスク装置のオフセット検出方式
US5862192A (en) 1991-12-31 1999-01-19 Lucent Technologies Inc. Methods and apparatus for equalization and decoding of digital communications channels using antenna diversity
US5621769A (en) 1992-06-08 1997-04-15 Novatel Communications Ltd. Adaptive-sequence-estimation apparatus employing diversity combining/selection
MY108838A (en) 1992-07-03 1996-11-30 Koninklijke Philips Electronics Nv Adaptive viterbi detector
KR960012019B1 (ko) 1993-11-18 1996-09-09 엘지전자 주식회사 에이치디티브이(hdtv)의 채널등화기
KR100300954B1 (ko) 1994-09-27 2001-10-22 윤종용 고정각속도방식의디스크재생장치의적응형등화기
US6665308B1 (en) 1995-08-25 2003-12-16 Terayon Communication Systems, Inc. Apparatus and method for equalization in distributed digital data transmission systems
US5970093A (en) 1996-01-23 1999-10-19 Tiernan Communications, Inc. Fractionally-spaced adaptively-equalized self-recovering digital receiver for amplitude-Phase modulated signals
US5742532A (en) 1996-05-09 1998-04-21 The Board Of Trustees Of The Leland Stanford Junior University System and method for generating fractional length delay lines in a digital signal processing system
US6633894B1 (en) 1997-05-08 2003-10-14 Legerity Inc. Signal processing arrangement including variable length adaptive filter and method therefor
US6377552B1 (en) 1997-08-29 2002-04-23 Motorola, Inc. System, device, and method for evaluating dynamic range in a communication system
WO1999019785A1 (en) 1997-10-10 1999-04-22 Rambus Incorporated Apparatus and method for generating a distributed clock signal using gear ratio techniques
US6222592B1 (en) 1998-01-13 2001-04-24 Samsung Electronics Co., Ltd. TV receiver equalizer storing channel characterizations for each TV channel between times of reception therefrom
US6111712A (en) 1998-03-06 2000-08-29 Cirrus Logic, Inc. Method to improve the jitter of high frequency phase locked loops used in read channels
US6157510A (en) 1998-03-10 2000-12-05 Maxtor Corporation Magnetic storage device with multiple read elements which are offset laterally and longitudinally
FI104772B (fi) 1998-03-23 2000-03-31 Nokia Networks Oy Itseoptimoiva kanavakorjaus- ja ilmaisumenetelmä ja itseoptimoiva kanavakorjain/ilmaisin
JP2000048488A (ja) 1998-07-27 2000-02-18 Pioneer Electron Corp クロストーク除去回路を有する記録情報再生装置
ID28538A (id) * 1998-08-14 2001-05-31 Qualcomm Inc Tata letak (arsitektur) memori untuk memetakan dekoder
JP3226499B2 (ja) 1998-09-25 2001-11-05 富士通株式会社 記憶ディスク装置のヘッド位置決め制御方法及びその装置
US6320920B1 (en) 1998-10-08 2001-11-20 Gregory Lee Beyke Phase coherence filter
US6597745B1 (en) * 1999-04-06 2003-07-22 Eric M. Dowling Reduced complexity multicarrier precoder
US6549587B1 (en) 1999-09-20 2003-04-15 Broadcom Corporation Voice and data exchange over a packet based network with timing recovery
US6181213B1 (en) 1999-06-14 2001-01-30 Realtek Semiconductor Corp. Phase-locked loop having a multi-phase voltage controlled oscillator
FR2796487B1 (fr) * 1999-06-28 2001-10-12 St Microelectronics Sa Procede et dispositif pour l'asservissement d'un faisceau optique incident sur une piste d'un support mobile d'informations, en particulier un disque numerique a vitesse de rotation elevee
US6519107B1 (en) 1999-09-24 2003-02-11 Maxtor Corporation Hard disk drive having self-written servo burst patterns
US6505222B1 (en) 1999-10-29 2003-01-07 International Business Machines Corporation Systems methods and computer program products for controlling undesirable bias in an equalizer
AU2280300A (en) 1999-11-27 2001-06-12 Deutsche Telekom Ag Method for co-channel interference cancelation in a multicarrier communication system
US6760371B1 (en) 2000-03-22 2004-07-06 The Boeing Company Method and apparatus implementation of a zero forcing equalizer
US7133239B1 (en) 2000-05-09 2006-11-07 Maxtor Corporation Methods and apparatuses for writing spiral servo patterns onto a disk surface
US6581182B1 (en) 2000-05-15 2003-06-17 Agere Systems Inc. Iterative decoding with post-processing of detected encoded data
US7245638B2 (en) * 2000-07-21 2007-07-17 Broadcom Corporation Methods and systems for DSP-based receivers
EP1233547A4 (en) 2000-08-30 2006-10-04 Matsushita Electric Ind Co Ltd DATA TRANSMISSION DEVICE, RADIO COMMUNICATIONS SYSTEM AND TECHNIQUE
US7133233B1 (en) 2000-10-24 2006-11-07 Maxtor Corporation Disk drive with read while write capability
US7046701B2 (en) 2000-11-03 2006-05-16 Qualcomm Inc. System, method, and apparatus for fractional delay
US7027497B2 (en) * 2000-12-19 2006-04-11 Ntt Docomo, Inc. Adaptive equalization method and adaptive equalizer
US6697891B2 (en) 2001-01-16 2004-02-24 Hitachi Global Storage Technologies Netherlands B.V. Parallel read/write circuit and method for efficient storing/retrieval of data to/from a recording medium
JP4487433B2 (ja) 2001-03-02 2010-06-23 ヤマハ株式会社 記録媒体記録装置
SG96277A1 (en) 2001-03-23 2003-05-23 Toshiba Kk Magnetic disk drive apparatus having a self-servo writing system and method for writing servo pattern therein
US6738205B1 (en) 2001-07-08 2004-05-18 Maxtor Corporation Self-writing of servo patterns in disk drives
US6670901B2 (en) 2001-07-31 2003-12-30 Motorola, Inc. Dynamic range on demand receiver and method of varying same
US6687073B1 (en) 2001-08-31 2004-02-03 Western Digital Technologies, Inc. Method of simultaneously writing servo tracks on a hard disk drive
US7440208B1 (en) 2001-09-21 2008-10-21 Maxtor Corporation Flexible partial response targets for data detectors
US6993291B2 (en) 2001-10-11 2006-01-31 Nokia Corporation Method and apparatus for continuously controlling the dynamic range from an analog-to-digital converter
US7085330B1 (en) 2002-02-15 2006-08-01 Marvell International Ltd. Method and apparatus for amplifier linearization using adaptive predistortion
TW591613B (en) 2002-03-26 2004-06-11 Via Tech Inc Method and related device for achieving stable writing state of compact disk driver by adjusting writing clock
JP3816050B2 (ja) 2002-04-23 2006-08-30 松下電器産業株式会社 信号処理装置
TWI287935B (en) * 2002-05-01 2007-10-01 Interdigital Tech Corp Point to multi-point services using high speed shared channels in wireless communication systems
TW200413907A (en) * 2002-08-29 2004-08-01 Motorola Inc Storage system with memory for storing data
US7180963B2 (en) 2002-11-25 2007-02-20 Ali Corporation Digital receiver capable of processing modulated signals at various data rates
US7324589B2 (en) * 2003-02-05 2008-01-29 Fujitsu Limited Method and system for providing error compensation to a signal using feedback control
US7830956B2 (en) * 2003-02-05 2010-11-09 Fujitsu Limited Method and system for processing a sampled signal
US7245448B2 (en) 2003-02-20 2007-07-17 Fujitsu Limited Information recording apparatus and data writing control device therefor
US7324561B1 (en) * 2003-06-13 2008-01-29 Silicon Clocks Inc. Systems and methods for generating an output oscillation signal with low jitter
JP2005135563A (ja) 2003-10-31 2005-05-26 Sanyo Electric Co Ltd 適応等化器
WO2005068971A1 (en) 2004-01-14 2005-07-28 Luminex Corporation Methods and systems for dynamic range expansion
CN1281003C (zh) * 2004-02-26 2006-10-18 上海交通大学 基于导频矩阵的时域自适应信道估计方法
US7184233B2 (en) 2004-06-04 2007-02-27 Quantum Corporation Dual source tracking servo systems and associated methods
US7333280B1 (en) * 2004-08-03 2008-02-19 Western Digital Technologies, Inc. Servo writing a disk drive by synchronizing a servo write clock to a reference pattern on the disk and compensating for repeatable phase error
US7271971B2 (en) * 2004-12-03 2007-09-18 International Business Machines Corporation Dynamically adapting a magnetic tape read channel equalizer
JP2006172586A (ja) 2004-12-15 2006-06-29 Hitachi Global Storage Technologies Netherlands Bv 磁気ディスク装置
EP1849236A1 (en) * 2004-12-29 2007-10-31 Intel Corporation Channel estimation and fixed thresholds for multi-threshold decoding of low-density parity check codes
US7333279B2 (en) 2005-03-22 2008-02-19 Seagate Technology Llc System and method for drive-side guarantee of quality of service and for extending the lifetime of storage devices
US7375562B2 (en) * 2005-03-25 2008-05-20 Faraday Technology Corp. Phase locked system for generating distributed clocks
US7256876B1 (en) * 2005-07-14 2007-08-14 At&T Corp. Estimating optical transmission system penalties induced by polarization mode dispersion (PMD)
US8160181B1 (en) 2005-10-24 2012-04-17 Marvell International Ltd. Nonlinear detectors for channels with signal-dependent noise
US7474487B2 (en) 2005-12-19 2009-01-06 Broadcom Corporation Read/write timing generator and methods for use therewith
US7529052B2 (en) 2005-12-19 2009-05-05 Broadcom Corporation Disk controller and methods for use therewith
US7813421B2 (en) * 2006-01-17 2010-10-12 Marvell World Trade Ltd. Order recursive computation for a MIMO equalizer
US7433142B2 (en) 2006-02-01 2008-10-07 International Business Machines Corporation Using at least one servo channel to provide timing recovery and timing information to data channels
US8335671B2 (en) * 2006-04-11 2012-12-18 Engl Heinz W Mathematical design of ion channel selectivity via inverse problem technology
CN1866945A (zh) * 2006-05-11 2006-11-22 上海交通大学 Ofdm***中基于可变遗忘因子的rls信道估计方法
US20080007855A1 (en) 2006-07-10 2008-01-10 Broadcom Corporation, A California Corporation Phase offset correction for timing recovery with use of ECC in a read channel for a disk drive
US8441751B1 (en) 2006-08-18 2013-05-14 Marvell International Ltd. Dibit pulse extraction methods and systems
US7940667B1 (en) 2006-09-13 2011-05-10 Pmc-Sierra Us, Inc. Delay measurements and calibration methods and apparatus for distributed wireless systems
KR100901787B1 (ko) 2006-12-15 2009-06-11 서강대학교기술지주 주식회사 후치필터링을 이용한 분수지연 필터 기반의 빔집속 장치 및 방법
US7715143B2 (en) 2006-12-31 2010-05-11 Broadcom Corporation Delta-sigma PLL using fractional divider from a multiphase ring oscillator
US7616685B2 (en) 2007-01-19 2009-11-10 Techwell, Inc. Method for channel tracking in an LMS adaptive equalizer for 8VSB
EP1976122A1 (en) * 2007-03-31 2008-10-01 Sony Deutschland Gmbh Adaptive filter device
US7787550B2 (en) 2007-07-24 2010-08-31 Texas Instruments Incorporated Combined frame alignment and timing recovery in digital subscriber line (DSL) communications systems
US7733592B2 (en) * 2007-10-11 2010-06-08 International Business Machines Corporation Methods for multi-channel data detection phase locked loop frequency error combination
JP2009134806A (ja) * 2007-11-30 2009-06-18 Fujitsu Ltd ヘッドｉｃ、リード回路及び媒体記憶装置
US7948703B1 (en) 2008-01-30 2011-05-24 Marvell International Ltd. Adaptive target optimization methods and systems for noise whitening based viterbi detectors
US8102938B2 (en) 2008-04-22 2012-01-24 Finisar Corporation Tuning system and method using a simulated bit error rate for use in an electronic dispersion compensator
US7929237B2 (en) 2008-06-27 2011-04-19 Agere Systems Inc. Modulated disk lock clock and methods for using such
US8027117B1 (en) 2008-08-25 2011-09-27 Marvell International Ltd. Zone servo writing using self servo writing
US8296637B1 (en) 2008-09-22 2012-10-23 Marvell International Ltd. Channel quality monitoring and method for qualifying a storage channel using an iterative decoder
US7929238B1 (en) 2008-10-14 2011-04-19 Western Digital Technologies, Inc. Disk drive seeking with a fixed rate clock when crossing servo zones to facilitate zoned servo sectors
CN101478510B (zh) * 2009-02-17 2013-06-19 上海高清数字科技产业有限公司 一种自适应均衡器及使用该均衡器的接收机***
US8040631B2 (en) 2009-05-18 2011-10-18 Seagate Technology Llc Servo processors that alternately control head positioning relative to sequential servo patterns
CN101577536B (zh) * 2009-06-17 2012-05-09 北京九方中实电子科技有限责任公司 一种改进的lms算法实现器
CN101932001B (zh) * 2009-06-24 2013-08-21 中兴通讯股份有限公司 一种自适应调制编码方法
JP2011014196A (ja) 2009-07-02 2011-01-20 Renesas Electronics Corp 適応等化器、情報再生装置、及び適応等化方法
US8139301B1 (en) * 2009-07-22 2012-03-20 Western Digital (Fremont), Llc Disk drive comprising a dual read element and delay circuitry to improve read signal
EP2442451A1 (en) * 2009-08-18 2012-04-18 TELEFONAKTIEBOLAGET LM ERICSSON (publ) Soft output Viterbi algorithm method and decoder
US8312359B2 (en) 2009-09-18 2012-11-13 Lsi Corporation Branch-metric calibration using varying bandwidth values
US8331050B1 (en) 2009-09-25 2012-12-11 Marvell International Ltd. Patterned magnetic media synchronization systems
TWI396089B (zh) * 2009-10-16 2013-05-11 Moxa Inc 以參數提供多通道傳輸串列資料之裝置及其方法
US20110090773A1 (en) 2009-10-16 2011-04-21 Chih-Ching Yu Apparatus for generating viterbi-processed data using an input signal obtained from reading an optical disc
US20110176400A1 (en) 2010-01-19 2011-07-21 Gerasimov Anton L Method of servo spiral switching during self servo-write for a disk drive
US8508879B1 (en) * 2010-01-21 2013-08-13 Marvell International Ltd. Write clock rephase for magnetic recording device
US8400726B1 (en) 2010-01-28 2013-03-19 Link—A—Media Devices Corporation Controlling preamble target amplitude
US8713413B1 (en) 2010-02-09 2014-04-29 Sk Hynix Memory Solutions Inc. Generation of interpolated samples for decision based decoding
EP2555195A4 (en) 2010-03-29 2014-05-21 Panasonic Corp OPTICAL DISC RECORDING DEVICE AND RECORDING SIGNAL PRODUCTION DEVICE
US8542766B2 (en) 2010-05-04 2013-09-24 Samsung Electronics Co., Ltd. Time alignment algorithm for transmitters with EER/ET amplifiers and others
JP4852166B1 (ja) * 2010-08-04 2012-01-11 シャープ株式会社 移動局装置、通信システム、通信方法および集積回路
US9362955B2 (en) * 2010-09-10 2016-06-07 Trellis Phase Communications, Lp Encoding and decoding using constrained interleaving
JP5582954B2 (ja) 2010-10-12 2014-09-03 ルネサスエレクトロニクス株式会社 デジタルｐｌｌ回路、情報再生装置、ディスク再生装置および信号処理方法
US8665543B2 (en) 2010-10-29 2014-03-04 Sk Hynix Memory Solutions Inc. Inter-track interference cancelation for shingled magnetic recording
US8842750B2 (en) 2010-12-21 2014-09-23 Intel Corporation Channel estimation for DVB-T2 demodulation using an adaptive prediction technique
US20120166953A1 (en) * 2010-12-23 2012-06-28 Microsoft Corporation Techniques for electronic aggregation of information
WO2012127637A1 (ja) 2011-03-22 2012-09-27 富士通株式会社 クロック生成回路及びクロック生成回路制御方法
CN103493376B (zh) 2011-04-20 2016-11-16 飞思卡尔半导体公司 用于时钟信号生成的***及方法
US8539328B2 (en) 2011-08-19 2013-09-17 Lsi Corporation Systems and methods for noise injection driven parameter selection
US8456230B2 (en) 2011-09-22 2013-06-04 Lsi Corporation Adaptive filter with coefficient determination based on output of real time clock
US8479086B2 (en) 2011-10-03 2013-07-02 Lsi Corporation Systems and methods for efficient parameter modification
JP2013149306A (ja) * 2012-01-18 2013-08-01 Toshiba Corp 信号処理回路、信号処理方法、及び磁気ディスク装置
US8923137B2 (en) 2012-02-06 2014-12-30 Qualcomm Incorporated System and method for information verification based on channel awareness
US9077349B2 (en) * 2012-02-21 2015-07-07 Qualcomm Incorporated Automatic detection and compensation of frequency offset in point-to-point communication
US8724245B1 (en) 2012-06-21 2014-05-13 Western Digital Technologies, Inc. Disk drive employing overlapping servo zones to facilitate servo zone crossing
US8780477B1 (en) 2012-06-21 2014-07-15 Western Digital Technologies, Inc. Disk drive adjusting servo timing to compensate for transient when crossing a servo zone boundary
SG196730A1 (en) * 2012-07-16 2014-02-13 Agency Science Tech & Res Methods for reading data from a storage medium using a reader and storage devices
US9239754B2 (en) * 2012-08-04 2016-01-19 Seagate Technology Llc Single read based soft-decision decoding of non-volatile memory
EP2712136B1 (en) * 2012-09-20 2015-02-25 Nxp B.V. Channel frequency response estimation and tracking for time- and frequency varying communication channels
US9385757B1 (en) 2012-09-27 2016-07-05 Marvell International Ltd. Systems and methods for using a non-binary soft output viterbi algorithm
CN102916916B (zh) * 2012-10-23 2015-04-22 华南理工大学 基于最小误码率准则的自适应信道均衡器及其实现方法
US9189379B2 (en) 2013-02-06 2015-11-17 Avago Technologies General Ip (Singapore) Pte. Ltd. Buffer for managing data samples in a read channel
US9246668B1 (en) * 2013-03-12 2016-01-26 Marvell International Ltd. Unified control for digital timing recovery and packet processing
US9093115B1 (en) 2013-03-15 2015-07-28 Seagate Technology Llc Track interference cancellation
WO2014186445A1 (en) * 2013-05-15 2014-11-20 Huawei Technologies Co., Ltd. Low complexity, adaptive, fractionally spaced equalizer with non-integer sampling
US8767341B1 (en) 2013-05-16 2014-07-01 HGST Netherlands B.V. Servo systems with augmented servo bursts
US8760794B1 (en) 2013-05-16 2014-06-24 HGST Netherlands B.V. Servo systems with augmented servo bursts
WO2014196046A1 (ja) * 2013-06-06 2014-12-11 パイオニア株式会社 伝送路推定装置、受信装置、伝送路推定方法、伝送路推定プログラム及び記録媒体
US9165597B2 (en) 2013-06-28 2015-10-20 Seagate Technology Llc Time-multiplexed single input single output (SISO) data recovery channel
WO2015009718A1 (en) * 2013-07-16 2015-01-22 Marvell World Trade Ltd. Systems and methods for calibrating read and write operations in two dimensional magnetic recording
US9129650B2 (en) * 2013-07-25 2015-09-08 Avago Technologies General Ip (Singapore) Pte. Ltd. Array-reader based magnetic recording systems with frequency division multiplexing
CN103476026B (zh) * 2013-09-06 2017-01-18 中国科学院软件研究所 基于卫星信道编码的自适应隐蔽通信方法
US9064537B1 (en) 2013-09-13 2015-06-23 Western Digital Technologies, Inc. Disk drive measuring radial offset between heads by detecting a difference between ramp contact
CN103560984B (zh) * 2013-10-31 2017-12-15 北京工业大学 基于多模型加权软切换的信道自适应估计方法
US9245578B1 (en) 2013-11-26 2016-01-26 Western Digital Technologies, Inc. Disk drive compensating for inter-track interference in analog read signal
US9257145B1 (en) * 2013-11-27 2016-02-09 Western Digital Technologies, Inc. Disk drive measuring down-track spacing of read sensors
JP2015122632A (ja) * 2013-12-24 2015-07-02 富士通株式会社 光通信受信装置
US9245579B2 (en) * 2013-12-27 2016-01-26 Avago Technologies General Ip (Singapore) Pte. Ltd. Two-dimensional magnetic recording reader offset estimation
US9025269B1 (en) 2014-01-02 2015-05-05 Western Digital Technologies, Inc. Disk drive compensating for cycle slip of disk locked clock when reading mini-wedge
US9645763B2 (en) 2014-01-13 2017-05-09 Seagate Technology Llc Framework for balancing robustness and latency during collection of statistics from soft reads
CN105745712A (zh) * 2014-01-20 2016-07-06 株式会社日立制作所 信息再生装置、信息再生方法、信息记录装置以及信息记录方法
CN103825852A (zh) * 2014-01-28 2014-05-28 华南理工大学 一种双模自适应判决反馈均衡模块及其实现方法
US9099132B1 (en) * 2014-02-25 2015-08-04 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for multi-head separation determination
US9280995B2 (en) 2014-03-28 2016-03-08 Avago Technologies General Ip (Singapore) Pte. Ltd. Locking a disk-locked clock using timestamps of successive servo address marks in a spiral servo track
US8861111B1 (en) * 2014-04-01 2014-10-14 Lsi Corporation Two dimensional magnetic recording servo system phase alignment
US9019642B1 (en) 2014-04-02 2015-04-28 Lsi Corporation Synchronization mark detection for multi-dimensional magnetic recording
US8837068B1 (en) * 2014-04-14 2014-09-16 Lsi Corporation Two dimensional magnetic recording servo system adaptive combination
US8861112B1 (en) * 2014-04-23 2014-10-14 Lsi Corporation Two dimensional magnetic recording system head separation estimator
US20150341158A1 (en) * 2014-05-23 2015-11-26 Mediatek Inc. Loop gain calibration apparatus for controlling loop gain of timing recovery loop and related loop gain calibration method
US8953276B1 (en) 2014-06-05 2015-02-10 Seagate Technology Llc Correcting position error based on reading first and second user data signals
US9417797B2 (en) 2014-06-09 2016-08-16 Seagate Technology Llc Estimating read reference voltage based on disparity and derivative metrics
US9431052B2 (en) * 2014-06-26 2016-08-30 Marvell World Trade Ltd. Two dimensional magnetic recording systems, devices and methods
US9196298B1 (en) * 2014-06-30 2015-11-24 Avago Technologies General Ip (Singapore) Pte. Ltd. Zero phase start for array reader magnetic recording system
CN104052691B (zh) * 2014-07-02 2017-02-15 东南大学 基于压缩感知的mimo‑ofdm***信道估计方法
US9117470B1 (en) 2014-07-17 2015-08-25 International Business Machines Corporation Write delay to de-skew data in read while write function for tape storage devices
US9245580B1 (en) * 2014-10-31 2016-01-26 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for three reader storage access
US9007707B1 (en) * 2014-10-31 2015-04-14 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for accessing codewords in parallel using a three sensor reader
US9680484B2 (en) * 2014-12-05 2017-06-13 Texas Instruments Incorporated Clock conditioner circuitry with improved holdover exit transient performance
US9690361B2 (en) * 2014-12-24 2017-06-27 Intel Corporation Low-power context-aware control for analog frontend
US9424878B1 (en) * 2015-02-04 2016-08-23 Avago Technologies General Ip (Singapore) Pte. Ltd. Two dimensional magnetic recording head separation calculator
US9401161B1 (en) 2015-03-11 2016-07-26 Seagate Technology Llc Magnetic read head with multiple read transducers each having different design characteristics
US9286915B1 (en) 2015-03-12 2016-03-15 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for format efficient sector fragment processing
US9508369B2 (en) 2015-03-13 2016-11-29 Seagate Technology Llc Defining a maximum sequential write duration for a data storage device utilizing heat-assisted recording
US9311959B1 (en) 2015-03-30 2016-04-12 Seagate Technology Llc Read channel optimization using multi-dimensional smoothing
US9489976B2 (en) 2015-04-06 2016-11-08 Seagate Technology Llc Noise prediction detector adaptation in transformed space
US9590803B2 (en) * 2015-05-22 2017-03-07 Seagate Technology Llc Timing error processor that uses the derivative of an interpolator function
CN106201333B (zh) 2015-06-01 2019-04-12 株式会社东芝 存储装置、控制器以及数据再读出方法
CN105050137B (zh) * 2015-06-18 2019-06-28 西安电子科技大学 一种基于信息物理***模型的车联网拥塞控制方法
US9564157B1 (en) 2015-08-21 2017-02-07 Seagate Technology Llc System and method for detecting reader-writer offset in a heat-assisted magnetic recording head
US10347343B2 (en) 2015-10-30 2019-07-09 Seagate Technology Llc Adaptive read threshold voltage tracking with separate characterization on each side of voltage distribution about distribution mean
US10192614B2 (en) 2015-10-30 2019-01-29 Seagate Technology Llc Adaptive read threshold voltage tracking with gap estimation between default read threshold voltages
US9542972B1 (en) 2015-11-12 2017-01-10 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for multi-head coefficient based scaling
US9837990B1 (en) 2015-12-11 2017-12-05 Syntropy Systems, Llc Digital signal processor
US10043582B2 (en) 2016-02-11 2018-08-07 Seagate Technology Llc Establishing parameters of subsequent read retry operations based on syndrome weights of prior failed decodings
US9536563B1 (en) 2016-02-16 2017-01-03 Seagate Technology Llc Detecting shingled overwrite errors
US10445171B2 (en) 2016-02-29 2019-10-15 Seagate Technology Llc On-the-fly error detection algorithm during retry procedure
CN105656819B (zh) * 2016-03-21 2018-12-18 电子科技大学 一种基于压缩感知和大规模mimo的自适应信道估计方法
CN105812299B (zh) * 2016-04-22 2020-05-15 中国地质大学（武汉） 基于联合块稀疏重构的无线传感网信道估计方法
US9947362B1 (en) 2016-06-25 2018-04-17 Seagate Technology Llc Asynchronous interference cancellation
US10180868B2 (en) 2016-07-08 2019-01-15 Seagate Technology Llc Adaptive read threshold voltage tracking with bit error rate estimation based on non-linear syndrome weight mapping
US10290358B2 (en) 2016-07-08 2019-05-14 Seagate Technology Llc Independent read threshold voltage tracking for multiple dependent read threshold voltages using syndrome weights
US9819456B1 (en) 2016-10-17 2017-11-14 Seagate Technology Llc Preamble detection and frequency offset determination
US10164760B1 (en) * 2016-10-18 2018-12-25 Seagate Technology Llc Timing excursion recovery
US10152457B1 (en) 2016-10-25 2018-12-11 Seagate Technology Llc Target parameter adaptation
US9998136B1 (en) * 2017-02-17 2018-06-12 Seagate Technology Llc Loop consistency using multiple channel estimates
JP2018160302A (ja) 2017-03-23 2018-10-11 株式会社東芝 ストレージ装置及びコントローラ
US10014026B1 (en) * 2017-06-20 2018-07-03 Seagate Technology Llc Head delay calibration and tracking in MSMR systems
US10388368B2 (en) 2017-10-31 2019-08-20 Seagate Technology Llc Adaptive read threshold voltage tracking with charge leakage mitigation using charge leakage settling time
US10276233B1 (en) 2017-10-31 2019-04-30 Seagate Technology Llc Adaptive read threshold voltage tracking with charge leakage mitigation using threshold voltage offsets
US10297281B1 (en) 2017-11-06 2019-05-21 Seagate Technology Llc Servo sector detection
US10498565B1 (en) 2018-09-05 2019-12-03 Macom Technology Solutions Holding, Inc Sampling phase optimization for digital modulated signals

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1695314A (zh) * 2002-11-15 2005-11-09 意大利电信股份公司 减小了定时抖动的早－迟同步器
CN103491036A (zh) * 2012-06-12 2014-01-01 马维尔国际贸易有限公司 用于无线基带处理的装置和方法

Also Published As

Publication number Publication date
US10469290B1 (en) 2019-11-05
US20180366156A1 (en) 2018-12-20
US20180366155A1 (en) 2018-12-20
US20180366149A1 (en) 2018-12-20
US10714134B2 (en) 2020-07-14
TW201907293A (zh) 2019-02-16
US10936003B1 (en) 2021-03-02
US10755734B2 (en) 2020-08-25
TWI701591B (zh) 2020-08-11
US10607648B1 (en) 2020-03-31
US10157637B1 (en) 2018-12-18
US10276197B2 (en) 2019-04-30
CN109104200A (zh) 2018-12-28
TW201907260A (zh) 2019-02-16
US10177771B1 (en) 2019-01-08
US10014026B1 (en) 2018-07-03
SG10201805246XA (en) 2019-01-30
CN109104388A (zh) 2018-12-28
US20200005819A1 (en) 2020-01-02
US10410672B1 (en) 2019-09-10
US11361788B2 (en) 2022-06-14
TW201905682A (zh) 2019-02-01
SG10201805247VA (en) 2019-01-30
TWI691899B (zh) 2020-04-21
US10068608B1 (en) 2018-09-04
SG10201804852XA (en) 2019-01-30
US20180367164A1 (en) 2018-12-20
CN109104204A (zh) 2018-12-28
US20200065262A1 (en) 2020-02-27
CN109104200B (zh) 2022-07-01
CN109104388B (zh) 2021-06-11
US10665256B2 (en) 2020-05-26
US10496559B1 (en) 2019-12-03

Similar Documents

Publication Publication Date Title
CN109104204B (zh) 用于混合定时恢复的装置、***和方法
US7808408B2 (en) Minimizing adverse effects of skew between two analog-to-digital converters
JP2008011189A (ja) タイム・インターリーブａ／ｄ変換装置
US9893877B2 (en) Circuits, systems, and methods for synchronization of sampling and sample rate setting
JP2011030204A (ja) データ処理回路での２ティア・サンプリング補正のシステムおよび方法
US7439885B2 (en) Method and system for sample rate conversion
US20100177615A1 (en) Maximum likelihood decoder and information reproduction apparatus
US11636903B2 (en) Semiconductor circuit, receiving device, and memory system
US10097200B1 (en) Resynchronization of sample rate converters
US9083354B2 (en) Clock signal timing-based noise suppression
US9356767B1 (en) Hybrid analog/digital clock recovery system
US7375558B2 (en) Method and apparatus for pre-clocking
US9418698B2 (en) Dynamic gain control for use with adaptive equalizers
US8594254B2 (en) Waveform interpolator architecture for accurate timing recovery based on up-sampling technique
US10298240B1 (en) Wide frequency range clock generation with phase interpolation
JP4972907B2 (ja) ドットクロック再生回路
US8970268B2 (en) Semiconductor apparatus
EP2608409B1 (en) Multichannel sample rate converter
JP2007019848A (ja) 信号処理装置、信号処理方法
US20080152055A1 (en) System and method of signal processing
JP2016039423A (ja) クロック信号分配回路、クロック信号分配方法、及びクロック信号分配プログラム
US9053742B1 (en) Repeated runout (RRO) zero phase start (ZPS)
CN114598311A (zh) 用于比较功能安全***中的冗余信号的装置和方法
US9111573B1 (en) Detection of end of preamble in read channel without interpolation
JP2005222649A (ja) Ｐｌｌ回路及びｐｌｌ回路を有する光ディスク再生装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant