SG10201805247VA - Hybrid timing recovery - Google Patents

Hybrid timing recovery

Info

Publication number
SG10201805247VA
SG10201805247VA SG10201805247VA SG10201805247VA SG10201805247VA SG 10201805247V A SG10201805247V A SG 10201805247VA SG 10201805247V A SG10201805247V A SG 10201805247VA SG 10201805247V A SG10201805247V A SG 10201805247VA SG 10201805247V A SG10201805247V A SG 10201805247VA
Authority
SG
Singapore
Prior art keywords
phase
value
digital
interpolator
signal
Prior art date
Application number
SG10201805247VA
Inventor
Bellorado Jason
Marrow Marcus
Wu Zheng
Original Assignee
Seagate Technology Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seagate Technology Llc filed Critical Seagate Technology Llc
Publication of SG10201805247VA publication Critical patent/SG10201805247VA/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/3707—Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
    • G11B5/48—Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed
    • G11B5/58—Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed with provision for moving the head for the purpose of maintaining alignment of the head relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track following
    • G11B5/596—Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed with provision for moving the head for the purpose of maintaining alignment of the head relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track following for track following on disks
    • G11B5/59633—Servo formatting
    • G11B5/59666—Self servo writing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03878—Line equalisers; line build-out devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/102—Program control for peripheral devices where the programme performs an interfacing function, e.g. device driver
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10037—A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10046—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter
    • G11B20/10055—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter using partial response filtering when writing the signal to the medium or reading it therefrom
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10222—Improvement or modification of read or write signals clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10222—Improvement or modification of read or write signals clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation
    • G11B20/1024—Improvement or modification of read or write signals clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation wherein a phase-locked loop [PLL] is used
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
    • G11B5/48—Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed
    • G11B5/58—Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed with provision for moving the head for the purpose of maintaining alignment of the head relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track following
    • G11B5/596—Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed with provision for moving the head for the purpose of maintaining alignment of the head relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track following for track following on disks
    • G11B5/59633—Servo formatting
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/001—Analogue/digital/analogue conversion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4138—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors soft-output Viterbi algorithm based decoding, i.e. Viterbi decoding with weighted decisions
    • H03M13/4146—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors soft-output Viterbi algorithm based decoding, i.e. Viterbi decoding with weighted decisions soft-output Viterbi decoding according to Battail and Hagenauer in which the soft-output is determined using path metric differences along the maximum-likelihood path, i.e. "SOVA" decoding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used
    • H04J3/0617—Systems characterised by the synchronising information used the synchronising signal being characterised by the frequency or phase
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers without distortion of the input signal
    • H03G3/20—Automatic control
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2948—Iterative decoding
    • H03M13/2951—Iterative decoding using iteration stopping criteria
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7097—Interference-related aspects
    • H04B1/7103—Interference-related aspects the interference being multiple access interference
    • H04B1/7105—Joint detection techniques, e.g. linear detectors
    • H04B1/71055—Joint detection techniques, e.g. linear detectors using minimum mean squared error [MMSE] detector
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
    • H04L7/0025—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of clock signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
    • H04L7/0029—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of received data signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Abstract

OF THE DISCLOSURE An apparatus may include a circuit configured to receive a first phase control value of a phase control value signal, generate a first phase interpolator control signal value of a phase interpolator control signal and generate a first digital interpolator control signal value of a digital interpolator control signal. The apparatus may further be configured to phase interpolate a clock signal based on the first phase interpolator control signal value to produce a phase shifted clock signal and digitally interpolate a digital sample based on the first digital interpolator signal value to produce a phase shifted digital sample having an effective phase based on the first phase control value, the digital sample generated using the phase shifted clock signal as a sample clock. Figure 1
SG10201805247VA 2017-06-20 2018-06-19 Hybrid timing recovery SG10201805247VA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201762522248P 2017-06-20 2017-06-20
US15/791,190 US10665256B2 (en) 2017-06-20 2017-10-23 Hybrid timing recovery

Publications (1)

Publication Number Publication Date
SG10201805247VA true SG10201805247VA (en) 2019-01-30

Family

ID=62683652

Family Applications (3)

Application Number Title Priority Date Filing Date
SG10201804852XA SG10201804852XA (en) 2017-06-20 2018-06-07 Regularized parameter adaptation
SG10201805246XA SG10201805246XA (en) 2017-06-20 2018-06-19 Approximated parameter adaptation
SG10201805247VA SG10201805247VA (en) 2017-06-20 2018-06-19 Hybrid timing recovery

Family Applications Before (2)

Application Number Title Priority Date Filing Date
SG10201804852XA SG10201804852XA (en) 2017-06-20 2018-06-07 Regularized parameter adaptation
SG10201805246XA SG10201805246XA (en) 2017-06-20 2018-06-19 Approximated parameter adaptation

Country Status (4)

Country Link
US (14) US10014026B1 (en)
CN (3) CN109104388B (en)
SG (3) SG10201804852XA (en)
TW (3) TWI701591B (en)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8595191B2 (en) 2009-12-31 2013-11-26 Commvault Systems, Inc. Systems and methods for performing data management operations using snapshots
US10152457B1 (en) 2016-10-25 2018-12-11 Seagate Technology Llc Target parameter adaptation
US10382166B1 (en) * 2017-02-22 2019-08-13 Seagate Technology Llc Constrained receiver parameter optimization
US10014026B1 (en) 2017-06-20 2018-07-03 Seagate Technology Llc Head delay calibration and tracking in MSMR systems
GB2566759B8 (en) 2017-10-20 2021-12-08 Please Hold Uk Ltd Encoding identifiers to produce audio identifiers from a plurality of audio bitstreams
GB2566760B (en) * 2017-10-20 2019-10-23 Please Hold Uk Ltd Audio Signal
JP6813474B2 (en) * 2017-12-26 2021-01-13 株式会社東芝 Magnetic disk drive and read / write offset correction method
US11022511B2 (en) 2018-04-18 2021-06-01 Aron Kain Sensor commonality platform using multi-discipline adaptable sensors for customizable applications
US10522177B1 (en) 2018-07-31 2019-12-31 Seagate Technology Llc Disc locked clock-based servo timing
US11018842B1 (en) 2018-07-31 2021-05-25 Seagate Technology Llc Dynamic timing recovery bandwidth modulation for phase offset mitigation
US11016681B1 (en) 2018-07-31 2021-05-25 Seagate Technology Llc Multi-threshold parameter adaptation
US10803902B1 (en) 2018-08-19 2020-10-13 Seagate Technology Llc Hardware-based read sample averaging
US10460762B1 (en) * 2018-09-04 2019-10-29 Seagate Technology Llc Cancelling adjacent track interference signal with different data rate
US10468060B1 (en) 2018-09-27 2019-11-05 Seagate Technology Llc Cancelling adjacent track interference
CN110554838B (en) * 2019-06-27 2020-08-14 中南大学 Thermal data prediction method based on joint optimization echo state network
JP7439474B2 (en) * 2019-11-25 2024-02-28 富士電機株式会社 Programmable controller systems and modules
JP2022003598A (en) * 2020-06-23 2022-01-11 株式会社東芝 Magnetic disk device and read processing method
US11366602B2 (en) 2020-06-23 2022-06-21 Western Digital Technologies, Inc. Data storage device with burn-after-read mode
US11495248B2 (en) * 2020-06-23 2022-11-08 Fujifilm Corporation Signal processing device, magnetic tape cartridge, magnetic tape reading apparatus, processing method of signal processing device, operation method of magnetic tape reading apparatus, and non-transitory computer-readable storage medium
US11595050B2 (en) * 2021-07-16 2023-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Circuits and methods for a cascade phase locked loop
US11456792B1 (en) * 2021-07-30 2022-09-27 Raytheon Company Intermodulation suppression in phased arrays using volterra filters
US11562767B1 (en) 2021-09-08 2023-01-24 Seagate Technology Llc Multi-sector read offset recovery
US11735220B2 (en) 2021-12-27 2023-08-22 Seagate Technology Llc Phase locking multiple clocks of different frequencies
US11694722B1 (en) 2022-02-15 2023-07-04 Western Digital Technologies, Inc. Data timestamp and read counter for magnetic recording devices
US20240022390A1 (en) * 2022-07-15 2024-01-18 Hughes Network Systems Method and Apparatus for Synchronizing Frequency in remote terminals
CN116055928B (en) * 2023-04-03 2023-06-02 深圳市紫光同创电子有限公司 Data sampling method, device, electronic equipment and storage medium

Family Cites Families (198)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2508491B2 (en) 1987-09-28 1996-06-19 ソニー株式会社 Data playback device
JP2653933B2 (en) 1991-04-30 1997-09-17 富士通株式会社 Offset detection method for magnetic disk drives
US5862192A (en) 1991-12-31 1999-01-19 Lucent Technologies Inc. Methods and apparatus for equalization and decoding of digital communications channels using antenna diversity
US5621769A (en) 1992-06-08 1997-04-15 Novatel Communications Ltd. Adaptive-sequence-estimation apparatus employing diversity combining/selection
MY108838A (en) 1992-07-03 1996-11-30 Koninklijke Philips Electronics Nv Adaptive viterbi detector
KR960012019B1 (en) 1993-11-18 1996-09-09 엘지전자 주식회사 Hdtv channel equipment
KR100300954B1 (en) 1994-09-27 2001-10-22 윤종용 Adaptive equalizer of fixed angular velocity type disc reproducing device
US6665308B1 (en) 1995-08-25 2003-12-16 Terayon Communication Systems, Inc. Apparatus and method for equalization in distributed digital data transmission systems
US5970093A (en) 1996-01-23 1999-10-19 Tiernan Communications, Inc. Fractionally-spaced adaptively-equalized self-recovering digital receiver for amplitude-Phase modulated signals
US5742532A (en) 1996-05-09 1998-04-21 The Board Of Trustees Of The Leland Stanford Junior University System and method for generating fractional length delay lines in a digital signal processing system
US6633894B1 (en) 1997-05-08 2003-10-14 Legerity Inc. Signal processing arrangement including variable length adaptive filter and method therefor
US6377552B1 (en) 1997-08-29 2002-04-23 Motorola, Inc. System, device, and method for evaluating dynamic range in a communication system
WO1999019785A1 (en) 1997-10-10 1999-04-22 Rambus Incorporated Apparatus and method for generating a distributed clock signal using gear ratio techniques
US6222592B1 (en) 1998-01-13 2001-04-24 Samsung Electronics Co., Ltd. TV receiver equalizer storing channel characterizations for each TV channel between times of reception therefrom
US6111712A (en) 1998-03-06 2000-08-29 Cirrus Logic, Inc. Method to improve the jitter of high frequency phase locked loops used in read channels
US6157510A (en) 1998-03-10 2000-12-05 Maxtor Corporation Magnetic storage device with multiple read elements which are offset laterally and longitudinally
FI104772B (en) 1998-03-23 2000-03-31 Nokia Networks Oy Self-optimizing channel correction and detection method and self-optimizing channel correction / detection
JP2000048488A (en) 1998-07-27 2000-02-18 Pioneer Electron Corp Recording information reproducing device having cross talk removal circuit
ID28538A (en) * 1998-08-14 2001-05-31 Qualcomm Inc MEMORY LAYOUT (ARCHITECTURE) FOR MAPPING DECODERS
JP3226499B2 (en) 1998-09-25 2001-11-05 富士通株式会社 HEAD POSITIONING CONTROL METHOD AND DEVICE FOR STORAGE DISK DEVICE
US6320920B1 (en) 1998-10-08 2001-11-20 Gregory Lee Beyke Phase coherence filter
US6597745B1 (en) * 1999-04-06 2003-07-22 Eric M. Dowling Reduced complexity multicarrier precoder
US6549587B1 (en) 1999-09-20 2003-04-15 Broadcom Corporation Voice and data exchange over a packet based network with timing recovery
US6181213B1 (en) 1999-06-14 2001-01-30 Realtek Semiconductor Corp. Phase-locked loop having a multi-phase voltage controlled oscillator
FR2796487B1 (en) * 1999-06-28 2001-10-12 St Microelectronics Sa METHOD AND DEVICE FOR SERVOING AN INCIDENT OPTICAL BEAM ON A TRACK OF A MOBILE INFORMATION MEDIA, IN PARTICULAR A DIGITAL DISC WITH A HIGH SPEED OF ROTATION
US6519107B1 (en) 1999-09-24 2003-02-11 Maxtor Corporation Hard disk drive having self-written servo burst patterns
US6505222B1 (en) 1999-10-29 2003-01-07 International Business Machines Corporation Systems methods and computer program products for controlling undesirable bias in an equalizer
WO2001041387A1 (en) 1999-11-27 2001-06-07 Deutsche Telekom Ag Method for co-channel interference cancelation in a multicarrier communication system
US6760371B1 (en) 2000-03-22 2004-07-06 The Boeing Company Method and apparatus implementation of a zero forcing equalizer
US7133239B1 (en) 2000-05-09 2006-11-07 Maxtor Corporation Methods and apparatuses for writing spiral servo patterns onto a disk surface
US6581182B1 (en) 2000-05-15 2003-06-17 Agere Systems Inc. Iterative decoding with post-processing of detected encoded data
US7245638B2 (en) * 2000-07-21 2007-07-17 Broadcom Corporation Methods and systems for DSP-based receivers
CN1913395A (en) 2000-08-30 2007-02-14 松下电器产业株式会社 Data transmitting device, and system and method for radio communication
US7133233B1 (en) 2000-10-24 2006-11-07 Maxtor Corporation Disk drive with read while write capability
US7046701B2 (en) 2000-11-03 2006-05-16 Qualcomm Inc. System, method, and apparatus for fractional delay
US7027497B2 (en) * 2000-12-19 2006-04-11 Ntt Docomo, Inc. Adaptive equalization method and adaptive equalizer
US6697891B2 (en) 2001-01-16 2004-02-24 Hitachi Global Storage Technologies Netherlands B.V. Parallel read/write circuit and method for efficient storing/retrieval of data to/from a recording medium
JP4487433B2 (en) 2001-03-02 2010-06-23 ヤマハ株式会社 Recording medium recording device
SG96277A1 (en) 2001-03-23 2003-05-23 Toshiba Kk Magnetic disk drive apparatus having a self-servo writing system and method for writing servo pattern therein
US6738205B1 (en) 2001-07-08 2004-05-18 Maxtor Corporation Self-writing of servo patterns in disk drives
US6670901B2 (en) 2001-07-31 2003-12-30 Motorola, Inc. Dynamic range on demand receiver and method of varying same
US6687073B1 (en) 2001-08-31 2004-02-03 Western Digital Technologies, Inc. Method of simultaneously writing servo tracks on a hard disk drive
US7440208B1 (en) 2001-09-21 2008-10-21 Maxtor Corporation Flexible partial response targets for data detectors
US6993291B2 (en) 2001-10-11 2006-01-31 Nokia Corporation Method and apparatus for continuously controlling the dynamic range from an analog-to-digital converter
US7085330B1 (en) 2002-02-15 2006-08-01 Marvell International Ltd. Method and apparatus for amplifier linearization using adaptive predistortion
TW591613B (en) 2002-03-26 2004-06-11 Via Tech Inc Method and related device for achieving stable writing state of compact disk driver by adjusting writing clock
JP3816050B2 (en) 2002-04-23 2006-08-30 松下電器産業株式会社 Signal processing device
TWI469561B (en) * 2002-05-01 2015-01-11 Interdigital Tech Corp Point to multi-point services using high speed shared channels in wireless communication systems
TW200413907A (en) * 2002-08-29 2004-08-01 Motorola Inc Storage system with memory for storing data
EP1561287B1 (en) * 2002-11-15 2009-03-25 Telecom Italia S.p.A. Early-late synchronizer having reduced timing jitter
US7180963B2 (en) 2002-11-25 2007-02-20 Ali Corporation Digital receiver capable of processing modulated signals at various data rates
US7830956B2 (en) * 2003-02-05 2010-11-09 Fujitsu Limited Method and system for processing a sampled signal
US7324589B2 (en) * 2003-02-05 2008-01-29 Fujitsu Limited Method and system for providing error compensation to a signal using feedback control
US7245448B2 (en) 2003-02-20 2007-07-17 Fujitsu Limited Information recording apparatus and data writing control device therefor
US7324561B1 (en) * 2003-06-13 2008-01-29 Silicon Clocks Inc. Systems and methods for generating an output oscillation signal with low jitter
JP2005135563A (en) 2003-10-31 2005-05-26 Sanyo Electric Co Ltd Adaptive equalizer
EP1704402B1 (en) 2004-01-14 2016-05-11 Luminex Corporation Methods and systems for dynamic range expansion
CN1281003C (en) * 2004-02-26 2006-10-18 上海交通大学 Time-domain adaptive channel estimating method based on pilot matrix
US7184233B2 (en) 2004-06-04 2007-02-27 Quantum Corporation Dual source tracking servo systems and associated methods
US7333280B1 (en) * 2004-08-03 2008-02-19 Western Digital Technologies, Inc. Servo writing a disk drive by synchronizing a servo write clock to a reference pattern on the disk and compensating for repeatable phase error
US7271971B2 (en) * 2004-12-03 2007-09-18 International Business Machines Corporation Dynamically adapting a magnetic tape read channel equalizer
JP2006172586A (en) 2004-12-15 2006-06-29 Hitachi Global Storage Technologies Netherlands Bv Magnetic disk device
US8015468B2 (en) * 2004-12-29 2011-09-06 Intel Corporation Channel estimation and fixed thresholds for multi-threshold decoding of low-density parity check codes
US7333279B2 (en) 2005-03-22 2008-02-19 Seagate Technology Llc System and method for drive-side guarantee of quality of service and for extending the lifetime of storage devices
US7375562B2 (en) * 2005-03-25 2008-05-20 Faraday Technology Corp. Phase locked system for generating distributed clocks
US7256876B1 (en) * 2005-07-14 2007-08-14 At&T Corp. Estimating optical transmission system penalties induced by polarization mode dispersion (PMD)
US8160181B1 (en) 2005-10-24 2012-04-17 Marvell International Ltd. Nonlinear detectors for channels with signal-dependent noise
US7474487B2 (en) 2005-12-19 2009-01-06 Broadcom Corporation Read/write timing generator and methods for use therewith
US7529052B2 (en) 2005-12-19 2009-05-05 Broadcom Corporation Disk controller and methods for use therewith
US7813421B2 (en) * 2006-01-17 2010-10-12 Marvell World Trade Ltd. Order recursive computation for a MIMO equalizer
US7433142B2 (en) 2006-02-01 2008-10-07 International Business Machines Corporation Using at least one servo channel to provide timing recovery and timing information to data channels
WO2007120728A2 (en) * 2006-04-11 2007-10-25 Mathconsult Gmbh Mathematical design of ion channel selectivity via inverse problems technology
CN1866945A (en) * 2006-05-11 2006-11-22 上海交通大学 RLS channel estimating method based on variable forgetting factor in OFDM system
US20080007855A1 (en) 2006-07-10 2008-01-10 Broadcom Corporation, A California Corporation Phase offset correction for timing recovery with use of ECC in a read channel for a disk drive
US8441751B1 (en) 2006-08-18 2013-05-14 Marvell International Ltd. Dibit pulse extraction methods and systems
US7940667B1 (en) 2006-09-13 2011-05-10 Pmc-Sierra Us, Inc. Delay measurements and calibration methods and apparatus for distributed wireless systems
KR100901787B1 (en) 2006-12-15 2009-06-11 서강대학교기술지주 주식회사 Fractional delay filter-based beamformer apparatus using post filtering
US7715143B2 (en) 2006-12-31 2010-05-11 Broadcom Corporation Delta-sigma PLL using fractional divider from a multiphase ring oscillator
US7616685B2 (en) 2007-01-19 2009-11-10 Techwell, Inc. Method for channel tracking in an LMS adaptive equalizer for 8VSB
EP1976122A1 (en) * 2007-03-31 2008-10-01 Sony Deutschland Gmbh Adaptive filter device
US7787550B2 (en) 2007-07-24 2010-08-31 Texas Instruments Incorporated Combined frame alignment and timing recovery in digital subscriber line (DSL) communications systems
US7733592B2 (en) * 2007-10-11 2010-06-08 International Business Machines Corporation Methods for multi-channel data detection phase locked loop frequency error combination
JP2009134806A (en) * 2007-11-30 2009-06-18 Fujitsu Ltd Head ic, read circuit, and medium storage device
US7948703B1 (en) 2008-01-30 2011-05-24 Marvell International Ltd. Adaptive target optimization methods and systems for noise whitening based viterbi detectors
US8102938B2 (en) 2008-04-22 2012-01-24 Finisar Corporation Tuning system and method using a simulated bit error rate for use in an electronic dispersion compensator
US7929237B2 (en) 2008-06-27 2011-04-19 Agere Systems Inc. Modulated disk lock clock and methods for using such
US8027117B1 (en) 2008-08-25 2011-09-27 Marvell International Ltd. Zone servo writing using self servo writing
US8296637B1 (en) 2008-09-22 2012-10-23 Marvell International Ltd. Channel quality monitoring and method for qualifying a storage channel using an iterative decoder
US7929238B1 (en) 2008-10-14 2011-04-19 Western Digital Technologies, Inc. Disk drive seeking with a fixed rate clock when crossing servo zones to facilitate zoned servo sectors
CN101478510B (en) * 2009-02-17 2013-06-19 上海高清数字科技产业有限公司 Adaptive equalizer and receiver system using the equalizer
US8040631B2 (en) 2009-05-18 2011-10-18 Seagate Technology Llc Servo processors that alternately control head positioning relative to sequential servo patterns
CN101577536B (en) * 2009-06-17 2012-05-09 北京九方中实电子科技有限责任公司 Method for realizing improved LMS algorithm
CN101932001B (en) * 2009-06-24 2013-08-21 中兴通讯股份有限公司 Adaptive modulation coding method
JP2011014196A (en) 2009-07-02 2011-01-20 Renesas Electronics Corp Adaptive equalizer, information reproduction device, and adaptive equalization method
US8139301B1 (en) * 2009-07-22 2012-03-20 Western Digital (Fremont), Llc Disk drive comprising a dual read element and delay circuitry to improve read signal
EP2302811B1 (en) * 2009-08-18 2013-03-27 Telefonaktiebolaget L M Ericsson (Publ) Soft output viterbi algorithm method and decoder
US8312359B2 (en) 2009-09-18 2012-11-13 Lsi Corporation Branch-metric calibration using varying bandwidth values
US8331050B1 (en) 2009-09-25 2012-12-11 Marvell International Ltd. Patterned magnetic media synchronization systems
TWI396089B (en) * 2009-10-16 2013-05-11 Moxa Inc System for using multi-channels to transmit serial data according to arguments and method thereof
US20110090773A1 (en) 2009-10-16 2011-04-21 Chih-Ching Yu Apparatus for generating viterbi-processed data using an input signal obtained from reading an optical disc
US20110176400A1 (en) 2010-01-19 2011-07-21 Gerasimov Anton L Method of servo spiral switching during self servo-write for a disk drive
US8508879B1 (en) * 2010-01-21 2013-08-13 Marvell International Ltd. Write clock rephase for magnetic recording device
US8400726B1 (en) 2010-01-28 2013-03-19 Link—A—Media Devices Corporation Controlling preamble target amplitude
US8713413B1 (en) 2010-02-09 2014-04-29 Sk Hynix Memory Solutions Inc. Generation of interpolated samples for decision based decoding
EP2555195A4 (en) 2010-03-29 2014-05-21 Panasonic Corp Optical disc recording device and recording signal generation device
US8542766B2 (en) 2010-05-04 2013-09-24 Samsung Electronics Co., Ltd. Time alignment algorithm for transmitters with EER/ET amplifiers and others
JP4852166B1 (en) * 2010-08-04 2012-01-11 シャープ株式会社 Mobile station apparatus, communication system, communication method, and integrated circuit
US9362955B2 (en) * 2010-09-10 2016-06-07 Trellis Phase Communications, Lp Encoding and decoding using constrained interleaving
JP5582954B2 (en) 2010-10-12 2014-09-03 ルネサスエレクトロニクス株式会社 DIGITAL PLL CIRCUIT, INFORMATION REPRODUCING DEVICE, DISC REPRODUCING DEVICE, AND SIGNAL PROCESSING METHOD
US8665543B2 (en) 2010-10-29 2014-03-04 Sk Hynix Memory Solutions Inc. Inter-track interference cancelation for shingled magnetic recording
US8842750B2 (en) 2010-12-21 2014-09-23 Intel Corporation Channel estimation for DVB-T2 demodulation using an adaptive prediction technique
US20120166953A1 (en) * 2010-12-23 2012-06-28 Microsoft Corporation Techniques for electronic aggregation of information
JPWO2012127637A1 (en) 2011-03-22 2014-07-24 富士通株式会社 Clock generation circuit and clock generation circuit control method
EP2700171B1 (en) 2011-04-20 2018-04-04 NXP USA, Inc. System and method for clock signal generation
US8539328B2 (en) 2011-08-19 2013-09-17 Lsi Corporation Systems and methods for noise injection driven parameter selection
US8456230B2 (en) 2011-09-22 2013-06-04 Lsi Corporation Adaptive filter with coefficient determination based on output of real time clock
US8479086B2 (en) 2011-10-03 2013-07-02 Lsi Corporation Systems and methods for efficient parameter modification
JP2013149306A (en) * 2012-01-18 2013-08-01 Toshiba Corp Signal processing circuit, signal processing method, and magnetic disk drive
US8923137B2 (en) 2012-02-06 2014-12-30 Qualcomm Incorporated System and method for information verification based on channel awareness
US9077349B2 (en) * 2012-02-21 2015-07-07 Qualcomm Incorporated Automatic detection and compensation of frequency offset in point-to-point communication
US9357517B2 (en) * 2012-06-12 2016-05-31 Marvell World Trade Ltd. Apparatus and method for wireless baseband processing
US8780477B1 (en) 2012-06-21 2014-07-15 Western Digital Technologies, Inc. Disk drive adjusting servo timing to compensate for transient when crossing a servo zone boundary
US8724245B1 (en) 2012-06-21 2014-05-13 Western Digital Technologies, Inc. Disk drive employing overlapping servo zones to facilitate servo zone crossing
US9082418B2 (en) * 2012-07-16 2015-07-14 Marvell International Ltd. Methods for reading data from a storage medium using a reader and storage devices
US9239754B2 (en) * 2012-08-04 2016-01-19 Seagate Technology Llc Single read based soft-decision decoding of non-volatile memory
EP2712136B1 (en) * 2012-09-20 2015-02-25 Nxp B.V. Channel frequency response estimation and tracking for time- and frequency varying communication channels
US9385757B1 (en) 2012-09-27 2016-07-05 Marvell International Ltd. Systems and methods for using a non-binary soft output viterbi algorithm
CN102916916B (en) * 2012-10-23 2015-04-22 华南理工大学 Minimum bit error rate principle based adaptive channel balancer and implementation method thereof
US9189379B2 (en) 2013-02-06 2015-11-17 Avago Technologies General Ip (Singapore) Pte. Ltd. Buffer for managing data samples in a read channel
US9246668B1 (en) * 2013-03-12 2016-01-26 Marvell International Ltd. Unified control for digital timing recovery and packet processing
US9093115B1 (en) 2013-03-15 2015-07-28 Seagate Technology Llc Track interference cancellation
WO2014186445A1 (en) * 2013-05-15 2014-11-20 Huawei Technologies Co., Ltd. Low complexity, adaptive, fractionally spaced equalizer with non-integer sampling
US8760794B1 (en) 2013-05-16 2014-06-24 HGST Netherlands B.V. Servo systems with augmented servo bursts
US8767341B1 (en) 2013-05-16 2014-07-01 HGST Netherlands B.V. Servo systems with augmented servo bursts
US9544168B2 (en) 2013-06-06 2017-01-10 Pioneer Corporation Channel estimation device, receiving device, channel estimation method, channel estimation program, and recording medium
US9165597B2 (en) 2013-06-28 2015-10-20 Seagate Technology Llc Time-multiplexed single input single output (SISO) data recovery channel
WO2015009718A1 (en) * 2013-07-16 2015-01-22 Marvell World Trade Ltd. Systems and methods for calibrating read and write operations in two dimensional magnetic recording
US9129650B2 (en) * 2013-07-25 2015-09-08 Avago Technologies General Ip (Singapore) Pte. Ltd. Array-reader based magnetic recording systems with frequency division multiplexing
CN103476026B (en) * 2013-09-06 2017-01-18 中国科学院软件研究所 Self-adaption covert communication method based on satellite channel coding
US9064537B1 (en) 2013-09-13 2015-06-23 Western Digital Technologies, Inc. Disk drive measuring radial offset between heads by detecting a difference between ramp contact
CN103560984B (en) * 2013-10-31 2017-12-15 北京工业大学 Channel self-adapting method of estimation based on multi-model weighting soft handover
US9245578B1 (en) 2013-11-26 2016-01-26 Western Digital Technologies, Inc. Disk drive compensating for inter-track interference in analog read signal
US9257145B1 (en) * 2013-11-27 2016-02-09 Western Digital Technologies, Inc. Disk drive measuring down-track spacing of read sensors
JP2015122632A (en) * 2013-12-24 2015-07-02 富士通株式会社 Optical communication receiver
US9245579B2 (en) * 2013-12-27 2016-01-26 Avago Technologies General Ip (Singapore) Pte. Ltd. Two-dimensional magnetic recording reader offset estimation
US9025269B1 (en) 2014-01-02 2015-05-05 Western Digital Technologies, Inc. Disk drive compensating for cycle slip of disk locked clock when reading mini-wedge
US9645763B2 (en) 2014-01-13 2017-05-09 Seagate Technology Llc Framework for balancing robustness and latency during collection of statistics from soft reads
WO2015107684A1 (en) * 2014-01-20 2015-07-23 株式会社日立製作所 Information replay device, information replay method, information storage device, and information storage method
CN103825852A (en) * 2014-01-28 2014-05-28 华南理工大学 Dual-mode adaptive decision feedback equalization module and realization method thereof
US9099132B1 (en) * 2014-02-25 2015-08-04 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for multi-head separation determination
US9280995B2 (en) 2014-03-28 2016-03-08 Avago Technologies General Ip (Singapore) Pte. Ltd. Locking a disk-locked clock using timestamps of successive servo address marks in a spiral servo track
US8861111B1 (en) * 2014-04-01 2014-10-14 Lsi Corporation Two dimensional magnetic recording servo system phase alignment
US9019642B1 (en) 2014-04-02 2015-04-28 Lsi Corporation Synchronization mark detection for multi-dimensional magnetic recording
US8837068B1 (en) * 2014-04-14 2014-09-16 Lsi Corporation Two dimensional magnetic recording servo system adaptive combination
US8861112B1 (en) * 2014-04-23 2014-10-14 Lsi Corporation Two dimensional magnetic recording system head separation estimator
US20150341158A1 (en) * 2014-05-23 2015-11-26 Mediatek Inc. Loop gain calibration apparatus for controlling loop gain of timing recovery loop and related loop gain calibration method
US8953276B1 (en) 2014-06-05 2015-02-10 Seagate Technology Llc Correcting position error based on reading first and second user data signals
US9417797B2 (en) 2014-06-09 2016-08-16 Seagate Technology Llc Estimating read reference voltage based on disparity and derivative metrics
US9431052B2 (en) * 2014-06-26 2016-08-30 Marvell World Trade Ltd. Two dimensional magnetic recording systems, devices and methods
US9196298B1 (en) * 2014-06-30 2015-11-24 Avago Technologies General Ip (Singapore) Pte. Ltd. Zero phase start for array reader magnetic recording system
CN104052691B (en) * 2014-07-02 2017-02-15 东南大学 MIMO-OFDM system channel estimation method based on compressed sensing
US9117470B1 (en) 2014-07-17 2015-08-25 International Business Machines Corporation Write delay to de-skew data in read while write function for tape storage devices
US9245580B1 (en) * 2014-10-31 2016-01-26 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for three reader storage access
US9007707B1 (en) * 2014-10-31 2015-04-14 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for accessing codewords in parallel using a three sensor reader
US9680484B2 (en) * 2014-12-05 2017-06-13 Texas Instruments Incorporated Clock conditioner circuitry with improved holdover exit transient performance
US9690361B2 (en) * 2014-12-24 2017-06-27 Intel Corporation Low-power context-aware control for analog frontend
US9424878B1 (en) * 2015-02-04 2016-08-23 Avago Technologies General Ip (Singapore) Pte. Ltd. Two dimensional magnetic recording head separation calculator
US9401161B1 (en) 2015-03-11 2016-07-26 Seagate Technology Llc Magnetic read head with multiple read transducers each having different design characteristics
US9286915B1 (en) 2015-03-12 2016-03-15 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for format efficient sector fragment processing
US9508369B2 (en) 2015-03-13 2016-11-29 Seagate Technology Llc Defining a maximum sequential write duration for a data storage device utilizing heat-assisted recording
US9311959B1 (en) 2015-03-30 2016-04-12 Seagate Technology Llc Read channel optimization using multi-dimensional smoothing
US9489976B2 (en) 2015-04-06 2016-11-08 Seagate Technology Llc Noise prediction detector adaptation in transformed space
US9590803B2 (en) * 2015-05-22 2017-03-07 Seagate Technology Llc Timing error processor that uses the derivative of an interpolator function
CN106201333B (en) 2015-06-01 2019-04-12 株式会社东芝 Storage device, controller and data reading method again
CN105050137B (en) * 2015-06-18 2019-06-28 西安电子科技大学 A kind of car networking jamming control method based on information physical system model
US9564157B1 (en) 2015-08-21 2017-02-07 Seagate Technology Llc System and method for detecting reader-writer offset in a heat-assisted magnetic recording head
US10347343B2 (en) 2015-10-30 2019-07-09 Seagate Technology Llc Adaptive read threshold voltage tracking with separate characterization on each side of voltage distribution about distribution mean
US10192614B2 (en) 2015-10-30 2019-01-29 Seagate Technology Llc Adaptive read threshold voltage tracking with gap estimation between default read threshold voltages
US9542972B1 (en) 2015-11-12 2017-01-10 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for multi-head coefficient based scaling
US9837990B1 (en) 2015-12-11 2017-12-05 Syntropy Systems, Llc Digital signal processor
US10043582B2 (en) 2016-02-11 2018-08-07 Seagate Technology Llc Establishing parameters of subsequent read retry operations based on syndrome weights of prior failed decodings
US9536563B1 (en) 2016-02-16 2017-01-03 Seagate Technology Llc Detecting shingled overwrite errors
US10445171B2 (en) 2016-02-29 2019-10-15 Seagate Technology Llc On-the-fly error detection algorithm during retry procedure
CN105656819B (en) * 2016-03-21 2018-12-18 电子科技大学 A kind of adaptive channel estimation method based on compressed sensing and extensive MIMO
CN105812299B (en) * 2016-04-22 2020-05-15 中国地质大学（武汉） Wireless sensor network channel estimation method based on joint block sparse reconstruction
US9947362B1 (en) 2016-06-25 2018-04-17 Seagate Technology Llc Asynchronous interference cancellation
US10180868B2 (en) 2016-07-08 2019-01-15 Seagate Technology Llc Adaptive read threshold voltage tracking with bit error rate estimation based on non-linear syndrome weight mapping
US10290358B2 (en) 2016-07-08 2019-05-14 Seagate Technology Llc Independent read threshold voltage tracking for multiple dependent read threshold voltages using syndrome weights
US9819456B1 (en) 2016-10-17 2017-11-14 Seagate Technology Llc Preamble detection and frequency offset determination
US10164760B1 (en) * 2016-10-18 2018-12-25 Seagate Technology Llc Timing excursion recovery
US10152457B1 (en) 2016-10-25 2018-12-11 Seagate Technology Llc Target parameter adaptation
US9998136B1 (en) * 2017-02-17 2018-06-12 Seagate Technology Llc Loop consistency using multiple channel estimates
JP2018160302A (en) 2017-03-23 2018-10-11 株式会社東芝 Storage device and controller
US10014026B1 (en) 2017-06-20 2018-07-03 Seagate Technology Llc Head delay calibration and tracking in MSMR systems
US10276233B1 (en) 2017-10-31 2019-04-30 Seagate Technology Llc Adaptive read threshold voltage tracking with charge leakage mitigation using threshold voltage offsets
US10388368B2 (en) 2017-10-31 2019-08-20 Seagate Technology Llc Adaptive read threshold voltage tracking with charge leakage mitigation using charge leakage settling time
US10297281B1 (en) 2017-11-06 2019-05-21 Seagate Technology Llc Servo sector detection
US10498565B1 (en) 2018-09-05 2019-12-03 Macom Technology Solutions Holding, Inc Sampling phase optimization for digital modulated signals

Also Published As

Publication number Publication date
SG10201804852XA (en) 2019-01-30
CN109104204A (en) 2018-12-28
US20200005819A1 (en) 2020-01-02
US11361788B2 (en) 2022-06-14
US20180366155A1 (en) 2018-12-20
TW201907293A (en) 2019-02-16
CN109104200B (en) 2022-07-01
US10936003B1 (en) 2021-03-02
CN109104204B (en) 2020-09-22
CN109104200A (en) 2018-12-28
US10469290B1 (en) 2019-11-05
US20180366156A1 (en) 2018-12-20
CN109104388A (en) 2018-12-28
TWI701591B (en) 2020-08-11
TW201905682A (en) 2019-02-01
US10276197B2 (en) 2019-04-30
CN109104388B (en) 2021-06-11
US10607648B1 (en) 2020-03-31
US20200065262A1 (en) 2020-02-27
US10014026B1 (en) 2018-07-03
US20180367164A1 (en) 2018-12-20
US10755734B2 (en) 2020-08-25
US10665256B2 (en) 2020-05-26
US10714134B2 (en) 2020-07-14
US10157637B1 (en) 2018-12-18
US10410672B1 (en) 2019-09-10
US10177771B1 (en) 2019-01-08
SG10201805246XA (en) 2019-01-30
TW201907260A (en) 2019-02-16
US20180366149A1 (en) 2018-12-20
TWI691899B (en) 2020-04-21
US10068608B1 (en) 2018-09-04
US10496559B1 (en) 2019-12-03

Similar Documents

Publication Publication Date Title
SG10201805247VA (en) Hybrid timing recovery
EP4250747A3 (en) Wireless coordination of audio sources
EP2903162A3 (en) A MDLL/PLL hybrid design with uniformly distributed output phases
EP3701631B8 (en) Digital-to-time converter (dtc) assisted all digital phase locked loop (adpll) circuit
JP2008157971A5 (en)
GB2431061A (en) Synchronous follow-up apparatus and synchronous follow-up method
MX2018003675A (en) Integrated radio-frequency circuit, radar sensor and operating method.
TWI799538B (en) Quadrature clock generation circuit and method
TW201614975A (en) Clock and data recovery circuit and method
EP3780478A4 (en) Phase detection method, phase detection circuit, and clock recovery device
MX2019014804A (en) Predicting structured illumination parameters.
TW200634480A (en) Multi-phase clock generator and method thereof
WO2010033436A3 (en) Techniques for generating fractional clock signals
WO2014182448A3 (en) Synchronous data-link throughput enhancement technique based on data signal duty-cycle and phase modulation/demodulation
EP4235362A3 (en) Interface system
WO2016109777A3 (en) Hybrid timing for a gnss receiver
WO2016205630A3 (en) Frequency multipliers
GB2547609A (en) Synchronizing downhole subs
EP4049370A4 (en) Digital clock circuit for generating high-ratio frequency multiplication clock signal
WO2016032191A3 (en) Ultra low power wideband asynchronous binary phase shift keying demodulation circuit using first order sideband filters aligned at zero degree phase
EP3761511A4 (en) Frequency multiplier, digital phase lock loop circuit and frequency multiplying method
GB2552633A (en) Improved pulse generation for downhole logging
TW200725624A (en) Clock synchronization apparatus
TW201613302A (en) Half-rate clock-data recovery circuit and method thereof
TW200740123A (en) Methods for adjusting sampling clock of sampling circuit and related apparatuses