CN109037350A - Thin film transistor (TFT) and preparation method thereof, array substrate - Google Patents
Thin film transistor (TFT) and preparation method thereof, array substrate Download PDFInfo
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- CN109037350A CN109037350A CN201810861413.7A CN201810861413A CN109037350A CN 109037350 A CN109037350 A CN 109037350A CN 201810861413 A CN201810861413 A CN 201810861413A CN 109037350 A CN109037350 A CN 109037350A
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- 239000000758 substrate Substances 0.000 title claims abstract description 39
- 238000002360 preparation method Methods 0.000 title claims abstract description 36
- 239000010409 thin film Substances 0.000 title claims abstract description 36
- 229910052751 metal Inorganic materials 0.000 claims abstract description 123
- 239000002184 metal Substances 0.000 claims abstract description 123
- 238000009413 insulation Methods 0.000 claims abstract description 51
- 238000000034 method Methods 0.000 claims abstract description 29
- 238000002161 passivation Methods 0.000 claims abstract description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims description 71
- 239000007769 metal material Substances 0.000 claims description 27
- 239000011149 active material Substances 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- 238000012545 processing Methods 0.000 claims description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 238000004380 ashing Methods 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 239000011651 chromium Substances 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 238000000059 patterning Methods 0.000 abstract description 5
- 238000000151 deposition Methods 0.000 description 6
- 238000005260 corrosion Methods 0.000 description 5
- 230000007797 corrosion Effects 0.000 description 5
- 239000007772 electrode material Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012827 research and development Methods 0.000 description 2
- 238000003325 tomography Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000027648 face development Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
Abstract
The present invention provides a kind of thin film transistor (TFT) and preparation method thereof, array substrate, the thin film transistor (TFT) includes substrate, grid, gate insulation layer, the first metal layer, active layer, second metal layer, passivation layer, grid is set on substrate, gate insulation layer covers the grid, the first metal layer includes the first electrode and second electrode being arranged at intervals on gate insulation layer, second metal layer includes spaced source electrode and drain electrode, one end of active layer is located between first electrode and source electrode, the other end of active layer is located between second electrode and drain electrode, passivation layer is covered in source electrode, drain electrode, the exposed surface of active layer, by the way that active layer is located between the first metal layer and second metal layer, improve the contact performance between active layer and second metal layer.The first metal layer is formed with second metal layer by patterning processes twice in preparation method of the invention, so as to avoid there is corner cut.
Description
Technical field
The present invention relates to array substrate manufacturing technology fields more particularly to a kind of thin film transistor (TFT) and preparation method thereof, battle array
Column substrate.
Background technique
Thin film transistor active matrix liquid crystal display (TFTAMLCD) is with its high information quantity, multi-grey level and is able to achieve coloured silk
Color video shows the dominant technology as current field of information display and the hot spot of research and development.As TFTAMLCD is to big face
Development long-pending, high-definition, the requirement to metal electrode material are also higher and higher.On the one hand, it is desirable that the resistance of metal electrode is wanted
It is low, to reduce image fault caused by signal delay；On the other hand, the thermal stability of metallic film and adhesion are more preferable.
Therefore, the preparation metallic film that resistivity is low, thermal stability and adhesion are good and route become the emphasis for research and development.
In existing TFT, in order to improve the contact performance of TFT electrode, TFT electrode generallys use multi-layer metal structure,
As shown in Figure 1, wherein TFT electrode includes the first metal layer 4 and second metal layer 6, and the first metal layer 4 is contacted with active layer 5.
In existing TFT preparation process, good first metal material layer of adhesion, the second metal material are first deposited on active layer 5
Then the bed of material is etched through photoetching process, dissimilar metal is in same etching solution and is in contact with each other or by other conductors
Together with due to corrosion potential difference, it will cause the local corrosion of the first metal material layer, the second metal material layer contact site
That is there is corner cut, as shown in figure 1 shown in dotted line frame, the appearance of corner cut in galvanic corrosion (galvanic corrosion) phenomenon
It easily causes subsequent passivating film tomography, TFT electrically unstable etc. abnormal, or even reduces product yield.
Summary of the invention
To solve the above-mentioned problems, the present invention provides a kind of thin film transistor (TFT) and preparation method thereof, array substrate, Neng Gouti
The contact performance between active layer and second metal layer is risen, corner cut is avoided the occurrence of down, improves the electric property of thin film transistor (TFT).
It is proposed by the present invention the specific technical proposal is: provide a kind of thin film transistor (TFT), the thin film transistor (TFT) include substrate,
Grid, gate insulation layer, the first metal layer, active layer, second metal layer, passivation layer, the grid is set on the substrate, described
Gate insulation layer covers the grid, and the first metal layer includes the first electrode being arranged at intervals on the gate insulation layer and the
Two electrodes, the second metal layer include spaced source electrode and drain electrode, and one end of the active layer is located in described first
Between electrode and the source electrode, the other end of the active layer is located between the second electrode and the drain electrode, described blunt
Change layer and is covered in the exposed surface of the source electrode, drain electrode, active layer.
Further, the source electrode is contacted with the first electrode, and the drain electrode is contacted with the second electrode.
Further, the adhesion of the first metal layer and the gate insulation layer be greater than the second metal layer with it is described
The adhesion of gate insulation.
Further, the material of the second metal layer is copper.
Further, the material of the first metal layer is selected from one of molybdenum, chromium, titanium.
The present invention also provides a kind of array substrate, the array substrate includes any thin film transistor (TFT) as above.
The present invention also provides a kind of preparation method of thin film transistor (TFT), the preparation method comprising steps of
One substrate is provided；
Grid and gate insulation layer are formed over the substrate, and the gate insulation layer covers the grid；
The first metal layer is formed on the gate insulation layer, the first metal layer includes being arranged at intervals at the gate insulation
First electrode and second electrode on layer；
Active layer, second metal layer are formed on the first metal layer, the second metal layer includes spaced
Source electrode and drain electrode, one end of the active layer are located between the first electrode and the source electrode, the active layer it is another
End is located between the second electrode and the drain electrode；
Deposit passivation layer, the passivation layer are covered in the exposed surface of the source electrode, drain electrode, active layer.
Further, active layer is formed on the first metal layer, second metal layer specifically includes:
Active material is deposited on the first metal layer；
It is coated with third photoresist layer on the active material, the third photoresist layer is exposed by third road light shield
Light makes the third photoresist pattern layers, forms third photoresist region；
It is removed by etch process not by the active material of the third photoresist region overlay, forms active layer, it is described
One end of active layer is contacted with the first electrode and covering part first electrode, the other end of the active layer and described second
Electrode contact and covering part second electrode；
The second metal material layer is deposited on the gate insulation layer, first electrode, second electrode and active layer；
On second metal material layer be coated with the 4th photoresist layer, by the 4th light shield to the 4th photoresist layer into
Row exposure, makes the 4th photoresist pattern layers, forms the 4th photoresist region being spaced apart from each other；
It is removed by etch process not by the second metal material layer of the 4th photoresist region overlay, forms the second metal
Layer, the second metal layer includes spaced source electrode and drain electrode, and one end of the active layer is located in the first electrode
Between the source electrode, the other end of the active layer is located between the second electrode and the drain electrode, the source electrode with
The first electrode contact, the drain electrode are contacted with the second electrode.
Further, active layer is formed on the first metal layer, second metal layer includes:
Active material is deposited on the first metal layer；
The second metal material layer is deposited on the active material；
On second metal material layer coat third photoresist layer, by third road light shield to the third photoresist layer into
The exposure of row grayscale, makes the third photoresist pattern layers, forms third photoresist region, third photoresist region includes middle part
With the side for being located at the middle part two sides, the thickness of the middle part is less than the thickness of side；
It is removed by etch process not by the active material of the third photoresist region overlay, the second metal material layer,
Active layer is formed, one end of the active layer is contacted with the first electrode, the other end of the active layer and second electricity
Pole contact；
Ashing processing is carried out to third photoresist region, to remove middle part and reduce the thickness of side, retains part
Side；
The second metal material layer not covered by the portion sides is removed by etch process, forms second metal layer,
The second metal layer includes spaced source electrode and drain electrode, and one end of the active layer is located in the first electrode and institute
It states between source electrode, the other end of the active layer is located between the second electrode and the drain electrode.
Thin film transistor (TFT) proposed by the present invention includes active layer, source electrode, drain electrode and spaced first electrode and
Two electrodes, one end of the active layer are located between the first electrode and the source electrode, the other end folder of the active layer
Between the second electrode and the drain electrode, by the way that active layer is located between the first metal layer and second metal layer,
Improve the contact performance between active layer and second metal layer.The first metal layer and the second metal in preparation method of the invention
Layer is formed by patterning processes twice, to avoid the occurrence of down corner cut, improves the electric property of thin film transistor (TFT).
Detailed description of the invention
With reference to the accompanying drawing, by the way that detailed description of specific embodiments of the present invention, technical solution of the present invention will be made
And other beneficial effects are apparent.
Fig. 1 is the structural schematic diagram for occurring corner cut in existing thin film transistor (TFT) preparation process；
Fig. 2 is the structural schematic diagram of array substrate in the embodiment of the present invention 1；
Fig. 3 a~3f is the preparation method flow chart of thin film transistor (TFT) in embodiment 1；
Fig. 4 a~4e is the preparation flow figure of grid and gate insulation layer in embodiment 1；
Fig. 5 a~5d is the preparation flow figure of the first metal layer in embodiment 1；
Fig. 6 a~6d is the preparation flow figure of active layer in embodiment 1；
Fig. 7 a~7d is the preparation flow figure of second metal layer in embodiment 1；
Fig. 8 is the structural schematic diagram of array substrate in the embodiment of the present invention 2；
Fig. 9 a~9j is the preparation method flow chart of thin film transistor (TFT) in embodiment 2.
Specific embodiment
Hereinafter, with reference to the accompanying drawings to detailed description of the present invention embodiment.However, it is possible to come in many different forms real
The present invention is applied, and the present invention should not be construed as limited to the specific embodiment illustrated here.On the contrary, providing these implementations
Example is in order to explain the principle of the present invention and its practical application, to make others skilled in the art it will be appreciated that the present invention
Various embodiments and be suitable for the various modifications of specific intended application.In the accompanying drawings, identical label will be used for table always
Show identical element.
The present invention provides a kind of thin film transistor (TFT), the thin film transistor (TFT) includes substrate, grid, gate insulation layer, first
Metal layer, active layer, second metal layer, passivation layer, grid are set on substrate, and gate insulation layer covers grid, the first metal layer packet
The first electrode and second electrode being arranged at intervals on gate insulation layer are included, second metal layer includes spaced source electrode and leakage
One end of pole, active layer is located between first electrode and source electrode, and the other end of active layer is located in second electrode and drain electrode
Between, passivation layer is covered in the exposed surface of source electrode, drain electrode, active layer.
The present invention also provides a kind of preparation methods of thin film transistor (TFT), and the preparation method comprises the following steps:
One substrate is provided；
Grid and gate insulation layer is formed on the substrate, gate insulation layer covers grid；
The first metal layer is formed on gate insulation layer, the first metal layer includes the first electricity being arranged at intervals on gate insulation layer
Pole and second electrode；
Active layer, second metal layer are formed on the first metal layer, and second metal layer includes spaced source electrode and leakage
One end of pole, active layer is located between first electrode and source electrode, and the other end of active layer is located in second electrode and drain electrode
Between；
Deposit passivation layer, passivation layer are covered in the exposed surface of source electrode, drain electrode, active layer.
Thin film transistor (TFT) proposed by the present invention includes active layer, source electrode, drain electrode and spaced first electrode and
Two electrodes, one end of the active layer are located between the first electrode and the source electrode, the other end folder of the active layer
Between the second electrode and the drain electrode, by the way that active layer is located between the first metal layer and second metal layer,
Improve the contact performance between active layer and second metal layer.The first metal layer and the second metal in preparation method of the invention
Layer is formed by patterning processes twice, corner cut is occurred down so as to avoid by a patterning processes, is improved thin film transistor (TFT)
Electric property.
To carry out the structure and preparation method of thin film transistor (TFT) of the invention below by two specific embodiments
Detailed description.
Embodiment 1
Referring to Fig. 2, the array substrate in the present embodiment includes multiple thin film transistor (TFT)s 10, and multiple thin film transistor (TFT)s are in array
Setting.Thin film transistor (TFT) 10 includes substrate 1, grid 2, gate insulation layer 3, the first metal layer 4, active layer 5, second metal layer 6, blunt
Change layer 7.Grid 2 is set on substrate 1, and gate insulation layer 3 covers grid 2, and the first metal layer 4 includes being arranged at intervals at gate insulation layer 3
On first electrode 41 and second electrode 42, second metal layer 6 includes spaced source electrode 61 and drain electrode 62, and source electrode 61 is located at
It is contacted in first electrode 41 and with first electrode 41, drain electrode 62 is located in second electrode 42 and contacts with second electrode 42, active
Layer 5 includes source contact end 51, back groove 52, drain contact end 53, and source contact end 51 is located in first electrode 41 and source
Between pole 61 and covering part first electrode 41, drain contact end 53 is located between second electrode 42 and drain electrode 62 simultaneously covering part
Divide second electrode 42, back groove 52 is between first electrode 41 and second electrode 42 and corresponding with grid 2, and passivation layer 7 covers
It is placed on source electrode 61, drain the exposed surface of 62, active layer 5.
In the present embodiment, first electrode 41 and second electrode 42 and the adhesion of gate insulation layer 3 are greater than source electrode 61 and drain electrode
62 with the adhesion of gate insulation layer 3.The material of gate insulation layer 3 is insulating materials, preferably, the material of second metal layer 6 is copper,
Since copper has the excellent performances such as Low ESR, high conductivity, become the electrodes conduct metal material of mainstream, still, copper is exhausted with grid
Adhesion between edge layer is poor, therefore, the first metal layer 4, the second gold medal is arranged between second metal layer 6 and gate insulation layer 3
Belong to layer 6 to contact with the first metal layer 4, the material of the first metal layer 4 is selected from one of molybdenum, chromium, titanium, the first metal layer 4 and grid
There is preferable adhesion, to promote the heat of metal electrode while reducing the resistivity of metal electrode between insulating layer 3
Stability and adhesion.Wherein, the metal electrode in the present embodiment refers to source electrode 61 or drain electrode 62.
In the present embodiment, source contact end 51 is set between first electrode 41 and source electrode 61, and drain contact end 53 is located in
Between second electrode 42 and drain electrode 62, by the way that active layer 5 to be located between the first metal layer 4 and second metal layer 6, improve
Contact performance between active layer 5 and second metal layer 6.
Array substrate in the present embodiment further includes pixel electrode 8, and pixel electrode 8 is connect by via hole with drain electrode 62.
Referring to Fig. 3 a~3f, the present embodiment additionally provides the first embodiment of the preparation method of above-mentioned thin film transistor (TFT),
In the first embodiment, the preparation method comprising steps of
S1, a substrate 1 is provided, as shown in Figure 3a；
S2,4 form grid 2 and gate insulation layer 3 on substrate 1, and gate insulation layer 3 covers grid 2, as shown in Figure 3b；
S3,4 form the first metal layer 4 on gate insulation layer 3, and the first metal layer 4 includes being arranged at intervals on gate insulation layer 3
First electrode 41 and second electrode 42, as shown in Figure 3c；
S4,4 form active layer 5 on the first metal layer 4, and active layer 5 includes source contact end 51, back groove 52, leakage
Pole contact jaw 53, source contact end 51 contact and covering part first electrode 41 with first electrode 41, drain contact end 53 and the
Two electrodes 42 contact and covering part second electrode 42, carry on the back groove 52 between first electrode 41 and second electrode 42 and with
Grid 2 is corresponding, as shown in Figure 3d；
S5, second metal layer 6 is formed on the first metal layer 4 and active layer 5, second metal layer 6 includes spaced
Source electrode 61 and drain electrode 62, source electrode 61 is located in first electrode 41, and drain electrode 62 is located in second electrode 42,51 sandwiched of source contact end
Between first electrode 41 and source electrode 61, drain contact end 53 is located between second electrode 42 and drain electrode 62, source electrode 61 and the
The contact of one electrode 41, drain electrode 62 are contacted with second electrode 42, as shown in Figure 3 e；
S6, deposit passivation layer 7, passivation layer 7 is covered in source electrode 61, drain the exposed surface of 62, active layer 5, such as Fig. 3 f institute
Show.
In the preparation method of the present embodiment, the first metal layer 4 is obtained with second metal layer 6 by patterning processes twice,
When so as to avoid the formation of the first metal layer 4 and second metal layer 6, since etching liquid is to the etching speed of different metal materials
Rate difference causes the first metal layer 4 and 6 contact site of second metal layer local corrosion occur and the phenomenon of falling corner cut occur, after causing
Continuous passivation layer tomography, thin film transistor (TFT) are electrically unstable etc., improve production yield.
Referring to Fig. 4 a~4e, specifically, step S2 includes:
S21, gate material layers 20, the first photoresist layer 100 are sequentially depositing on substrate 1, as shown in fig. 4 a；
S22, the first photoresist layer 100 is exposed by first of light shield, makes the first photoresist pattern layers, form first
Photoresist region, as shown in Figure 4 b；
S23, it is removed by etch process not by the gate material layers 20 of the first photoresist region overlay, forms grid 2, such as scheme
Shown in 4c；
S24, the first photoresist region is removed by photoresist cineration technics, as shown in figure 4d；
S25, gate insulation layer 3 is deposited on substrate 1 and grid 2, gate insulation layer 3 covers grid 2, as shown in fig 4e.
Referring to Fig. 5 a~5d, specifically, step S3 includes:
S21, the first metal material layer 40, the second photoresist layer 101 are sequentially depositing on gate insulation layer 3, as shown in Figure 5 a；
S22, the second photoresist layer 101 is exposed by second light shield, makes the second photoresist pattern layers, formed mutual
The second photoresist region at interval, as shown in Figure 5 b；
S23, it is removed by etch process not by the first metal material layer 40 of the second photoresist region overlay, forms the first gold medal
Belong to layer 4, the first metal layer 4 includes the first electrode 41 and second electrode 42 being arranged at intervals on gate insulation layer 3, such as Fig. 5 c institute
Show；
S24, the second photoresist region is removed by photoresist cineration technics, as fig 5d.
Referring to Fig. 6 a~6d, specifically, step S4 includes:
S41, active material 50, third photoresist layer 102 are sequentially depositing on the first metal layer 4, as shown in Figure 6 a；
S42, third photoresist layer 102 is exposed by third road light shield, makes third photoresist pattern layers, form third
Photoresist region, as shown in Figure 6 b；
S43, it is removed by etch process not by the active material 50 of third photoresist region overlay, forms active layer 5, have
Active layer 5 includes source contact end 51, back groove 52, drain contact end 53, and source contact end 51 contacts simultaneously with first electrode 41
Covering part first electrode 41, drain contact end 53 is contacted with second electrode 42 and covering part second electrode 42, carries on the back groove
52 is between first electrode 41 and second electrode 42 and corresponding with grid 2, as fig. 6 c；
S44, third photoresist region is removed by photoresist cineration technics, as shown in fig 6d.
Referring to Fig. 7 a~7d, specifically, step S5 includes:
S51, the second metal material layer 60, the 4th photoresist layer are deposited on gate insulation layer 3, the first metal layer 4, active layer 5
103, as shown in Figure 7a；
S52, the 4th photoresist layer 103 is exposed by the 4th light shield, makes the 4th photoresist pattern layers, formed mutual
The 4th photoresist region at interval, as shown in Figure 7b；
S53, it is removed by etch process not by the second metal material layer 60 of the 4th photoresist region overlay, forms the second gold medal
Belong to layer 6, second metal layer 6 includes spaced source electrode 61 and drain electrode 62, source contact end 51 be located in first electrode 41 with
Between source electrode 61, drain contact end 53 is located between second electrode 42 and drain electrode 62, and source electrode 61 is contacted with first electrode 41, leakage
Pole 62 is contacted with second electrode 42, as shown in Figure 7 c；
S54, the 4th photoresist region is removed by photoresist cineration technics, as shown in figure 7d.
When preparing array substrate, after step S6, it is also necessary to be carried out by the 5th light shield technique to passivation layer
Graphical treatment forms via hole on the passivation layer, and then, pixel deposition electrode material layer, passes through the 6th light on the passivation layer
Cover technique to carry out patterned process to pixel electrode material layer, obtains pixel electrode 8, and the preparation process of entire array substrate needs
Need six light shields.
Embodiment 2
Referring to Fig. 8, the present embodiment difference from example 1 is that, source electrode 61 is not contacted with first electrode 41, is drained
62 do not contact with second electrode 42.
Referring to Fig. 9 a~9j, the preparation method of the present embodiment uses half-tone mask technique, and the preparation method includes step
It is rapid:
S1, a substrate 1 is provided, as illustrated in fig. 9；
S2, grid 2 and gate insulation layer 3 are formed on substrate 1, gate insulation layer 3 covers grid 2, as shown in figure 9b；
S3, the first metal layer 4 is formed on gate insulation layer 3, the first metal layer 4 includes being arranged at intervals on gate insulation layer 3
First electrode 41 and second electrode 42, as is shown in fig. 9 c；
S4, active material 50, the second metal material layer 60, third photoresist layer 70 are sequentially depositing on the first metal layer 4,
As shown in figure 9d；
S5, grayscale exposure is carried out to third photoresist layer 70 by third road light shield, makes third photoresist pattern layers, form the
Three photoresist regions, third photoresist region include middle part and positioned at the side of the middle part two sides, and the thickness of middle part is less than side
The thickness in portion, as shown in figure 9e；
S6, it is removed by etch process not by the active material 50 of third photoresist region overlay, the second metal material layer
60, active layer 5 is formed, as shown in figure 9f, active layer 5 includes source contact end 51, back groove 52, drain contact end 53, source
Pole contact jaw 51 extends to the surface of first electrode 41, and drain contact end 53 extends to the surface of second electrode 42, carries on the back groove
52 is between first electrode 41 and second electrode 42 and corresponding with grid 2；
S7, ashing processing is carried out to third photoresist region, to remove middle part and reduce the thickness of side, retains part side
Portion, as shown in figure 9g；
S8, the second metal material layer 60 not covered by portion sides is removed by etch process, forms second metal layer
6, second metal layer 6 includes spaced source electrode 61 and drain electrode 62, and source contact end 51 is located in first electrode 41 and source electrode
Between 61, drain contact end 53 is located between second electrode 42 and drain electrode 62, as shown in Fig. 9 h；
S9, third photoresist region is removed by photoresist cineration technics, as illustrated in fig. 9i
S10, deposit passivation layer 7, passivation layer 7 is covered in source electrode 61, drain the exposed surface of 62, active layer 5, such as Fig. 9 j institute
Show.
Step S1~S3 is in the same manner as in Example 1 in the present embodiment, and which is not described herein again.When preparing array substrate,
After step S10, it is also necessary to be patterned processing to passivation layer by the 4th light shield technique, be formed on the passivation layer
Hole, then, pixel deposition electrode material layer, carries out pixel electrode material layer by the 5th light shield technique on the passivation layer
Patterned process, obtains pixel electrode 8, and the preparation process of entire array substrate needs five light shields.Therefore, the present embodiment
Active layer 5, second metal layer are formed on the first metal layer 4 by half-tone mask technique in the preparation method of thin film transistor (TFT)
6, one of light shield can be saved relative to first embodiment, to simplify preparation process, reduce preparation cost.
The above is only the specific embodiment of the application, it is noted that for the ordinary skill people of the art
For member, under the premise of not departing from the application principle, several improvements and modifications can also be made, these improvements and modifications are also answered
It is considered as the protection scope of the application.
Claims (9)
1. a kind of thin film transistor (TFT), which is characterized in that including substrate, grid, gate insulation layer, the first metal layer, active layer, second
Metal layer, passivation layer, the grid are set on the substrate, and the gate insulation layer covers the grid, the first metal layer
Including the first electrode and second electrode being arranged at intervals on the gate insulation layer, the second metal layer includes spaced
Source electrode and drain electrode, one end of the active layer are located between the first electrode and the source electrode, the active layer it is another
End is located between the second electrode and the drain electrode, and it is exposed that the passivation layer is covered in the source electrode, drain electrode, active layer
Surface.
2. thin film transistor (TFT) according to claim 1, which is characterized in that the source electrode is contacted with the first electrode, institute
Drain electrode is stated to contact with the second electrode.
3. thin film transistor (TFT) according to claim 2, which is characterized in that the first metal layer and the gate insulation layer
Adhesion is greater than the adhesion of the second metal layer and the gate insulation.
4. thin film transistor (TFT) according to claim 3, which is characterized in that the material of the second metal layer is copper.
5. thin film transistor (TFT) according to claim 4, which is characterized in that the material of the first metal layer be selected from molybdenum, chromium,
One of titanium.
6. a kind of array substrate, which is characterized in that including the thin film transistor (TFT) as described in claim 1-4 is any.
7. a kind of preparation method of thin film transistor (TFT), which is characterized in that the preparation method comprising steps of
One substrate is provided；
Grid and gate insulation layer are formed over the substrate, and the gate insulation layer covers the grid；
The first metal layer is formed on the gate insulation layer, the first metal layer includes being arranged at intervals on the gate insulation layer
First electrode and second electrode；
Active layer, second metal layer are formed on the first metal layer, the second metal layer includes spaced source electrode
And drain electrode, one end of the active layer are located between the first electrode and the source electrode, the other end folder of the active layer
Between the second electrode and the drain electrode；
Deposit passivation layer, the passivation layer are covered in the exposed surface of the source electrode, drain electrode, active layer.
8. preparation method according to claim 7, which is characterized in that form active layer, the on the first metal layer
Two metal layers specifically include:
Active material is deposited on the first metal layer；
It is coated with third photoresist layer on the active material, the third photoresist layer is exposed by third road light shield,
Make the third photoresist pattern layers, forms third photoresist region；
It is removed by etch process not by the active material of the third photoresist region overlay, forms active layer, it is described active
One end of layer is contacted with the first electrode and covering part first electrode, the other end of the active layer and the second electrode
Contact simultaneously covering part second electrode；
The second metal material layer is deposited on the gate insulation layer, first electrode, second electrode and active layer；
It is coated with the 4th photoresist layer on second metal material layer, the 4th photoresist layer is exposed by the 4th light shield
Light makes the 4th photoresist pattern layers, forms the 4th photoresist region being spaced apart from each other；
It is removed by etch process not by the second metal material layer of the 4th photoresist region overlay, forms second metal layer,
The second metal layer includes spaced source electrode and drain electrode, and one end of the active layer is located in the first electrode and institute
State between source electrode, the other end of the active layer is located between the second electrode and the drain electrode, the source electrode with it is described
First electrode contact, the drain electrode are contacted with the second electrode.
9. preparation method according to claim 7, which is characterized in that form active layer, the on the first metal layer
Two metal layers include:
Active material is deposited on the first metal layer；
The second metal material layer is deposited on the active material；
Third photoresist layer is coated on second metal material layer, and ash is carried out to the third photoresist layer by third road light shield
Rank exposure, makes the third photoresist pattern layers, forms third photoresist region, third photoresist region includes middle part and position
In the side of the middle part two sides, the thickness of the middle part is less than the thickness of side；
It is removed by etch process not by the active material of the third photoresist region overlay, the second metal material layer, is formed
Active layer, one end of the active layer are contacted with the first electrode, and the other end of the active layer connects with the second electrode
Touching；
Ashing processing is carried out to third photoresist region, to remove middle part and reduce the thickness of side, retains portion sides；
The second metal material layer not covered by the portion sides is removed by etch process, forms second metal layer, it is described
Second metal layer includes spaced source electrode and drain electrode, and one end of the active layer is located in the first electrode and the source
Between pole, the other end of the active layer is located between the second electrode and the drain electrode.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN201810861413.7A CN109037350A (en) | 2018-08-01 | 2018-08-01 | Thin film transistor (TFT) and preparation method thereof, array substrate |
| PCT/CN2019/070996 WO2020024561A1 (en) | 2018-08-01 | 2019-01-09 | Thin film transistor and preparation method therefor and array substrate |
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| CN201810861413.7A CN109037350A (en) | 2018-08-01 | 2018-08-01 | Thin film transistor (TFT) and preparation method thereof, array substrate |
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| WO2020024561A1 (en) * | 2018-08-01 | 2020-02-06 | 深圳市华星光电半导体显示技术有限公司 | Thin film transistor and preparation method therefor and array substrate |
| CN111434386A (en) * | 2019-01-15 | 2020-07-21 | 研能科技股份有限公司 | Method for manufacturing micro-fluid actuator |
| CN114967257A (en) * | 2022-05-11 | 2022-08-30 | Tcl华星光电技术有限公司 | Display panel and manufacturing method thereof |
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| WO2020024561A1 (en) * | 2018-08-01 | 2020-02-06 | 深圳市华星光电半导体显示技术有限公司 | Thin film transistor and preparation method therefor and array substrate |
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| WO2020024561A1 (en) | 2020-02-06 |
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