CN100590854C - Pixel structure and its making method - Google Patents
Pixel structure and its making method Download PDFInfo
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- CN100590854C CN100590854C CN200710166952A CN200710166952A CN100590854C CN 100590854 C CN100590854 C CN 100590854C CN 200710166952 A CN200710166952 A CN 200710166952A CN 200710166952 A CN200710166952 A CN 200710166952A CN 100590854 C CN100590854 C CN 100590854C
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Abstract
This invention relates to a manufacturing method for the pixel structure of an edge field switch LCD including: forming a patternized first conduction layer containing data lines and grid on a base board, forming a first insulation layer covering said first conduction layer on the board, forming a patternized semiconductor layer on the first insualtion layer of the grid, forming a patternized second conduction layer containing a source, a drain and grid lines, forming a pixel electrode connected with the drain and covering the display region, forming a second insulation layer, patternizing said second insulation layer and said first insulation layer and a third conduction layer containing data line connecting electrode, grid line connecting electrode and a common electrode.
Description
Technical field
The present invention relates to a kind of dot structure and manufacture method thereof of LCD; Be particularly related to a kind of fringing field and switch (Fringe Field Switching, FFS) dot structure of LCD and manufacture method thereof.
Background technology
In the present display product, the application of LCD is healed and is become extensively, becomes the main flow on the market gradually, yet with regard to the image performance of LCD, still has problems such as reaction speed is slow, aperture opening ratio is lower.For reaction rate and the aperture opening ratio that increases LCD, known have a kind of fringing field switching liquid crystal display (Fringe Field Switching Liquid Crystal Display, FFS-LCD), with general closed planar switching liquid crystal display (In-Plane Switching Liquid Crystal Display, IPS) compare, the fringing field switching liquid crystal display has higher aperture opening ratio, and integral light-transmitting is better, also has higher reaction rate than traditional LCD.
In the dot structure of fringing field switching liquid crystal display, pixel electrode stacked and insulated from each other and common electrode on the viewing area of dot structure, have been used, particularly pixel electrode has narrow slit structure, when applying a voltage on pixel electrode and the common electrode, just can between the edge of the narrow slit structure of pixel electrode and this common electrode, produce electric field, and then the liquid crystal that control is positioned on the dot structure rotates.
The dot structure of traditional fringing field switching liquid crystal display is shown in Figure 1A, Figure 1B, wherein this dot structure comprises control area 111 and viewing area 112, this one pixel structure process method please refer to Fig. 1 C to Fig. 1 I, for convenience of description, wherein Figure 1B to Fig. 1 I draws along the A-A ' among Figure 1A, B-B ' and C-C ' hatching.In the one pixel structure process method of traditional fringing field switching liquid crystal display, utilize first road photoetching and the etching work procedure earlier, on substrate 110, form the first metal layer 120 of patterning, the first metal layer 120 can comprise grid 121 and gate line 123, shown in Fig. 1 C, wherein gate line 123 extends to the connection pad zone 113 on the substrate 110.
Then, form first insulating barrier 130, to cover aforesaid the first metal layer 120, again with the second road photoetching and etching work procedure on first insulating barrier 130 and corresponding to the position of grid 121, form the semiconductor layer 140 of patterning, shown in Fig. 1 D, this semiconductor layer 140 can comprise semiconductor channel layer and ohmic contact layer (not shown).
The 3rd road photoetching and etching work procedure are used for forming first contact hole 131 on first insulating barrier 130, to expose gate line 123 in these connection pad zone 113 parts, shown in Fig. 1 E.The 4th road photoetching and etching work procedure are used to form second metal level 150 of patterning, this second metal level 150 comprises source electrode 151, drain electrode 152, data wire 153 and the first grid polar curve connection pad layer 154 that forms simultaneously, source electrode 151 and drain and 152 electrically connect this semiconductor layer 140 respectively wherein, data wire 153 acknowledge(ment) signals are to control this dot structure, first grid polar curve connection pad layer 154 electrically connects gate line 123 via first contact hole 131, shown in Fig. 1 F.
Form second insulating barrier 160 that covers aforementioned structure then, next, utilize the 5th road photoetching and etching work procedure, on second insulating barrier 160, form the transparent electrode layer of patterning, to form common electrode 171, shown in Fig. 1 G.
Form the 3rd insulating barrier 180 again, and utilize the 6th road photoetching and etching work procedure, carry out patterning at the 3rd above-mentioned insulating barrier 180 and second insulating barrier 160, etch second contact hole 181 and the 3rd contact hole 182, wherein second contact hole, 181 parts expose drain electrode 152, the 3rd contact hole 182 parts expose first grid polar curve connection pad layer 154, shown in Fig. 1 H.The 7th road photoetching and etching work procedure are used to form the 3rd metal level 190 of patterning, the 3rd metal level 190 comprises pixel electrode 191 and second grid line connection pad layer 192, pixel electrode 191 is formed on the viewing area 112 and via second contact hole 181 and electrically connects drain electrode 152,192 on second grid line connection pad layer electrically connects first grid polar curve connection pad layers 154 via the 3rd contact hole 182, and then electrically connect with gate line 123, shown in Fig. 1 I.
Comprehensive aforementioned operation as can be known, the one pixel structure process method of tradition fringing field switching liquid crystal display needs to use seven road photoetching and etching work procedures at least, and formed dot structure has comprised three-layer insulated layer, and it is high that this causes manufacturing cost and operation to expend time in.How to reduce the number of employed photo-mask process and insulating barrier, and take into account the aperture opening ratio of dot structure, this is the problem that industry needs to be resolved hurrily.
Summary of the invention
A purpose of the present invention is to provide a kind of dot structure and manufacture method thereof, manufacture method of the present invention only need be used six road photoetching and etching work procedures, compared with prior art, manufacturing process of the present invention can make the manufacturing cost of this dot structure and the decline that expends time in.
Another object of the present invention is to provide a kind of dot structure and manufacture method thereof, because dot structure of the present invention only comprises dielectric layers, each dot structure compared with prior art has higher light transmission.
For reaching above-mentioned purpose, one pixel structure process method disclosed in this invention comprises following steps: form patterning first conductive layer on substrate, this patterning first conductive layer comprises data wire and grid; On this substrate, form first insulating barrier, to cover this patterning first conductive layer; On this first insulating barrier above this grid, form patterned semiconductor layer; Form patterning second conductive layer, this patterning second conductive layer comprises source electrode, drain electrode and gate line, wherein this source electrode and this drain electrode lay respectively at the subregion on this patterned semiconductor layer, and this grid, this patterned semiconductor layer, this source electrode and this drain electrode constitute thin-film transistor structure on the control area of dot structure; Form pixel electrode, this pixel electrode electrically connects this drain electrode and covers the viewing area; Form second insulating barrier; This second insulating barrier of patterning and this first insulating barrier are with this data wire of expose portion, this source electrode, this gate line and this grid; And formation patterning the 3rd conductive layer, comprise data wire connection electrode, gate line connection electrode and common electrode, wherein this data wire connection electrode electrically connects this data wire and this source electrode, this gate line connection electrode electrically connects this gate line and this grid, and this common electrode is formed on this second insulating barrier of this viewing area.
In the above-mentioned manufacture method, the step that forms this patterning first conductive layer can comprise following steps: deposition first conductive layer on this substrate; On this first conductive layer, form the first patterning photoresist layer; Carry out etching work procedure, to form this data wire and this grid; And remove this first patterning photoresist layer.
In the above-mentioned manufacture method, the step that forms patterned semiconductor layer can be by the second patterning photoresist layer carries out patterning to semiconductor layer, to form this patterned semiconductor layer on this first insulating barrier above this grid.
In the above-mentioned manufacture method, the step that forms this patterning second conductive layer can comprise following steps: deposit second conductive layer; On this second conductive layer, form the 3rd patterning photoresist layer; Carry out etching work procedure, remove this second conductive layer of part, form this source electrode and this drain electrode and on this first insulating barrier above this grid of part, form this gate line with subregion in this patterned semiconductor layer; And remove the 3rd patterning photoresist layer.
In the above-mentioned manufacture method, the step that forms this pixel electrode can comprise following steps: the deposit transparent electrode layer; On this transparent electrode layer, form the 4th patterning photoresist layer; Carry out etching work procedure, should form this pixel electrode in the drain electrode on this first insulating barrier of this viewing area and partly; And remove the 4th patterning photoresist layer.
In the above-mentioned manufacture method, the step of this second insulating barrier of patterning and this first insulating barrier can comprise following steps: form the 5th patterning photoresist layer on this second insulating barrier; Carry out etching work procedure, remove this second insulating barrier of part and first insulating barrier, with formation expose this data wire first contact hole, form second contact hole that exposes this source electrode, form the 3rd contact hole that exposes this gate line, and form the 4th contact hole that exposes this grid; And remove the 5th patterning photoresist layer.
In the above-mentioned manufacture method, the step that forms this patterning the 3rd conductive layer can comprise following steps: deposit the 3rd conductive layer; On the 3rd conductive layer, form the 6th patterning photoresist layer; Carry out etching work procedure, to form this data wire connection electrode, this gate line connection electrode and this common electrode, wherein this data wire connection electrode is connected this data wire and this source electrode via this first contact hole with second contact hole, this gate line connection electrode is connected this gate line and this grid via the 3rd contact hole with the 4th contact hole, and this common electrode is formed on this second insulating barrier and is electrically insulated with this pixel electrode, and this common electrode has a plurality of slits; And remove the 6th patterning photoresist layer.
In the above-mentioned manufacture method, the 3rd conductive layer can be transparency conducting layer.
The present invention also discloses another kind of one pixel structure process method, comprises following steps: form patterning first conductive layer on substrate, this patterning first conductive layer comprises data wire and grid; On this substrate, form first insulating barrier, to cover this patterning first conductive layer; On this first insulating barrier above this grid, form patterned semiconductor layer; Form patterning second conductive layer, this patterning second conductive layer comprises source electrode, drain electrode and gate line, wherein this source electrode and this drain electrode lay respectively at the subregion on this patterned semiconductor layer, and this grid, this patterned semiconductor layer, this source electrode and this drain electrode constitute thin-film transistor structure in the control area of dot structure; Form common electrode, this common electrode covers the viewing area of dot structure; Form second insulating barrier; This second insulating barrier of patterning and this first insulating barrier are with this data wire of expose portion, this source electrode, this drain electrode, this gate line and this grid; And formation patterning the 3rd conductive layer, this patterning the 3rd conductive layer comprises data wire connection electrode, gate line connection electrode and pixel electrode, wherein this data wire connection electrode electrically connects this data wire and this source electrode, this gate line connection electrode electrically connects this gate line and this grid, and this pixel electrode is formed on this second insulating barrier of this viewing area and electrically connects this drain electrode.
In the above-mentioned manufacture method, the step that forms this patterning first conductive layer can comprise following steps: deposition first conductive layer on this substrate; On this first conductive layer, form the first patterning photoresist layer; Carry out etching work procedure, to form this data wire and this grid; And remove this first patterning photoresist layer.
In the above-mentioned manufacture method, the step that forms patterned semiconductor layer can be by the second patterning photoresist layer carries out patterning to semiconductor layer, to form this patterned semiconductor layer on this first insulating barrier above this grid.
In the above-mentioned manufacture method, the step that forms this patterning second conductive layer can comprise following steps: deposit second conductive layer; On this second conductive layer, form the 3rd patterning photoresist layer; Carry out etching work procedure, remove this second conductive layer of part, form this source electrode and this drain electrode and on this first insulating barrier above this grid of part, form this gate line with subregion in this patterned semiconductor layer; And remove the 3rd patterning photoresist layer.
In the above-mentioned manufacture method, the step that forms this common electrode can comprise following steps: the deposit transparent electrode layer; On this transparent electrode layer, form the 4th patterning photoresist layer; Carry out etching work procedure, on this first insulating barrier, to form this common electrode; And remove the 4th patterning photoresist layer.
In the above-mentioned manufacture method, the step of this second insulating barrier of patterning and this first insulating barrier can comprise following steps: form the 5th patterning photoresist layer on this second insulating barrier; Carry out etching work procedure, remove this second insulating barrier of part and first insulating barrier, with formation expose this data wire first contact hole, form second contact hole that exposes this source electrode, form the 3rd contact hole that exposes this gate line, form the 4th contact hole that exposes this grid, and form the 5th contact hole that exposes this leakage; And remove the 5th patterning photoresist layer.
In the above-mentioned manufacture method, the step that forms this patterning the 3rd conductive layer can comprise following steps: deposit the 3rd conductive layer; On the 3rd conductive layer, form the 6th patterning photoresist layer; Carry out etching work procedure, to form this data wire connection electrode, this gate line connection electrode and this pixel electrode, wherein this data wire connection electrode is connected this data wire and this source electrode via this first contact hole with second contact hole, this gate line connection electrode is connected this gate line and this grid via the 3rd contact hole with the 4th contact hole, and this pixel electrode is electrically connected at this drain electrode via the 5th contact hole, and this pixel electrode has a plurality of slits; And remove the 6th patterning photoresist layer.
In the above-mentioned manufacture method, the 3rd conductive layer can be transparency conducting layer.
The present invention also discloses a kind of dot structure, comprise gate line, data wire, thin-film transistor structure, data wire connection electrode, gate line connection electrode and display structure, wherein, this data wire and this gate line define pixel region, and this pixel region comprises control area and viewing area; This thin-film transistor structure is formed on this control area, and comprises grid, source electrode and drain electrode; This data wire connection electrode electrically connects this source electrode and this data wire, this gate line connection electrode electrically connects this grid and this gate line, this display structure is formed on this viewing area, and comprise the common electrode and the pixel electrode of overlapping each other and insulating, wherein this pixel electrode and this drain electrode electrically connect.
Above-mentioned dot structure also can comprise: insulating barrier is formed between this common electrode and this pixel electrode.
In the above-mentioned dot structure, this common electrode can be formed on this insulating barrier and have a plurality of slits.
In the above-mentioned dot structure, this common electrode, this data wire connection electrode and this gate line connection electrode can form in same operation simultaneously.
In the above-mentioned dot structure, this pixel electrode can be formed on this insulating barrier and have a plurality of slits.
In the above-mentioned dot structure, this thin-film transistor structure also can comprise: semiconductor layer, correspondence are formed at this grid top, and are connected respectively with this source electrode and this drain electrode.
The present invention can significantly save manufacturing cost and manufacturing time, and can further promote the light transmission of dot structure.
For above-mentioned purpose of the present invention, technical characterictic and advantage can be become apparent, hereinafter be elaborated with the preferred embodiment conjunction with figs..
Description of drawings
Figure 1A is the floor map of traditional dot structure;
Figure 1B is the generalized section of traditional dot structure;
Fig. 1 C～Fig. 1 I is the schematic diagram of traditional dot structure processing step;
Fig. 2 A is the floor map of the dot structure of first embodiment of the invention;
Fig. 2 B is the generalized section of the dot structure of first embodiment of the invention;
Fig. 2 C～Fig. 2 H is the schematic diagram of first embodiment of the invention processing step;
Fig. 3 A is the floor map of the dot structure of second embodiment of the invention;
Fig. 3 B is the generalized section of the dot structure of second embodiment of the invention; And
Fig. 3 C～Fig. 3 H is the schematic diagram of second embodiment of the invention processing step.
Wherein, description of reference numerals is as follows:
110 substrates, 111 control areas
113 connection pad zones, 112 viewing areas
120 the first metal layers, 121 grids
123 gate lines, 130 first insulating barriers
131 first contact holes, 140 semiconductor layers
150 second metal levels, 151 source electrodes
152 drain electrodes, 153 data wires
154 first grid polar curve connection pad layers, 160 second insulating barrier
171 common electrodes 180 the 3rd insulating barrier
181 second contact holes 182 the 3rd contact hole
190 the 3rd metal levels, 191 pixel electrodes
192 second grid line connection pad layers, 210 substrate
212 viewing areas, 211 control areas
220 patternings, first conductive layer, 221 grids
222 data wires, 230 first insulating barriers
240 semiconductor layers, 241 semiconductor channel layers
242 ohmic contact layers, 250 patternings, second conductive layer
252 drain electrodes of 251 source electrodes
253 gate lines, 261 pixel electrodes
270 second insulating barriers, 271 first contact holes
272 second contact holes 273 the 3rd contact hole
274 the 4th contact holes, 280 patternings the 3rd conductive layer
281 data wire connection electrode, 282 gate line connection electrode
283 common electrodes, 310 substrates
312 viewing areas, 311 control areas
320 patternings, first conductive layer, 321 grids
322 data wires, 330 first insulating barriers
340 semiconductor layers, 341 semiconductor channel layers
342 ohmic contact layers, 350 patternings, second conductive layer
352 drain electrodes of 351 source electrodes
353 gate lines, 361 common electrodes
370 second insulating barriers, 371 first contact holes
372 second contact holes 373 the 3rd contact hole
374 the 4th contact holes 375 the 5th contact hole
380 patternings the 3rd conductive layer, 381 data wire connection electrode
382 gate line connection electrode, 383 pixel electrodes
Embodiment
The invention belongs to a kind of plane internal conversion LCD (In Plane Switching LiquidCrystal Display, IPS-LCD) dot structure manufacture method, particularly wherein a kind of fringing field switching liquid crystal display (Fringe Field Switching Liquid Crystal Display, FFS-LCD) dot structure manufacture method, fringing field switching liquid crystal display of the present invention comprises a plurality of dot structures, and details are as follows for each one pixel structure process method.
The first embodiment of the present invention discloses a kind of one pixel structure process method, and its formed dot structure please refer to Fig. 2 A, Fig. 2 B, and wherein Fig. 2 A is the vertical view of dot structure, and Fig. 2 B then is the profile of dot structure.This dot structure comprises control area 211 and viewing area 212, the dot structure manufacture method of first embodiment of the invention, please refer to Fig. 2 C to Fig. 2 H, for convenience of description, wherein Fig. 2 B to Fig. 2 H draws along the A-A ' among Fig. 2 A, B-B ' and C-C ' hatching.
At first, utilize the first road photoetching and etching work procedure (PEP) to form patterning first conductive layer 220 on substrate 210, wherein patterning first conductive layer 220 comprises data wire 222 and grid 221, shown in Fig. 2 C, must explanation be that the grid 221 shown in Fig. 2 C is essentially same structure, and data wire 222 is essentially same structure, for the technology that clearly discloses present embodiment illustrates respectively, this point cooperates hatching of Fig. 2 A just can understand easily.In detail, the step of aforementioned formation patterning first conductive layer 220, be at first to deposit first conductive layer on substrate 210, form the first patterning photoresist layer (not shown) then on first conductive layer, and carry out etching work procedure, to form data wire 222 and the grid 221 shown in Fig. 2 C, remove this first patterning photoresist layer at last again.
Shown in Fig. 2 D, next can form first insulating barrier 230, cover aforesaid patterning first conductive layer 220, next just can implement second road photoetching and the etching work procedure of present embodiment, with the semiconductor layer 240 that forms patterning on first insulating barrier 230 of grid 221 tops, wherein semiconductor layer 240 can be described as active layer again, and it comprises semiconductor channel layer 241 and ohmic contact layer 242.In this second road photoetching and etching work procedure, can first depositing semiconductor layers 240, the N+ ion that reinjects, or the dopant deposition semiconductor material layer is on this semiconductor channel layer 241, to form ohmic contact layer 242 on semiconductor channel layer 241.Then, form the second patterning photoresist layer (not shown) on ohmic contact layer 242, carry out second etching work procedure again, to keep in fact semiconductor channel layer 241 and ohmic contact layer 242 corresponding to grid 221, remove this second patterning photoresist layer at last again, just can form aforementioned structure.
The 3rd road photoetching of present embodiment and etching work procedure are used to form patterning second conductive layer 250, patterning second conductive layer 250 comprises source electrode 251, drain electrode 252 and gate line 253, wherein source electrode 251 and drain electrode 252 subregions that lay respectively on the ohmic contact layer 242, and with grid 221, semiconductor layer 240, source electrode 251 and drain and 252 211 constitute thin-film transistor structures in the control area, shown in Fig. 2 E.In detail, form the method for patterning second conductive layer 250, comprise deposition second conductive layer earlier, form the 3rd patterning photoresist layer (figure does not show) again and on second conductive layer, carry out etching work procedure subsequently, remove part second conductive layer, to form source electrode 251 and to drain 252 in the subregion of ohmic contact layer 242, and form gate line 253 simultaneously, and last, remove the 3rd patterning photoresist layer again.
The 4th road photoetching of present embodiment and etching work procedure are used to form the pixel electrode 261 that electrically connects drain electrode 252, and wherein this pixel electrode 261 is covered on the viewing area 212 at least, shown in Fig. 2 F.More particularly, the method that forms pixel electrode 261 comprises deposition tin indium oxide (Indium Tin Oxide, ITO) transparent electrode layer of material, form the 4th patterning photoresist layer (not shown) then on transparent electrode layer, carry out etching work procedure subsequently, with form pixel electrode 261 on first insulating barrier 230 of viewing area 212 and part drain on 252 so that pixel electrode 261 electrically connects with drain electrode 252, at last, remove the 4th patterning photoresist layer again.
Next, deposit second insulating barrier 270 earlier, then with the 5th road photoetching and etching work procedure, patterning second insulating barrier 270 and first insulating barrier 230 are with expose portion data wire 222, source electrode 251, gate line 253 and grid 221, shown in Fig. 2 G.The method of patterning second insulating barrier 270 and first insulating barrier 230 comprises, form the 5th patterning photoresist layer (not shown) on second insulating barrier 270, carry out etching work procedure then, remove part second insulating barrier 270 and first insulating barrier 230, expose data wire 222 to form first contact hole 271, form second contact hole 272 and expose source electrode 251, form the 3rd contact hole 273 and expose gate line 253, and form the 4th contact hole 274 and expose grid 221, at last, remove the 5th patterning photoresist layer again.
The 6th road photoetching of present embodiment and etching work procedure are used to form patterning the 3rd conductive layer 280, wherein patterning the 3rd conductive layer 280 is a transparency conducting layer, shown in Fig. 2 H, patterning the 3rd conductive layer 280 can comprise data wire connection electrode 281, gate line connection electrode 282 and common electrode 283, wherein data wire connection electrode 281 electrically connects data wire 222 and source electrode 251 via first contact hole 271 and second contact hole 272, gate line connection electrode 282 electrically connects gate line 253 and grid 221 via the 3rd contact hole 273 and the 4th contact hole 274, common electrode 283 then is formed on second insulating barrier 270 of viewing area 212, common electrode 283 is characterised in that: be electrically insulated with pixel electrode 261, and have a plurality of slits, to form the fringing field switching construction.In detail, the method that forms patterning the 3rd conductive layer 280 comprises, the 3rd conductive layer of elder generation's deposit transparent, form the 6th patterning photoresist layer (not shown) then on the 3rd conductive layer, carry out etching work procedure again, to form data wire connection electrode 281, gate line connection electrode 282 and to have the common electrode 283 of slit, remove the 6th patterning photoresist layer at last again.
By above-mentioned operation, the formed dot structure of present embodiment can form thin-film transistor structure and forming display structure on viewing area 212 in the pixel region that gate line 253 and data wire 222 are defined on the control area 211; Wherein, display structure comprises overlaps and each other by second insulating barrier 270 common electrode 283 and pixel electrode 261 insulated from each other, wherein pixel electrode 261 electrically connects with the drain electrode 252 of thin-film transistor structure, and common electrode 283 has a plurality of slits; In addition, utilize data wire connection electrode 281 to electrically connect the source electrode 251 and data wire 222 of thin-film transistor structure, utilize gate line connection electrode 282 to electrically connect grid 221 and gate line 253, wherein common electrode 283, data wire connection electrode 281 and gate line connection electrode 282 can form in one procedure simultaneously.As aforementioned, the dot structure of present embodiment can be finished with six road photoetching and etching work procedure.
Disclosed method of the second embodiment of the present invention and formed dot structure, please refer to Fig. 3 A, 3B, wherein this dot structure comprises control area 311 and viewing area 312, the disclosed one pixel structure process method of present embodiment please refer to Fig. 3 C to Fig. 3 H, for convenience of description, wherein Fig. 3 B to Fig. 3 H draws along the A-A ' among Fig. 3 A, B-B ' and C-C ' hatching.
Shown in Fig. 3 C, first road photoetching of present embodiment and etching work procedure are used to form patterning first conductive layer 320 on substrate 310, wherein patterning first conductive layer 320 comprises data wire 322 and grid 321, it should be noted that, grid 321 shown in Fig. 3 C is essentially same structure, and data wire 322 is essentially same structure, and they are to illustrate respectively in order clearly to disclose the technology of present embodiment, cooperate the hatching of Fig. 3 A just can understand easily.
Forming the method for patterning first conductive layer 320 on substrate 310 comprises, deposition first conductive layer is on substrate 310 earlier, form the first patterning photoresist layer (figure does not show) again on first conductive layer, after carrying out etching work procedure, form grid 321 and data wire 322, remove the first patterning photoresist layer at last again.
Next, shown in Fig. 3 D, deposition first insulating barrier 330 is on substrate 310, with overlay patternization first conductive layer 320 earlier.Then, carry out second road photoetching and the etching work procedure of present embodiment, with the semiconductor layer 340 that forms patterning on first insulating barrier 330 of grid 321 tops, as previously mentioned, semiconductor layer 340 can be described as active layer again, comprises semiconductor channel layer 341 and ohmic contact layer 342.In detail, the method that forms the semiconductor layer 340 of patterning can be: the deposited semiconductor material layer, inject the N+ ion, or the dopant deposition semiconductor material layer is on semiconductor material layer, on semiconductor material layer, to form ohmic contact layer 342, and then form the second patterning photoresist layer (not shown) on ohmic contact layer 342, and carry out second etching work procedure, to keep, remove the second patterning photoresist layer at last more in fact corresponding to the semiconductor channel layer 341 and the ohmic contact layer 342 of grid 321.
Shown in Fig. 3 E, the 3rd road photoetching of present embodiment and etching work procedure are used to form patterning second conductive layer 350, patterning second conductive layer 350 comprises source electrode 351, drain electrode 352 and gate line 353, wherein source electrode 351 and drain electrode 352 subregions that lay respectively on the ohmic contact layer 342, and 311 constitute thin-film transistor structures in the control area with grid 321 and semiconductor layer 340.In detail, the method that forms patterning second conductive layer 350 comprises: deposit second conductive layer earlier, form the 3rd patterning photoresist layer (not shown) again on second conductive layer, carry out etching work procedure subsequently, remove part second conductive layer, forming source electrode 351 and to drain 352, and form gate line 353 simultaneously, remove the 3rd patterning photoresist layer at last again in the subregion of semiconductor layer 340.
The common electrode 361 that the 4th road photoetching of present embodiment and etching work procedure are used to form patterning, wherein common electrode 361 is covered on the viewing area 312, shown in Fig. 3 F.The method that forms common electrode 361 comprises the transparent electrode layer of deposition tin indium oxide material, form the 4th patterning photoresist layer (not shown) then on transparent electrode layer, and carry out etching work procedure, on first insulating barrier 330 of viewing area 312, remove the 4th patterning photoresist layer with the common electrode 361 that forms patterning at last again.
Next, deposit second insulating barrier 370, then with the 5th road photoetching and etching work procedure, patterning second insulating barrier 370 and first insulating barrier 330 are with expose portion data wire 322, source electrode 351, drain electrode 352, gate line 353 and grid 321, shown in Fig. 3 G.In detail, the method of patterning second insulating barrier 370 and first insulating barrier 330 comprises, form earlier the 5th patterning photoresist layer (figure does not show) after on second insulating barrier 370, carry out etching work procedure, remove part second insulating barrier 370 and first insulating barrier 330, expose first contact hole 371 of data wire 322 with formation, expose second contact hole 372 of source electrode 351, expose the 3rd contact hole 373 of gate line 353, expose the 4th contact hole 374 of grid 321, and expose drain electrode 352 the 5th contact hole 375, at last, remove the 5th patterning photoresist layer again.
Shown in Fig. 3 H, the 6th road photoetching of present embodiment and etching work procedure are used to form patterning the 3rd conductive layer 380, wherein patterning the 3rd conductive layer 380 is a transparency conducting layer, can comprise data wire connection electrode 381, gate line connection electrode 382 and pixel electrode 383, wherein data wire connection electrode 381 electrically connects data wire 322 and source electrode 351, gate line connection electrode 382 electrically connects gate line 353 and grid 321, and pixel electrode 383 is characterised in that: be formed on second insulating barrier 370 of viewing area 312, electrically connect drain electrode 352 and be electrically insulated, and have a plurality of slits with common electrode 361.
More particularly, the method that forms patterning the 3rd conductive layer 380 comprises, the 3rd conductive layer of elder generation's deposit transparent, form the 6th patterning photoresist layer (not shown) then on the 3rd conductive layer 380, carry out etching work procedure subsequently, to form data wire connection electrode 381 respectively, gate line connection electrode 382 and pixel electrode 383 and pixel electrode 383, wherein data wire connection electrode 381 electrically connects data wire 322 and source electrode 351 via first contact hole 371 and second contact hole 372, gate line connection electrode 382 electrically connects gate line 353 and grid 321 via the 3rd contact hole 373 and the 4th contact hole 374, and pixel electrode 383 is formed on second insulating barrier 370 of viewing area 312, and via the 5th contact hole 375 be electrically connected at the drain electrode 352, wherein pixel electrode 383 is by second insulating barrier 370 and common electrode 361 insulation, at last, remove the 6th patterning photoresist layer again.
By above-mentioned operation, the formed dot structure of present embodiment has different slightly with the dot structure of first embodiment.The pixel electrode 383 of present embodiment is formed on second insulating barrier 370 and has a plurality of slits, and electrically connects with the drain electrode 352 of thin-film transistor structure, and common electrode 361 then forms second insulating barrier 370 times.Similarly, common electrode 361, data wire connection electrode 381 and gate line connection electrode 382 just can form in one procedure simultaneously, and as aforementioned, the dot structure of present embodiment can be finished with six road photoetching and etching work procedure.
By aforementioned disclosed content, the present invention is applied to the dot structure of fringing field switching liquid crystal display, need seven road photoetching to compare with prior art with etching work procedure, the present invention only needs six road photoetching and etching work procedures, so can significantly save manufacturing cost and manufacturing time, and this dot structure only includes two layer insulatings, compares with the formed dot structure that includes three-layer insulated layer of prior art manufacture method, can further promote the light transmission of dot structure.
The above embodiments only are used for exemplifying embodiment of the present invention, and explain technical characterictic of the present invention, are not to be used for limiting protection scope of the present invention.Any those skilled in the art can unlabored change or the arrangement of the identity property scope that all belongs to the present invention and advocated, and the scope of the present invention should be as the criterion with claim.
Claims (22)
1. one pixel structure process method, this dot structure comprises control area and viewing area, and the method includes the steps of:
Form patterning first conductive layer on substrate, this patterning first conductive layer comprises data wire and grid;
On this substrate, form first insulating barrier, to cover this patterning first conductive layer;
On this first insulating barrier above this grid, form patterned semiconductor layer;
Form patterning second conductive layer, this patterning second conductive layer comprises source electrode, drain electrode and gate line, wherein this source electrode and this drain electrode lay respectively at the subregion on this patterned semiconductor layer, and this grid, this patterned semiconductor layer, this source electrode and this drain electrode constitute thin-film transistor structure in this control area;
Form pixel electrode, it electrically connects this drain electrode, and covers this viewing area;
Form second insulating barrier;
This second insulating barrier of patterning and this first insulating barrier are with this data wire of expose portion, this source electrode, this gate line and this grid; And
Form patterning the 3rd conductive layer, it comprises data wire connection electrode, gate line connection electrode and common electrode, wherein this data wire connection electrode electrically connects this data wire and this source electrode, this gate line connection electrode electrically connects this gate line and this grid, and this common electrode is formed on this second insulating barrier of this viewing area.
2. the method for claim 1, the step that wherein forms this patterning first conductive layer comprises following steps:
Deposition first conductive layer on this substrate;
On this first conductive layer, form the first patterning photoresist layer;
Carry out etching work procedure, to form this data wire and this grid; And
Remove this first patterning photoresist layer.
3. the method for claim 1, the step that wherein forms patterned semiconductor layer is by the second patterning photoresist layer semiconductor layer to be carried out patterning, to form this patterned semiconductor layer on this first insulating barrier above this grid.
4. the method for claim 1, the step that wherein forms this patterning second conductive layer comprises following steps:
Deposit second conductive layer;
On this second conductive layer, form the 3rd patterning photoresist layer;
Carry out etching work procedure, remove this second conductive layer of part, form this source electrode and this drain electrode, and on this first insulating barrier above this grid of part, form this gate line with subregion in this patterned semiconductor layer; And
Remove the 3rd patterning photoresist layer.
5. the method for claim 1, the step that wherein forms this pixel electrode comprises following steps:
The deposit transparent electrode layer;
On this transparent electrode layer, form the 4th patterning photoresist layer;
Carry out etching work procedure, should form this pixel electrode in the drain electrode on this first insulating barrier of this viewing area and partly; And
Remove the 4th patterning photoresist layer.
6. the method for claim 1, wherein the step of this second insulating barrier of patterning and this first insulating barrier comprises following steps:
On this second insulating barrier, form the 5th patterning photoresist layer;
Carry out etching work procedure, remove this second insulating barrier of part and first insulating barrier, with formation expose this data wire first contact hole, form second contact hole that exposes this source electrode, form the 3rd contact hole that exposes this gate line, and form the 4th contact hole that exposes this grid; And
Remove the 5th patterning photoresist layer.
7. method as claimed in claim 6, the step that wherein forms this patterning the 3rd conductive layer comprises following steps:
Deposit the 3rd conductive layer;
On the 3rd conductive layer, form the 6th patterning photoresist layer;
Carry out etching work procedure, to form this data wire connection electrode, this gate line connection electrode and this common electrode, wherein this data wire connection electrode is connected this data wire and this source electrode via this first contact hole with second contact hole, this gate line connection electrode is connected this gate line and this grid via the 3rd contact hole with the 4th contact hole, and this common electrode is formed on this second insulating barrier and is electrically insulated with this pixel electrode, and this common electrode has a plurality of slits; And
Remove the 6th patterning photoresist layer.
8. the method for claim 1, wherein the 3rd conductive layer is a transparency conducting layer.
9. one pixel structure process method, this dot structure comprises control area and viewing area, and the method includes the steps of:
Form patterning first conductive layer on substrate, this patterning first conductive layer comprises data wire and grid;
On this substrate, form first insulating barrier, to cover this patterning first conductive layer;
On this first insulating barrier above this grid, form patterned semiconductor layer;
Form patterning second conductive layer, this patterning second conductive layer comprises source electrode, drain electrode and gate line, wherein this source electrode and this drain electrode lay respectively at the subregion on this patterned semiconductor layer, and this grid, this patterned semiconductor layer, this source electrode and this drain electrode constitute thin-film transistor structure in this control area;
Form common electrode, it covers this viewing area;
Form second insulating barrier;
This second insulating barrier of patterning and this first insulating barrier are with this data wire of expose portion, this source electrode, this drain electrode, this gate line and this grid; And
Form patterning the 3rd conductive layer, it comprises data wire connection electrode, gate line connection electrode and pixel electrode, wherein this data wire connection electrode electrically connects this data wire and this source electrode, this gate line connection electrode electrically connects this gate line and this grid, and this pixel electrode is formed on this second insulating barrier of this viewing area and electrically connects this drain electrode.
10. method as claimed in claim 9, the step that wherein forms this patterning first conductive layer comprises following steps:
Deposition first conductive layer on this substrate;
On this first conductive layer, form the first patterning photoresist layer;
Carry out etching work procedure, to form this data wire and this grid; And
Remove this first patterning photoresist layer.
11. method as claimed in claim 9, the step that wherein forms patterned semiconductor layer are by the second patterning photoresist layer semiconductor layer to be carried out patterning, to form this patterned semiconductor layer on this first insulating barrier above this grid.
12. method as claimed in claim 9, the step that wherein forms this patterning second conductive layer comprises following steps:
Deposit second conductive layer;
On this second conductive layer, form the 3rd patterning photoresist layer;
Carry out etching work procedure, remove this second conductive layer of part, form this source electrode and this drain electrode, and on this first insulating barrier above this grid of part, form this gate line with subregion in this patterned semiconductor layer; And
Remove the 3rd patterning photoresist layer.
13. method as claimed in claim 9, the step that wherein forms this common electrode comprises following steps:
The deposit transparent electrode layer;
On this transparent electrode layer, form the 4th patterning photoresist layer;
Carry out etching work procedure, on this first insulating barrier, to form this common electrode; And
Remove the 4th patterning photoresist layer.
14. method as claimed in claim 9, wherein the step of this second insulating barrier of patterning and this first insulating barrier comprises following steps:
On this second insulating barrier, form the 5th patterning photoresist layer;
Carry out etching work procedure, remove this second insulating barrier of part and first insulating barrier, with formation expose this data wire first contact hole, form second contact hole that exposes this source electrode, form the 3rd contact hole that exposes this gate line, form the 4th contact hole that exposes this grid, and form the 5th contact hole that exposes this drain electrode; And
Remove the 5th patterning photoresist layer.
15. method as claimed in claim 14, the step that wherein forms this patterning the 3rd conductive layer comprises following steps:
Deposit the 3rd conductive layer;
On the 3rd conductive layer, form the 6th patterning photoresist layer;
Carry out etching work procedure, to form this data wire connection electrode, this gate line connection electrode and this pixel electrode, wherein this data wire connection electrode is connected this data wire and this source electrode via this first contact hole with second contact hole, this gate line connection electrode is connected this gate line and this grid via the 3rd contact hole with the 4th contact hole, and this pixel electrode is electrically connected at this drain electrode via the 5th contact hole, and this pixel electrode has a plurality of slits; And
Remove the 6th patterning photoresist layer.
16. method as claimed in claim 9, wherein the 3rd conductive layer is a transparency conducting layer.
17. a dot structure comprises:
Gate line;
Data wire defines pixel region with this gate line, and this pixel region comprises control area and viewing area;
Thin-film transistor structure is formed on this control area, and wherein this thin-film transistor structure comprises grid, source electrode and drain electrode;
The data wire connection electrode electrically connects this source electrode and this data wire;
The gate line connection electrode electrically connects this grid and this gate line;
First insulating barrier is formed on this control area and the viewing area, covers this data wire and this grid; And
Display structure, be formed on this first insulating barrier and be positioned on this viewing area, this display structure comprises the common electrode and the pixel electrode of overlapping each other and being insulated by second insulating barrier, wherein this second insulating barrier is formed between this common electrode and this pixel electrode, and this pixel electrode and this drain electrode electrically connect.
18. dot structure as claimed in claim 17, wherein this common electrode is formed on this second insulating barrier and has a plurality of slits.
19. dot structure as claimed in claim 18, wherein this common electrode, this data wire connection electrode and this gate line connection electrode form in same operation simultaneously.
20. dot structure as claimed in claim 17, wherein this pixel electrode is formed on this second insulating barrier and has a plurality of slits.
21. dot structure as claimed in claim 20, wherein this pixel electrode, this data wire connection electrode and this gate line connection electrode form in same operation simultaneously.
22. dot structure as claimed in claim 17, wherein this thin-film transistor structure also comprises: semiconductor layer, correspondence are formed at this grid top, and are connected respectively with this source electrode and this drain electrode.
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| CN200710166952A CN100590854C (en) | 2007-11-08 | 2007-11-08 | Pixel structure and its making method |
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| CN200710166952A CN100590854C (en) | 2007-11-08 | 2007-11-08 | Pixel structure and its making method |
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| CN100590854C true CN100590854C (en) | 2010-02-17 |
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| CN101261962B (en) * | 2008-04-24 | 2010-08-18 | 友达光电股份有限公司 | Active part array base board and its making method |
| CN102279493B (en) * | 2010-06-13 | 2015-09-23 | 上海天马微电子有限公司 | Pixel cell and liquid crystal indicator |
| CN103021944A (en) * | 2012-12-21 | 2013-04-03 | 北京京东方光电科技有限公司 | TFT (thin-film transistor) array substrate, manufacturing method of TFT array substrate, and display device with TFT array substrate |
| CN103779356A (en) * | 2014-01-21 | 2014-05-07 | 北京京东方光电科技有限公司 | Display panel mother board and preparation method thereof |
| CN105161455A (en) * | 2015-07-31 | 2015-12-16 | 深圳市华星光电技术有限公司 | FFS array substrate manufacturing method thereof, and display device |
| CN106353937B (en) * | 2016-11-28 | 2020-11-24 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate and display device |
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