WO2020024561A1 - Thin film transistor and preparation method therefor and array substrate - Google Patents

Thin film transistor and preparation method therefor and array substrate Download PDF

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Publication number
WO2020024561A1
WO2020024561A1 PCT/CN2019/070996 CN2019070996W WO2020024561A1 WO 2020024561 A1 WO2020024561 A1 WO 2020024561A1 CN 2019070996 W CN2019070996 W CN 2019070996W WO 2020024561 A1 WO2020024561 A1 WO 2020024561A1
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layer
electrode
metal layer
metal
active
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PCT/CN2019/070996
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French (fr)
Chinese (zh)
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谢华飞
陈书志
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020024561A1 publication Critical patent/WO2020024561A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors

Definitions

  • the present invention relates to the technical field of array substrate manufacturing, and in particular, to a thin film transistor, a method for manufacturing the same, and an array substrate.
  • TFT AMLCD Thin film transistor active matrix liquid crystal displays
  • the TFT electrode in order to improve the contact performance of the TFT electrode, the TFT electrode generally adopts a multilayer metal structure, as shown in FIG. 1, where the TFT electrode includes a first metal layer 4 and a second metal layer 6, The first metal layer 4 is in contact with the active layer 5.
  • a first metal material layer and a second metal material layer with good adhesion are first deposited on the active layer 5 and then etched through a photolithography process. The dissimilar metals are in the same etching solution and are on each other.
  • the present invention provides a thin film transistor, a method for manufacturing the same, and an array substrate, which can improve the contact performance between the active layer and the second metal layer, avoid the occurrence of chamfers, and improve the electrical properties of the thin film transistor. performance.
  • a specific technical solution proposed by the present invention is: a thin film transistor, which includes a substrate, a gate, a gate insulating layer, a first metal layer, an active layer, a second metal layer, and a passivation layer,
  • the gate is disposed on the substrate, the gate insulating layer covers the gate, and the first metal layer includes a gap disposed on the gate.
  • a first electrode and a second electrode on the gate insulation layer, the second metal layer includes a source electrode and a drain electrode spaced apart, and one end of the active layer is sandwiched between the first electrode and the source electrode In between, the other end of the active layer is sandwiched between the second electrode and the drain, and the passivation layer covers the exposed surface of the source, drain, and active layer.
  • the source electrode is in contact with the first electrode
  • the drain electrode is in contact with the second electrode
  • the adhesion between the first metal layer and the gate insulation layer is greater than the adhesion between the second metal layer and the gate insulation.
  • the material of the second metal layer is copper.
  • a material of the first metal layer is selected from one of molybdenum, chromium, and titanium.
  • the present invention also provides an array substrate, the array substrate including the thin film transistor according to any one of the above.
  • the present invention also provides a method for manufacturing a thin film transistor, the method includes the steps:
  • first metal layer on the gate insulating layer, the first metal layer including a first electrode and a second electrode disposed on the gate insulating layer at intervals;
  • An active layer and a second metal layer are formed on the first metal layer, the second metal layer includes a source electrode and a drain electrode spaced apart, and one end of the active layer is sandwiched between the first metal layer and the first metal layer. Between an electrode and the source, and the other end of the active layer is sandwiched between the second electrode and the drain;
  • an active layer on the first metal layer, and the second metal layer specifically include:
  • forming an active layer on the first metal layer, and the second metal layer includes:
  • the second metal layer includes source and drain electrodes spaced apart, and the active layer One end is sandwiched between the first electrode and the source electrode, and the other end of the active layer is sandwiched between the second electrode and the drain electrode.
  • the thin film transistor provided by the present invention includes an active layer, a source, a drain, and a first electrode and a second electrode disposed at intervals. One end of the active layer is sandwiched between the first electrode and the source. Between the electrodes, the other end of the active layer is sandwiched between the second electrode and the drain. By sandwiching the active layer between the first metal layer and the second metal layer, it is improved. Contact performance between the active layer and the second metal layer.
  • the first metal layer and the second metal layer are formed by two patterning processes, thereby avoiding the occurrence of chamfers and improving the electrical performance of the thin film transistor. Summary of invention
  • FIG. 1 is a schematic view of a structure in which a chamfered corner occurs during the preparation of an existing thin film transistor
  • FIG. 2 is a schematic structural diagram of an array substrate in Embodiment 1 of the present invention.
  • 3a-3f are flowcharts of a method for manufacturing a thin film transistor in Example 1;
  • 6a-6d are flowcharts of the preparation of an active layer in Example 1;
  • Embodiment 8 is a schematic structural diagram of an array substrate in Embodiment 2 of the present invention.
  • 9a-9j are flowcharts of a method for manufacturing a thin film transistor in Embodiment 2.
  • the present invention provides a thin film transistor, which includes a substrate, a gate, a gate insulating layer, a first metal layer, an active layer, a second metal layer, and a passivation layer, and the gate is disposed on the substrate.
  • a gate insulating layer covers the gate.
  • the first metal layer includes first and second electrodes spaced apart from the gate insulating layer.
  • the second metal layer includes source and drain electrodes spaced apart.
  • One end of the active layer Sandwiched between the first electrode and the source, The other end of the active layer is sandwiched between the second electrode and the drain, and the passivation layer covers the exposed surfaces of the source, drain, and active layer.
  • the present invention also provides a method for manufacturing a thin film transistor.
  • the method includes the following steps:
  • first metal layer on the gate insulating layer, the first metal layer including a first electrode and a second electrode disposed on the gate insulating layer at intervals;
  • the second metal layer including a source electrode and a drain electrode spaced apart, and one end of the active layer is sandwiched between the first electrode and the source electrode, The other end of the active layer is sandwiched between the second electrode and the drain;
  • a passivation layer is deposited, and the passivation layer covers the exposed surfaces of the source, drain, and active layers.
  • the thin film transistor provided by the present invention includes an active layer, a source, a drain, and a first electrode and a second electrode disposed at intervals. One end of the active layer is sandwiched between the first electrode and the source. Between the electrodes, the other end of the active layer is sandwiched between the second electrode and the drain. By sandwiching the active layer between the first metal layer and the second metal layer, it is improved. Contact performance between the active layer and the second metal layer.
  • the first metal layer and the second metal layer are formed through two patterning processes, thereby avoiding the chamfering angle through one patterning process and improving the electrical performance of the thin film transistor.
  • the array substrate in this embodiment includes a plurality of thin film transistors 10, and the plurality of thin film transistors are arranged in an array.
  • the thin film transistor 10 includes a substrate 1, a gate 2, a gate insulating layer 3, a first metal layer 4, an active layer 5, a second metal layer 6, and a passivation layer 7.
  • the gate electrode 2 is disposed on the substrate 1.
  • the gate insulating layer 3 covers the gate electrode 2.
  • the first metal layer 4 includes a first electrode 41 and a second electrode 42 spaced from the gate insulating layer 3.
  • the second metal layer 6 includes The source electrode 61 and the drain electrode 62 are arranged at intervals.
  • the source electrode 61 is located on the first electrode 41 and is in contact with the first electrode 41
  • the drain electrode 62 is located on the second electrode 42 and is in contact with the second electrode 42.
  • the active layer 5 includes The source contact terminal 51, the back channel portion 52, and the drain contact terminal 53, the source contact terminal 51 is sandwiched between the first electrode 41 and the source electrode 61 and covers part of the first electrode 41, and the drain contact terminal 53 is clamped.
  • the back channel region 52 is located between the first electrode 41 and the second electrode 42 and corresponds to the gate 2.
  • the passivation layer 7 covers the source 61, the drain 62, and the exposed active layer 5. surface.
  • the adhesion of the first electrode 41 and the second electrode 42 to the gate insulating layer 3 is greater than the adhesion of the source 61 and the drain electrode 62 to the gate insulating layer 3.
  • the material of the gate insulating layer 3 is an insulating material.
  • the material of the second metal layer 6 is copper. Because copper has excellent properties such as low resistance and high conductivity, it has become a mainstream electrode conductive metal material. However, copper and the gate The adhesion between the insulating layers is poor.
  • a first metal layer 4 is provided between the second metal layer 6 and the gate insulating layer 3, the second metal layer 6 is in contact with the first metal layer 4, and the first metal layer 4
  • the material is selected from one of molybdenum, chromium, and titanium.
  • the first metal layer 4 and the gate insulating layer 3 have good adhesion, thereby reducing the resistivity of the metal electrode and improving the thermal stability of the metal electrode. And adhesion.
  • the metal electrode in this embodiment refers to a source electrode 61 or a drain electrode 62.
  • the source contact terminal 51 is provided between the first electrode 41 and the source electrode 61, and the drain contact terminal 53 is sandwiched between the second electrode 42 and the drain electrode 62.
  • 5 is interposed between the first metal layer 4 and the second metal layer 6 to improve the contact performance between the active layer 5 and the second metal layer 6.
  • the array substrate in this embodiment further includes a pixel electrode 8, and the pixel electrode 8 is connected to the drain electrode 62 through a via hole.
  • this embodiment further provides a first embodiment of the above-mentioned method for manufacturing a thin film transistor.
  • the method includes the following steps:
  • S1 a substrate 1 is provided, as shown in FIG. 3a;
  • S2, 4 form a gate 2 and a gate insulating layer 3 on a substrate 1, and the gate insulating layer 3 covers the gate 2, as shown in FIG. 3b;
  • S3 and 4 form a first metal layer 4 on the gate insulating layer 3, and the first metal layer 4 includes a gate insulating layer disposed at intervals.
  • S4, 4 form an active layer 5 on the first metal layer 4.
  • the active layer 5 includes a source contact terminal 51 and a back channel portion 52.
  • the drain contact end 53, the source contact end 51 is in contact with the first electrode 41 and covers part of the first electrode 41, the drain contact end 53 is in contact with the second electrode 42 and covers part of the second electrode 42, and the back channel region 52 Located between the first electrode 41 and the second electrode 42 and corresponding to the gate 2, as shown in FIG. 3d;
  • a second metal layer 6 is formed on the first metal layer 4 and the active layer 5.
  • the second metal layer 6 includes a source electrode 61 and a drain electrode 62 disposed at intervals.
  • the source electrode 61 is located on the first electrode 41.
  • the drain 62 is located on the second electrode 42, the source contact 51 is sandwiched between the first electrode 41 and the source 61, and the drain contact 53 is sandwiched between the second electrode 42 and the drain 62.
  • the electrode 61 is in contact with the first electrode 41, and the drain 62 is in contact with the second electrode 42, as shown in FIG. 3e. Do not;
  • a passivation layer 7 is deposited, and the passivation layer 7 covers the exposed surfaces of the source 61, the drain 62, and the active layer 5, as shown in FIG. 3fB ) f.
  • the first metal layer 4 and the second metal layer 6 are obtained through two patterning processes, so that the formation of the first metal layer 4 and the second metal layer 6 due to etching can be avoided.
  • the different etching rates of different metal materials by the liquid cause local corrosion of the first metal layer 4 and the second metal layer 6 and a chamfer phenomenon, which leads to subsequent failure of the passivation layer and electrical instability of the thin film transistor. Improve production yield.
  • step S2 includes:
  • a gate insulating layer 3 is deposited on the substrate 1 and the gate 2.
  • the gate insulating layer 3 covers the gate 2, as shown in FIG. 4e.
  • step S3 includes:
  • the first metal material layer 40 not covered by the second photoresist area is removed by an etching process to form a first metal layer 4.
  • the first metal layer 4 includes first spacers disposed on the gate insulating layer 3.
  • the electrode 41 and the second electrode 42 are shown in FIG. 5c;
  • step S4 includes:
  • S41 An active material layer 50 and a third photoresist layer 102 are sequentially deposited on the first metal layer 4, as shown in FIG. 6a.
  • S42 Expose the third photoresist layer 102 through a third photomask to pattern the third photoresist layer to form a third photoresist region, as shown in FIG. 6b;
  • the active layer 5 includes a source contact terminal 51, a back channel portion 52, and a drain contact terminal 53, the source contact terminal 51 is in contact with the first electrode 41 and covers a part of the first electrode 41, and the drain contact terminal 53 and the first
  • the two electrodes 42 contact and cover a part of the second electrode 42
  • the back channel region 52 is located between the first electrode 41 and the second electrode 42 and corresponds to the gate electrode 2, as shown in FIG. 6c;
  • step S5 includes:
  • the second metal material layer 60 that is not covered by the fourth photoresist area is removed by an etching process to form a second metal layer 6, and the second metal layer 6 includes a source electrode 61 and a drain electrode 62 spaced apart.
  • the source contact end 51 is sandwiched between the first electrode 41 and the source electrode 61
  • the drain contact end 53 is sandwiched between the second electrode 42 and the drain electrode 62
  • the source electrode 61 is in contact with the first electrode 41
  • the drain electrode 62 is in contact with the second electrode 42, as shown in FIG. 7c;
  • the passivation layer needs to be patterned through a fifth photomask process, a via hole is formed in the passivation layer, and then a pixel is deposited on the passivation layer.
  • the electrode material layer the pixel electrode material layer is patterned through a sixth photomask process to obtain the pixel electrode 8.
  • the entire array substrate preparation process requires six photomasks.
  • this embodiment is different from Embodiment 1 in that the source electrode 61 is not in contact with the first electrode 41, and the drain electrode 62 is not in contact with the second electrode 42.
  • the manufacturing method of this embodiment uses a half-tone mask process, and the manufacturing method includes steps:
  • a substrate 1 is provided, as shown in FIG. 9a;
  • a gate 2 and a gate insulating layer 3 are formed on the substrate 1, and the gate insulating layer 3 covers the gate 2, as shown in FIG. 9b;
  • a first metal layer 4 is formed on the gate insulating layer 3, and the first metal layer 4 includes a first electrode 41 and a second electrode 42 spaced from the gate insulating layer 3, as shown in FIG. 9c;
  • S5. Perform grayscale exposure on the third photoresist layer 70 through the third photomask to pattern the third photoresist layer to form a third photoresist region.
  • the third photoresist region includes a middle portion and is located in the middle. The thickness of the side portion on both sides of the portion is smaller than the thickness of the side portion, as shown in FIG. 9e;
  • the active layer 5 includes a source.
  • the third photoresist region is subjected to ashing treatment to remove the middle portion and reduce the thickness of the side portions, and to retain portions of the side portions, as shown in FIG. 9g;
  • the second metal material layer 60 that is not partially covered by the side is removed by an etching process to form a second metal layer 6.
  • the second metal layer 6 includes a source electrode 61 and a drain electrode 62 that are disposed at intervals.
  • the contact end 51 is sandwiched between the first electrode 41 and the source electrode 61, and the drain contact end 53 is sandwiched between the second electrode 42 and the drain electrode 62, as shown in FIG. 9h;
  • a passivation layer 7 is deposited, and the passivation layer 7 covers the exposed surfaces of the source 61, the drain 62, and the active layer 5, as shown in FIG. 9j.
  • Steps S1-S3 in this embodiment are the same as those in Embodiment 1, and details are not described herein again.
  • the passivation layer needs to be patterned through a fourth photomask process, a via hole is formed in the passivation layer, and then a pixel electrode material layer is deposited on the passivation layer.
  • the pixel electrode material layer is patterned through a fifth photomask process to obtain the pixel electrode 8.
  • the entire array substrate preparation process requires five photomasks. Therefore, in this embodiment, in the method for manufacturing a thin film transistor, the active layer 5 and the second metal layer 6 are formed on the first metal layer 4 through a half-tone mask process. Compared with the first embodiment, In order to save a photomask, thereby simplifying the manufacturing process and reducing the manufacturing cost.

Abstract

Disclosed are a thin film transistor and a preparation method therefor and an array substrate. The thin film transistor (10) comprises a substrate (1), a grid electrode (2), a grid insulating layer (3), a first metal layer (4), an active layer (5), a second metal layer (6) and a passivation layer (7); the grid electrode (2) is disposed on the substrate (1); the grid insulating layer (3) covers the grid electrode (2); the first metal layer (4) comprises a first electrode (41) and a second electrode (42), which are disposed on the grid insulating layer (3) at an interval; the second metal layer (6) comprises a source electrode (61) and a drain electrode (62), which are disposed at an interval; one end of the active layer (5) is sandwiched between the first electrode (41) and the source electrode (61); the other end of the active layer (5) is sandwiched between the second electrode (42) and the drain electrode (62); the passivation layer (7) covers on the exposed surface of the source electrode (61), the drain electrode (62) and the active layer (5); and the active layer (5) is sandwiched between the first metal layer (4) and the second metal layer (6) to improve the contact performance of the active layer (5) and the second metal layer (6). According to the preparation method, the first metal layer (4) and the second metal layer (6) are formed by twice compositional processes, and chamfering is thus avoided.

Description

薄膜晶体管及其制备方法、 阵列基板  Thin film transistor, preparation method thereof, and array substrate
[0001] 常规技术领域 [0001] General Technical Field
[0002] 本发明涉及阵列基板制造技术领域， 尤其涉及一种薄膜晶体管及其制备方法、 阵列基板。  [0002] The present invention relates to the technical field of array substrate manufacturing, and in particular, to a thin film transistor, a method for manufacturing the same, and an array substrate.
背景技术  Background technique
[0003] 薄膜晶体管有源矩阵液晶显示器 (TFT AMLCD)以其高信息量、 多灰度级及能 实现彩***显示成为目前信息显示领域的主导技术和研究开发的热点。 随着 T FT AMLCD向大面积、 高清晰度的发展， 对金属电极材料的要求也越来越高。 一方面， 要求金属电极的电阻要低， 以减小信号延迟所引起的图像失真； 另一 方面， 金属薄膜的热稳定性和附着性要更好。 因此， 制备电阻率低、 热稳定性 和附着性好的金属薄膜与线路便成为研究开发的重点。  [0003] Thin film transistor active matrix liquid crystal displays (TFT AMLCD) have become the leading technology and research and development hotspot in the field of information display with its high information content, multiple gray levels, and the ability to achieve color video display. With the development of T FT AMLCD to a large area and high definition, the requirements for metal electrode materials are becoming higher and higher. On the one hand, the resistance of the metal electrode is required to be low in order to reduce the image distortion caused by the signal delay; on the other hand, the thermal stability and adhesion of the metal film are better. Therefore, the preparation of metal films and circuits with low resistivity, good thermal stability and adhesion has become the focus of research and development.
[0004] 在现有的 TFT中， 为了改善 TFT电极的接触性能， TFT电极通常采用多层金属 结构， 如图 1所示， 其中， TFT电极包括第一金属层 4和第二金属层 6， 第一金属 层 4与有源层 5接触。 在现有的 TFT制备工艺中， 先在有源层 5上沉积黏附性良好 的第一金属材料层、 第二金属材料层， 然后经光刻工艺进行蚀刻， 异种金属处 于同一蚀刻液中且彼此接触或通过其他导体连同， 由于腐蚀电位不同， 将会造 成第一金属材料层、 第二金属材料层接触部位的局部腐蚀即电偶腐蚀 (galvanic corrosion) 现象， 出现倒切角， 如图 1中虚线框所示， 倒切角的出现易造成后续 钝化膜断层、 TFT电性不稳定等异常， 甚至降低产品良率。  [0004] In the existing TFT, in order to improve the contact performance of the TFT electrode, the TFT electrode generally adopts a multilayer metal structure, as shown in FIG. 1, where the TFT electrode includes a first metal layer 4 and a second metal layer 6, The first metal layer 4 is in contact with the active layer 5. In the existing TFT manufacturing process, a first metal material layer and a second metal material layer with good adhesion are first deposited on the active layer 5 and then etched through a photolithography process. The dissimilar metals are in the same etching solution and are on each other. Contact or through other conductors together, due to the different corrosion potentials, the local corrosion of the first metal material layer and the second metal material layer at the contact points, ie galvanic corrosion, will result in chamfered corners, as shown in Figure 1. As shown by the dashed box, the occurrence of chamfered corners can easily cause abnormalities such as subsequent passivation film faults, TFT electrical instability, and even reduce product yield.
[0005] 为了解决上述问题， 本发明提供一种薄膜晶体管及其制备方法、 阵列基板， 能 够提升有源层与第二金属层之间的接触性能， 避免出现倒切角， 改善薄膜晶体 管的电学性能。  [0005] In order to solve the above problems, the present invention provides a thin film transistor, a method for manufacturing the same, and an array substrate, which can improve the contact performance between the active layer and the second metal layer, avoid the occurrence of chamfers, and improve the electrical properties of the thin film transistor. performance.
[0006] 发明内容  SUMMARY OF THE INVENTION
[0007] 本发明提出的具体技术方案为： 一种薄膜晶体管， 所述薄膜晶体管包括衬底、 栅极、 栅绝缘层、 第一金属层、 有源层、 第二金属层、 钝化层， 所述栅极设于 所述衬底上， 所述栅绝缘层覆盖所述栅极， 所述第一金属层包括间隔设置于所 述栅绝缘层上的第一电极和第二电极， 所述第二金属层包括间隔设置的源极和 漏极， 所述有源层的一端夹设于所述第一电极与所述源极之间， 所述有源层的 另一端夹设于所述第二电极与所述漏极之间， 所述钝化层覆盖于所述源极、 漏 极、 有源层裸露的表面。 [0007] A specific technical solution proposed by the present invention is: a thin film transistor, which includes a substrate, a gate, a gate insulating layer, a first metal layer, an active layer, a second metal layer, and a passivation layer, The gate is disposed on the substrate, the gate insulating layer covers the gate, and the first metal layer includes a gap disposed on the gate. A first electrode and a second electrode on the gate insulation layer, the second metal layer includes a source electrode and a drain electrode spaced apart, and one end of the active layer is sandwiched between the first electrode and the source electrode In between, the other end of the active layer is sandwiched between the second electrode and the drain, and the passivation layer covers the exposed surface of the source, drain, and active layer.
[0008] 进一步地， 所述源极与所述第一电极接触， 所述漏极与所述第二电极接触。  [0008] Further, the source electrode is in contact with the first electrode, and the drain electrode is in contact with the second electrode.
[0009] 进一步地， 所述第一金属层与所述栅绝缘层的黏附性大于所述第二金属层与所 述栅绝缘性的黏附性。 [0009] Further, the adhesion between the first metal layer and the gate insulation layer is greater than the adhesion between the second metal layer and the gate insulation.
[0010] 进一步地， 所述第二金属层的材质为铜。  [0010] Further, the material of the second metal layer is copper.
[0011] 进一步地， 所述第一金属层的材质选自钼、 铬、 钛中的一种。  [0011] Further, a material of the first metal layer is selected from one of molybdenum, chromium, and titanium.
[0012] 本发明还提供了一种阵列基板， 所述阵列基板包括如上任一所述的薄膜晶体管  [0012] The present invention also provides an array substrate, the array substrate including the thin film transistor according to any one of the above.
[0013] 本发明还提供了一种薄膜晶体管的制备方法， 所述制备方法包括步骤： [0013] The present invention also provides a method for manufacturing a thin film transistor, the method includes the steps:
[0014] 提供一衬底；  [0014] providing a substrate;
[0015] 在所述衬底上形成栅极和栅绝缘层， 所述栅绝缘层覆盖所述栅极；  [0015] forming a gate and a gate insulating layer on the substrate, the gate insulating layer covering the gate;
[0016] 在所述栅绝缘层上形成第一金属层， 所述第一金属层包括间隔设置于所述栅绝 缘层上的第一电极和第二电极；  [0016] forming a first metal layer on the gate insulating layer, the first metal layer including a first electrode and a second electrode disposed on the gate insulating layer at intervals;
[0017] 在所述第一金属层上形成有源层、 第二金属层， 所述第二金属层包括间隔设置 的源极和漏极， 所述有源层的一端夹设于所述第一电极与所述源极之间， 所述 有源层的另一端夹设于所述第二电极与所述漏极之间；  [0017] An active layer and a second metal layer are formed on the first metal layer, the second metal layer includes a source electrode and a drain electrode spaced apart, and one end of the active layer is sandwiched between the first metal layer and the first metal layer. Between an electrode and the source, and the other end of the active layer is sandwiched between the second electrode and the drain;
[0018] 沉积钝化层， 所述钝化层覆盖于所述源极、 漏极、 有源层裸露的表面。  [0018] depositing a passivation layer covering the exposed surfaces of the source, drain, and active layers.
[0019] 进一步地， 在所述第一金属层上形成有源层、 第二金属层具体包括：  [0019] Further, forming an active layer on the first metal layer, and the second metal layer specifically include:
[0020] 在所述第一金属层上沉积有源材料层；  [0020] depositing an active material layer on the first metal layer;
[0021] 在所述有源材料层上涂布第三光阻层， 通过第三道光罩对所述第三光阻层进行 曝光， 使所述第三光阻层图案化， 形成第三光阻区域；  [0021] coating a third photoresist layer on the active material layer, exposing the third photoresist layer through a third mask, and patterning the third photoresist layer to form a third light Resistance area
[0022] 通过蚀刻制程移除未被所述第三光阻区域覆盖的有源材料层， 形成有源层， 所 述有源层的一端与所述第一电极接触并覆盖部分第一电极， 所述有源层的另一 端与所述第二电极接触并覆盖部分第二电极；  [0022] removing an active material layer not covered by the third photoresist region by an etching process to form an active layer, one end of the active layer is in contact with the first electrode and covers a portion of the first electrode, The other end of the active layer is in contact with the second electrode and covers part of the second electrode;
[0023] 在所述栅绝缘层、 第一电极、 第二电极和有源层上沉积第二金属材料层； [0024] 在所述第二金属材料层上涂布第四光阻层， 通过第四道光罩对所述第四光阻层 进行曝光， 使所述第四光阻层图案化， 形成相互间隔的第四光阻区域； [0023] depositing a second metal material layer on the gate insulating layer, the first electrode, the second electrode, and the active layer; [0024] coating a fourth photoresist layer on the second metal material layer, exposing the fourth photoresist layer through a fourth photomask, and patterning the fourth photoresist layer to form an interval The fourth photoresist region;
[0025] 通过蚀刻制程移除未被所述第四光阻区域覆盖的第二金属材料层， 形成第二金 属层， 所述第二金属层包括间隔设置的源极和漏极， 所述有源层的一端夹设于 所述第一电极与所述源极之间， 所述有源层的另一端夹设于所述第二电极与所 述漏极之间， 所述源极与所述第一电极接触， 所述漏极与所述第二电极接触。  [0025] removing a second metal material layer not covered by the fourth photoresist region by an etching process to form a second metal layer, the second metal layer including source and drain electrodes disposed at intervals, and having One end of the source layer is sandwiched between the first electrode and the source, the other end of the active layer is sandwiched between the second electrode and the drain, and the source and The first electrode is in contact, and the drain is in contact with the second electrode.
[0026] 进一步地， 在所述第一金属层上形成有源层、 第二金属层包括：  [0026] Further, forming an active layer on the first metal layer, and the second metal layer includes:
[0027] 在所述第一金属层上沉积有源材料层；  [0027] depositing an active material layer on the first metal layer;
[0028] 在所述有源材料层上沉积第二金属材料层；  [0028] depositing a second metal material layer on the active material layer;
[0029] 在所述第二金属材料层上涂覆第三光阻层， 通过第三道光罩对所述第三光阻层 进行灰阶曝光， 使所述第三光阻层图案化， 形成第三光阻区域， 所述第三光阻 区域包括中间部和位于该中间部两侧的侧部， 所述中间部的厚度小于侧部的厚 度；  [0029] coating a third photoresist layer on the second metal material layer, performing grayscale exposure on the third photoresist layer through a third mask, and patterning the third photoresist layer to form A third photoresistive region, the third photoresistive region including an intermediate portion and side portions on both sides of the intermediate portion, and a thickness of the intermediate portion is smaller than a thickness of the side portion;
[0030] 通过蚀刻制程移除未被所述第三光阻区域覆盖的有源材料层、 第二金属材料层 ， 形成有源层， 所述有源层的一端与所述第一电极接触， 所述有源层的另一端 与所述第二电极接触；  [0030] removing the active material layer and the second metal material layer that are not covered by the third photoresist region by an etching process to form an active layer, and one end of the active layer is in contact with the first electrode, The other end of the active layer is in contact with the second electrode;
[0031] 对所述第三光阻区域进行灰化处理， 以去除中间部并减少侧部的厚度， 保留部 分侧部；  [0031] performing ashing treatment on the third photoresist region to remove the middle portion and reduce the thickness of the side portion, and to retain the portion of the side portion;
[0032] 通过蚀刻制程移除未被所述部分侧部覆盖的第二金属材料层， 形成第二金属层 ， 所述第二金属层包括间隔设置的源极和漏极， 所述有源层的一端夹设于所述 第一电极与所述源极之间， 所述有源层的另一端夹设于所述第二电极与所述漏 极之间。  [0032] removing a second metal material layer that is not covered by the side portion by an etching process to form a second metal layer, the second metal layer includes source and drain electrodes spaced apart, and the active layer One end is sandwiched between the first electrode and the source electrode, and the other end of the active layer is sandwiched between the second electrode and the drain electrode.
[0033] 本发明提出的薄膜晶体管包括有源层、 源极、 漏极以及间隔设置的第一电极和 第二电极， 所述有源层的一端夹设于所述第一电极与所述源极之间， 所述有源 层的另一端夹设于所述第二电极与所述漏极之间， 通过将有源层夹设于第一金 属层与第二金属层之间， 提升了有源层与第二金属层之间的接触性能。 本发明 的制备方法中第一金属层与第二金属层通过两次构图工艺形成， 从而避免出现 倒切角， 改善薄膜晶体管的电学性能。 发明概述 [0033] The thin film transistor provided by the present invention includes an active layer, a source, a drain, and a first electrode and a second electrode disposed at intervals. One end of the active layer is sandwiched between the first electrode and the source. Between the electrodes, the other end of the active layer is sandwiched between the second electrode and the drain. By sandwiching the active layer between the first metal layer and the second metal layer, it is improved. Contact performance between the active layer and the second metal layer. In the preparation method of the present invention, the first metal layer and the second metal layer are formed by two patterning processes, thereby avoiding the occurrence of chamfers and improving the electrical performance of the thin film transistor. Summary of invention
技术问题  technical problem
问题的解决方案  Problem solution
发明的有益效果  The beneficial effects of the invention
对附图的简要说明  Brief description of the drawings
附图说明  BRIEF DESCRIPTION OF THE DRAWINGS
[0034] 下面结合附图， 通过对本发明的具体实施方式详细描述， 将使本发明的技术方 案及其它有益效果显而易见。  [0034] The following describes the specific embodiments of the present invention in detail with reference to the accompanying drawings to make the technical solution and other beneficial effects of the present invention obvious.
[0035] 图 1为现有的薄膜晶体管制备过程中出现倒切角的结构示意图；  [0035] FIG. 1 is a schematic view of a structure in which a chamfered corner occurs during the preparation of an existing thin film transistor;
[0036] 图 2为本发明实施例 1中阵列基板的结构示意图；  [0036] FIG. 2 is a schematic structural diagram of an array substrate in Embodiment 1 of the present invention;
[0037] 图 3a-3f为实施例 1中薄膜晶体管的制备方法流程图；  3a-3f are flowcharts of a method for manufacturing a thin film transistor in Example 1;
[0038] 图 4a-4e为实施例 1中栅极和栅绝缘层的制备流程图；  4a-4e are flowcharts of preparing a gate and a gate insulating layer in Embodiment 1;
[0039] 图 5a-5d为实施例 1中第一金属层的制备流程图；  5a-5d are flowcharts of the preparation of the first metal layer in Example 1;
[0040] 图 6a-6d为实施例 1中有源层的制备流程图；  6a-6d are flowcharts of the preparation of an active layer in Example 1;
[0041] 图 7a-7d为实施例 1中第二金属层的制备流程图；  7a-7d are flowcharts of preparing a second metal layer in Example 1;
[0042] 图 8为本发明实施例 2中阵列基板的结构示意图；  8 is a schematic structural diagram of an array substrate in Embodiment 2 of the present invention;
[0043] 图 9a-9j为实施例 2中薄膜晶体管的制备方法流程图。  9a-9j are flowcharts of a method for manufacturing a thin film transistor in Embodiment 2.
[0044] 具体实施方式  DETAILED DESCRIPTION
[0045] 以下， 将参照附图来详细描述本发明的实施例。 然而， 可以以许多不同的形式 来实施本发明， 并且本发明不应该被解释为限制于这里阐述的具体实施例。 相 反， 提供这些实施例是为了解释本发明的原理及其实际应用， 从而使本领域的 其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改 。 在附图中， 相同的标号将始终被用于表示相同的元件。  [0045] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The invention may, however, be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. Rather, these embodiments are provided to explain the principles of the invention and its practical application, to thereby enable others skilled in the art to understand the various embodiments of the invention and various modifications as are suited to the particular contemplated application. In the drawings, the same reference numerals will always be used to represent the same elements.
[0046] 本发明提供了一种薄膜晶体管， 所述薄膜晶体管包括衬底、 栅极、 栅绝缘层、 第一金属层、 有源层、 第二金属层、 钝化层， 栅极设于衬底上， 栅绝缘层覆盖 栅极， 第一金属层包括间隔设置于栅绝缘层上的第一电极和第二电极， 第二金 属层包括间隔设置的源极和漏极， 有源层的一端夹设于第一电极与源极之间， 有源层的另一端夹设于第二电极与漏极之间， 钝化层覆盖于源极、 漏极、 有源 层裸露的表面。 [0046] The present invention provides a thin film transistor, which includes a substrate, a gate, a gate insulating layer, a first metal layer, an active layer, a second metal layer, and a passivation layer, and the gate is disposed on the substrate. On the bottom, a gate insulating layer covers the gate. The first metal layer includes first and second electrodes spaced apart from the gate insulating layer. The second metal layer includes source and drain electrodes spaced apart. One end of the active layer Sandwiched between the first electrode and the source, The other end of the active layer is sandwiched between the second electrode and the drain, and the passivation layer covers the exposed surfaces of the source, drain, and active layer.
[0047] 本发明还提供了一种薄膜晶体管的制备方法， 所述制备方法包括以下步骤： [0047] The present invention also provides a method for manufacturing a thin film transistor. The method includes the following steps:
[0048] 提供一衬底； [0048] providing a substrate;
[0049] 在衬底上形成栅极和栅绝缘层， 栅绝缘层覆盖栅极；  [0049] forming a gate and a gate insulating layer on a substrate, the gate insulating layer covering the gate;
[0050] 在栅绝缘层上形成第一金属层， 第一金属层包括间隔设置于栅绝缘层上的第一 电极和第二电极；  [0050] forming a first metal layer on the gate insulating layer, the first metal layer including a first electrode and a second electrode disposed on the gate insulating layer at intervals;
[0051] 在第一金属层上形成有源层、 第二金属层， 第二金属层包括间隔设置的源极和 漏极， 有源层的一端夹设于第一电极与源极之间， 有源层的另一端夹设于第二 电极与漏极之间；  [0051] forming an active layer and a second metal layer on the first metal layer, the second metal layer including a source electrode and a drain electrode spaced apart, and one end of the active layer is sandwiched between the first electrode and the source electrode, The other end of the active layer is sandwiched between the second electrode and the drain;
[0052] 沉积钝化层， 钝化层覆盖于源极、 漏极、 有源层裸露的表面。  [0052] A passivation layer is deposited, and the passivation layer covers the exposed surfaces of the source, drain, and active layers.
[0053] 本发明提出的薄膜晶体管包括有源层、 源极、 漏极以及间隔设置的第一电极和 第二电极， 所述有源层的一端夹设于所述第一电极与所述源极之间， 所述有源 层的另一端夹设于所述第二电极与所述漏极之间， 通过将有源层夹设于第一金 属层与第二金属层之间， 提升了有源层与第二金属层之间的接触性能。 本发明 的制备方法中第一金属层与第二金属层通过两次构图工艺形成， 从而避免了通 过一次构图工艺而出现倒切角， 改善薄膜晶体管的电学性能。  [0053] The thin film transistor provided by the present invention includes an active layer, a source, a drain, and a first electrode and a second electrode disposed at intervals. One end of the active layer is sandwiched between the first electrode and the source. Between the electrodes, the other end of the active layer is sandwiched between the second electrode and the drain. By sandwiching the active layer between the first metal layer and the second metal layer, it is improved. Contact performance between the active layer and the second metal layer. In the preparation method of the present invention, the first metal layer and the second metal layer are formed through two patterning processes, thereby avoiding the chamfering angle through one patterning process and improving the electrical performance of the thin film transistor.
[0054] 下面通过两个具体的实施例来对本发明的薄膜晶体管的结构以及制备方法进行 详细的描述。  [0054] The structure and manufacturing method of the thin film transistor of the present invention will be described in detail through two specific embodiments.
[0055] 实施例 1  Example 1
[0056] 参照图 2, 本实施例中的阵列基板包括多个薄膜晶体管 10, 多个薄膜晶体管呈 阵列设置。 薄膜晶体管 10包括衬底 1、 栅极 2、 栅绝缘层 3、 第一金属层 4、 有源 层 5、 第二金属层 6、 钝化层 7。 栅极 2设于衬底 1上， 栅绝缘层 3覆盖栅极 2, 第一 金属层 4包括间隔设置于栅绝缘层 3上的第一电极 41和第二电极 42, 第二金属层 6 包括间隔设置的源极 61和漏极 62， 源极 61位于第一电极 41上并与第一电极 41接 触， 漏极 62位于第二电极 42上并与第二电极 42接触， 有源层 5包括源极接触端 51 、 背沟道部 52、 漏极接触端 53 , 源极接触端 51夹设于第一电极 41与源极 61之间 并覆盖部分第一电极 41， 漏极接触端 53夹设于第二电极 42与漏极 62之间并覆盖 部分第二电极 42， 背沟道区 52位于第一电极 41与第二电极 42之间并与栅极 2对应 ， 钝化层 7覆盖于源极 61、 漏极 62、 有源层 5裸露的表面。 [0056] Referring to FIG. 2, the array substrate in this embodiment includes a plurality of thin film transistors 10, and the plurality of thin film transistors are arranged in an array. The thin film transistor 10 includes a substrate 1, a gate 2, a gate insulating layer 3, a first metal layer 4, an active layer 5, a second metal layer 6, and a passivation layer 7. The gate electrode 2 is disposed on the substrate 1. The gate insulating layer 3 covers the gate electrode 2. The first metal layer 4 includes a first electrode 41 and a second electrode 42 spaced from the gate insulating layer 3. The second metal layer 6 includes The source electrode 61 and the drain electrode 62 are arranged at intervals. The source electrode 61 is located on the first electrode 41 and is in contact with the first electrode 41, and the drain electrode 62 is located on the second electrode 42 and is in contact with the second electrode 42. The active layer 5 includes The source contact terminal 51, the back channel portion 52, and the drain contact terminal 53, the source contact terminal 51 is sandwiched between the first electrode 41 and the source electrode 61 and covers part of the first electrode 41, and the drain contact terminal 53 is clamped. Provided between the second electrode 42 and the drain electrode 62 and covering Part of the second electrode 42, the back channel region 52 is located between the first electrode 41 and the second electrode 42 and corresponds to the gate 2. The passivation layer 7 covers the source 61, the drain 62, and the exposed active layer 5. surface.
[0057] 本实施例中， 第一电极 41和第二电极 42与栅绝缘层 3的黏附性大于源极 61和漏 极 62与栅绝缘层 3的黏附性。 栅绝缘层 3的材质为绝缘材料， 较佳地， 第二金属 层 6的材质为铜， 由于铜具有低阻抗、 高导电率等优良性能， 成为主流的电极导 电金属材料， 但是， 铜与栅绝缘层之间的黏附性较差， 因此， 在第二金属层 6与 栅绝缘层 3之间设置第一金属层 4, 第二金属层 6与第一金属层 4接触， 第一金属 层 4的材质选自钼、 铬、 钛中的一种， 第一金属层 4与栅绝缘层 3之间具有较好的 黏附性， 从而在降低金属电极的电阻率的同时提升金属电极的热稳定性和附着 性。 其中， 本实施例中的金属电极指的是源极 61或者漏极 62。  [0057] In this embodiment, the adhesion of the first electrode 41 and the second electrode 42 to the gate insulating layer 3 is greater than the adhesion of the source 61 and the drain electrode 62 to the gate insulating layer 3. The material of the gate insulating layer 3 is an insulating material. Preferably, the material of the second metal layer 6 is copper. Because copper has excellent properties such as low resistance and high conductivity, it has become a mainstream electrode conductive metal material. However, copper and the gate The adhesion between the insulating layers is poor. Therefore, a first metal layer 4 is provided between the second metal layer 6 and the gate insulating layer 3, the second metal layer 6 is in contact with the first metal layer 4, and the first metal layer 4 The material is selected from one of molybdenum, chromium, and titanium. The first metal layer 4 and the gate insulating layer 3 have good adhesion, thereby reducing the resistivity of the metal electrode and improving the thermal stability of the metal electrode. And adhesion. The metal electrode in this embodiment refers to a source electrode 61 or a drain electrode 62.
[0058] 本实施例中， 源极接触端 51设于第一电极 41与源极 61之间， 漏极接触端 53夹设 于第二电极 42与漏极 62之间， 通过将有源层 5夹设于第一金属层 4与第二金属层 6 之间， 提升了有源层 5与第二金属层 6之间的接触性能。  [0058] In this embodiment, the source contact terminal 51 is provided between the first electrode 41 and the source electrode 61, and the drain contact terminal 53 is sandwiched between the second electrode 42 and the drain electrode 62. 5 is interposed between the first metal layer 4 and the second metal layer 6 to improve the contact performance between the active layer 5 and the second metal layer 6.
[0059] 本实施例中的阵列基板还包括像素电极 8， 像素电极 8通过过孔与漏极 62连接。  [0059] The array substrate in this embodiment further includes a pixel electrode 8, and the pixel electrode 8 is connected to the drain electrode 62 through a via hole.
[0060] 参照图 3a-3f， 本实施例还提供了上述薄膜晶体管的制备方法的第一实施方式， 在第一实施方式中， 所述制备方法包括步骤： [0060] Referring to FIGS. 3a-3f, this embodiment further provides a first embodiment of the above-mentioned method for manufacturing a thin film transistor. In the first embodiment, the method includes the following steps:
[0061] S1、 提供一衬底 1， 如图 3a所示；  [0061] S1, a substrate 1 is provided, as shown in FIG. 3a;
[0062] S2、 4在衬底 1上形成栅极 2和栅绝缘层 3 , 栅绝缘层 3覆盖栅极 2, 如图 3b所示； [0062] S2, 4 form a gate 2 and a gate insulating layer 3 on a substrate 1, and the gate insulating layer 3 covers the gate 2, as shown in FIG. 3b;
[0063] S3、 4在栅绝缘层 3上形成第一金属层 4, 第一金属层 4包括间隔设置于栅绝缘层[0063] S3 and 4 form a first metal layer 4 on the gate insulating layer 3, and the first metal layer 4 includes a gate insulating layer disposed at intervals.
3上的第一电极 41和第二电极 42， 如图 3c所示； The first electrode 41 and the second electrode 42 on 3, as shown in FIG. 3c;
[0064] S4、 4在第一金属层 4上形成有源层 5 , 有源层 5包括源极接触端 51、 背沟道部 52 [0064] S4, 4 form an active layer 5 on the first metal layer 4. The active layer 5 includes a source contact terminal 51 and a back channel portion 52.
、 漏极接触端 53 , 源极接触端 51与第一电极 41接触并覆盖部分第一电极 41， 漏 极接触端 53与第二电极 42接触并覆盖部分第二电极 42， 背沟道区 52位于第一电 极 41与第二电极 42之间并与栅极 2对应， 如图 3d所示； The drain contact end 53, the source contact end 51 is in contact with the first electrode 41 and covers part of the first electrode 41, the drain contact end 53 is in contact with the second electrode 42 and covers part of the second electrode 42, and the back channel region 52 Located between the first electrode 41 and the second electrode 42 and corresponding to the gate 2, as shown in FIG. 3d;
[0065] S5、 在第一金属层 4和有源层 5上形成第二金属层 6， 第二金属层 6包括间隔设置 的源极 61和漏极 62， 源极 61位于第一电极 41上， 漏极 62位于第二电极 42上， 源 极接触端 51夹设于第一电极 41与源极 61之间， 漏极接触端 53夹设于第二电极 42 与漏极 62之间， 源极 61与第一电极 41接触， 漏极 62与第二电极 42接触， 如图 3e所 不； [0065] S5. A second metal layer 6 is formed on the first metal layer 4 and the active layer 5. The second metal layer 6 includes a source electrode 61 and a drain electrode 62 disposed at intervals. The source electrode 61 is located on the first electrode 41. The drain 62 is located on the second electrode 42, the source contact 51 is sandwiched between the first electrode 41 and the source 61, and the drain contact 53 is sandwiched between the second electrode 42 and the drain 62. The electrode 61 is in contact with the first electrode 41, and the drain 62 is in contact with the second electrode 42, as shown in FIG. 3e. Do not;
[0066] S6、 沉积钝化层 7， 钝化层 7覆盖于源极 61、 漏极 62、 有源层 5裸露的表面， 如 图 3fB)f示。 [0066] S6. A passivation layer 7 is deposited, and the passivation layer 7 covers the exposed surfaces of the source 61, the drain 62, and the active layer 5, as shown in FIG. 3fB ) f.
[0067] 在本实施例的制备方法中， 第一金属层 4与第二金属层 6通过两次构图工艺得到 ， 从而可以避免形成第一金属层 4与第二金属层 6时， 由于刻蚀液对不同的金属 材料的刻蚀速率不同造成第一金属层 4与第二金属层 6接触部位出现局部腐蚀而 出现倒切角现象， 造成后续钝化层断层、 薄膜晶体管电性不稳定等， 提高生产 良率。  [0067] In the manufacturing method of this embodiment, the first metal layer 4 and the second metal layer 6 are obtained through two patterning processes, so that the formation of the first metal layer 4 and the second metal layer 6 due to etching can be avoided. The different etching rates of different metal materials by the liquid cause local corrosion of the first metal layer 4 and the second metal layer 6 and a chamfer phenomenon, which leads to subsequent failure of the passivation layer and electrical instability of the thin film transistor. Improve production yield.
[0068] 参照图 4a-4e， 具体地， 步骤 S2包括：  [0068] Referring to FIGS. 4a-4e, specifically, step S2 includes:
[0069] S21、 在衬底 1上依次沉积栅极材料层 20、 第一光阻层 100， 如图 4a所示；  [0069] S21, sequentially depositing a gate material layer 20 and a first photoresist layer 100 on the substrate 1, as shown in FIG. 4a;
[0070] S22、 通过第一道光罩对第一光阻层 100进行曝光， 使第一光阻层图案化， 形成 第一光阻区域， 如图 4b所示；  [0070] S22. Expose the first photoresist layer 100 through the first photomask to pattern the first photoresist layer to form a first photoresist region, as shown in FIG. 4b;
[0071] S23、 通过蚀刻制程移除未被第一光阻区域覆盖的栅极材料层 20, 形成栅极 2, 如图 4c所示；  [0071] S23. Remove the gate material layer 20 not covered by the first photoresist region by an etching process to form a gate 2, as shown in FIG. 4c;
[0072] S24、 通过光阻灰化工艺将第一光阻区域去除， 如图 4d所示；  [0072] S24. Remove the first photoresist region by a photoresist ashing process, as shown in FIG. 4d;
[0073] S25、 在衬底 1和栅极 2上沉积栅绝缘层 3 , 栅绝缘层 3覆盖栅极 2, 如图 4e所示。  [0073] S25. A gate insulating layer 3 is deposited on the substrate 1 and the gate 2. The gate insulating layer 3 covers the gate 2, as shown in FIG. 4e.
[0074] 参照图 5a-5d， 具体地， 步骤 S3包括：  5a-5d, specifically, step S3 includes:
[0075] S21、 在栅绝缘层 3上依次沉积第一金属材料层 40、 第二光阻层 101， 如图 5a所 示；  [0075] S21, sequentially depositing a first metal material layer 40 and a second photoresist layer 101 on the gate insulating layer 3, as shown in FIG. 5a;
[0076] S22、 通过第二道光罩对第二光阻层 101进行曝光， 使第二光阻层图案化， 形成 相互间隔的第二光阻区域， 如图 5b所示；  [0076] S22. Expose the second photoresist layer 101 through a second photomask to pattern the second photoresist layer to form second photoresist regions spaced apart from each other, as shown in FIG. 5b;
[0077] S23、 通过蚀刻制程移除未被第二光阻区域覆盖的第一金属材料层 40, 形成第 一金属层 4, 第一金属层 4包括间隔设置于栅绝缘层 3上的第一电极 41和第二电极 42， 如图 5c所示；  [0077] S23. The first metal material layer 40 not covered by the second photoresist area is removed by an etching process to form a first metal layer 4. The first metal layer 4 includes first spacers disposed on the gate insulating layer 3. The electrode 41 and the second electrode 42 are shown in FIG. 5c;
[0078] S24、 通过光阻灰化工艺将第二光阻区域去除， 如图 5d所示。  [0078] S24. Remove the second photoresist region by a photoresist ashing process, as shown in FIG. 5d.
[0079] 参照图 6a-6d， 具体地， 步骤 S4包括：  6a-6d, specifically, step S4 includes:
[0080] S41、 在第一金属层 4上依次沉积有源材料层 50、 第三光阻层 102， 如图 6a所示 [0081] S42、 通过第三道光罩对第三光阻层 102进行曝光， 使第三光阻层图案化， 形成 第三光阻区域， 如图 6b所示； [0080] S41. An active material layer 50 and a third photoresist layer 102 are sequentially deposited on the first metal layer 4, as shown in FIG. 6a. [0081] S42. Expose the third photoresist layer 102 through a third photomask to pattern the third photoresist layer to form a third photoresist region, as shown in FIG. 6b;
[0082] S43、 通过蚀刻制程移除未被第三光阻区域覆盖的有源材料层 50, 形成有源层 5 [0082] S43. Remove the active material layer 50 not covered by the third photoresist region by an etching process to form an active layer 5
， 有源层 5包括源极接触端 51、 背沟道部 52、 漏极接触端 53， 源极接触端 51与第 一电极 41接触并覆盖部分第一电极 41， 漏极接触端 53与第二电极 42接触并覆盖 部分第二电极 42， 背沟道区 52位于第一电极 41与第二电极 42之间并与栅极 2对应 ， 如图 6c所示； The active layer 5 includes a source contact terminal 51, a back channel portion 52, and a drain contact terminal 53, the source contact terminal 51 is in contact with the first electrode 41 and covers a part of the first electrode 41, and the drain contact terminal 53 and the first The two electrodes 42 contact and cover a part of the second electrode 42, and the back channel region 52 is located between the first electrode 41 and the second electrode 42 and corresponds to the gate electrode 2, as shown in FIG. 6c;
[0083] S44、 通过光阻灰化工艺将第三光阻区域去除， 如图 6d所示。  [0083] S44. Remove the third photoresist region through a photoresist ashing process, as shown in FIG. 6d.
[0084] 参照图 7a-7d， 具体地， 步骤 S5包括：  [0084] Referring to FIGS. 7a-7d, specifically, step S5 includes:
[0085] S51、 在栅绝缘层 3、 第一金属层 4、 有源层 5上沉积第二金属材料层 60、 第四光 阻层 103， 如图 7a所示；  [0085] S51, depositing a second metal material layer 60 and a fourth photoresist layer 103 on the gate insulating layer 3, the first metal layer 4, and the active layer 5, as shown in FIG. 7a;
[0086] S52、 通过第四道光罩对第四光阻层 103进行曝光， 使第四光阻层图案化， 形成 相互间隔的第四光阻区域， 如图 7b所示；  [0086] S52. Expose the fourth photoresist layer 103 through a fourth photomask to pattern the fourth photoresist layer to form fourth photoresist regions spaced apart from each other, as shown in FIG. 7b;
[0087] S53、 通过蚀刻制程移除未被第四光阻区域覆盖的第二金属材料层 60, 形成第 二金属层 6 , 第二金属层 6包括间隔设置的源极 61和漏极 62, 源极接触端 51夹设 于第一电极 41与源极 61之间， 漏极接触端 53夹设于第二电极 42与漏极 62之间， 源极 61与第一电极 41接触， 漏极 62与第二电极 42接触， 如图 7c所示；  [0087] S53. The second metal material layer 60 that is not covered by the fourth photoresist area is removed by an etching process to form a second metal layer 6, and the second metal layer 6 includes a source electrode 61 and a drain electrode 62 spaced apart. The source contact end 51 is sandwiched between the first electrode 41 and the source electrode 61, the drain contact end 53 is sandwiched between the second electrode 42 and the drain electrode 62, the source electrode 61 is in contact with the first electrode 41, and the drain electrode 62 is in contact with the second electrode 42, as shown in FIG. 7c;
[0088] S54、 通过光阻灰化工艺将第四光阻区域去除， 如图 7d所示。  [0088] S54. The fourth photoresist region is removed by a photoresist ashing process, as shown in FIG. 7d.
[0089] 在制备阵列基板时， 在步骤 S6之后， 还需要通过第五道光罩工艺来对钝化层进 行图形化处理， 在钝化层上形成过孔， 然后， 在钝化层上沉积像素电极材料层 ， 通过第六道光罩工艺来对像素电极材料层进行图案化处理， 获得像素电极 8， 整个阵列基板的制备过程需要需要六道光罩。  [0089] When preparing the array substrate, after step S6, the passivation layer needs to be patterned through a fifth photomask process, a via hole is formed in the passivation layer, and then a pixel is deposited on the passivation layer. For the electrode material layer, the pixel electrode material layer is patterned through a sixth photomask process to obtain the pixel electrode 8. The entire array substrate preparation process requires six photomasks.
[0090] 实施例 2  Example 2
[0091] 参照图 8， 本实施例与实施例 1的不同之处在于， 源极 61与第一电极 41不接触， 漏极 62与第二电极 42不接触。  [0091] Referring to FIG. 8, this embodiment is different from Embodiment 1 in that the source electrode 61 is not in contact with the first electrode 41, and the drain electrode 62 is not in contact with the second electrode 42.
[0092] 参照图 9a-9j， 本实施例的制备方法采用半色调掩模工艺， 所述制备方法包括步 骤：  [0092] Referring to FIGS. 9a-9j, the manufacturing method of this embodiment uses a half-tone mask process, and the manufacturing method includes steps:
[0093] S1、 提供一衬底 1， 如图 9a所示； [0094] S2、 在衬底 1上形成栅极 2和栅绝缘层 3 , 栅绝缘层 3覆盖栅极 2, 如图 9b所示；[0093] S1. A substrate 1 is provided, as shown in FIG. 9a; [0094] S2. A gate 2 and a gate insulating layer 3 are formed on the substrate 1, and the gate insulating layer 3 covers the gate 2, as shown in FIG. 9b;
[0095] S3、 在栅绝缘层 3上形成第一金属层 4, 第一金属层 4包括间隔设置于栅绝缘层 3 上的第一电极 41和第二电极 42， 如图 9c所示； [0095] S3. A first metal layer 4 is formed on the gate insulating layer 3, and the first metal layer 4 includes a first electrode 41 and a second electrode 42 spaced from the gate insulating layer 3, as shown in FIG. 9c;
[0096] S4、 在第一金属层 4上依次沉积有源材料层 50、 第二金属材料层 60、 第三光阻 层 70， 如图 9d所示；  [0096] S4. An active material layer 50, a second metal material layer 60, and a third photoresist layer 70 are sequentially deposited on the first metal layer 4, as shown in FIG. 9d;
[0097] S5、 通过第三道光罩对第三光阻层 70进行灰阶曝光， 使第三光阻层图案化， 形 成第三光阻区域， 第三光阻区域包括中间部和位于该中间部两侧的侧部， 中间 部的厚度小于侧部的厚度， 如图 9e所示；  [0097] S5. Perform grayscale exposure on the third photoresist layer 70 through the third photomask to pattern the third photoresist layer to form a third photoresist region. The third photoresist region includes a middle portion and is located in the middle. The thickness of the side portion on both sides of the portion is smaller than the thickness of the side portion, as shown in FIG. 9e;
[0098] S6、 通过蚀刻制程移除未被第三光阻区域覆盖的有源材料层 50、 第二金属材料 层 60, 形成有源层 5 , 如图 9f所示， 有源层 5包括源极接触端 51、 背沟道部 52、 漏 极接触端 53 , 源极接触端 51延伸至第一电极 41的表面， 漏极接触端 53延伸至第 二电极 42的表面， 背沟道区 52位于第一电极 41与第二电极 42之间并与栅极 2对应  [0098] S6. The active material layer 50 and the second metal material layer 60 that are not covered by the third photoresist area are removed by an etching process to form an active layer 5. As shown in FIG. 9f, the active layer 5 includes a source. The electrode contact terminal 51, the back channel portion 52, and the drain contact terminal 53, the source contact terminal 51 extends to the surface of the first electrode 41, the drain contact terminal 53 extends to the surface of the second electrode 42, and the back channel region 52 Located between the first electrode 41 and the second electrode 42 and corresponding to the gate 2
[0099] S7、 对第三光阻区域进行灰化处理， 以去除中间部并减少侧部的厚度， 保留部 分侧部， 如图 9g所示； [0099] S7. The third photoresist region is subjected to ashing treatment to remove the middle portion and reduce the thickness of the side portions, and to retain portions of the side portions, as shown in FIG. 9g;
[0100] S8、 通过蚀刻制程移除未被部分侧部覆盖的第二金属材料层 60， 形成第二金属 层 6 , 第二金属层 6包括间隔设置的源极 61和漏极 62, 源极接触端 51夹设于第一 电极 41与源极 61之间， 漏极接触端 53夹设于第二电极 42与漏极 62之间， 如图 9h 所示；  [0100] S8. The second metal material layer 60 that is not partially covered by the side is removed by an etching process to form a second metal layer 6. The second metal layer 6 includes a source electrode 61 and a drain electrode 62 that are disposed at intervals. The contact end 51 is sandwiched between the first electrode 41 and the source electrode 61, and the drain contact end 53 is sandwiched between the second electrode 42 and the drain electrode 62, as shown in FIG. 9h;
[0101] S9、 通过光阻灰化工艺将第三光阻区域去除， 如图 9i所示  [0101] S9. Remove the third photoresist region through a photoresist ashing process, as shown in FIG. 9i
[0102] S10、 沉积钝化层 7， 钝化层 7覆盖于源极 61、 漏极 62、 有源层 5裸露的表面， 如 图 9j所示。  [0102] S10. A passivation layer 7 is deposited, and the passivation layer 7 covers the exposed surfaces of the source 61, the drain 62, and the active layer 5, as shown in FIG. 9j.
[0103] 本实施例中步骤 S1-S3与实施例 1中相同， 这里不再赘述。 在制备阵列基板时， 在步骤 S10之后， 还需要通过第四道光罩工艺来对钝化层进行图形化处理， 在钝 化层上形成过孔， 然后， 在钝化层上沉积像素电极材料层， 通过第五道光罩工 艺来对像素电极材料层进行图案化处理， 获得像素电极 8 , 整个阵列基板的制备 过程需要需要五道光罩。 因此， 本实施例在薄膜晶体管的制备方法通过半色调 掩模工艺在第一金属层 4上形成有源层 5、 第二金属层 6 , 相对于第一实施方式可 以节省一道光罩， 从而简化制备工艺、 降低制备成本。 [0103] Steps S1-S3 in this embodiment are the same as those in Embodiment 1, and details are not described herein again. When preparing the array substrate, after step S10, the passivation layer needs to be patterned through a fourth photomask process, a via hole is formed in the passivation layer, and then a pixel electrode material layer is deposited on the passivation layer. The pixel electrode material layer is patterned through a fifth photomask process to obtain the pixel electrode 8. The entire array substrate preparation process requires five photomasks. Therefore, in this embodiment, in the method for manufacturing a thin film transistor, the active layer 5 and the second metal layer 6 are formed on the first metal layer 4 through a half-tone mask process. Compared with the first embodiment, In order to save a photomask, thereby simplifying the manufacturing process and reducing the manufacturing cost.
[0104] 以上所述仅是本申请的具体实施方式， 应当指出， 对于本技术领域的普通技术 人员来说， 在不脱离本申请原理的前提下， 还可以做出若干改进和润饰， 这些 改进和润饰也应视为本申请的保护范围。  [0104] The above description is only a specific implementation of the present application. It should be noted that, for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and retouches can be made. These improvements He retouching should also be regarded as the protection scope of this application.

Claims

权利要求书 Claim
[权利要求 1] 一种薄膜晶体管， 其特征在于， 包括衬底、 栅极、 栅绝缘层、 第一金 属层、 有源层、 第二金属层、 钝化层， 所述栅极设于所述衬底上， 所 述栅绝缘层覆盖所述栅极， 所述第一金属层包括间隔设置于所述栅绝 缘层上的第一电极和第二电极， 所述第二金属层包括间隔设置的源极 和漏极， 所述有源层的一端夹设于所述第一电极与所述源极之间， 所 述有源层的另一端夹设于所述第二电极与所述漏极之间， 所述钝化层 覆盖于所述源极、 漏极、 有源层裸露的表面。  [Claim 1] A thin film transistor, comprising a substrate, a gate, a gate insulating layer, a first metal layer, an active layer, a second metal layer, and a passivation layer, and the gate is provided at On the substrate, the gate insulating layer covers the gate, the first metal layer includes a first electrode and a second electrode spaced apart from the gate insulating layer, and the second metal layer includes spaced apart One end of the active layer is sandwiched between the first electrode and the source electrode, and the other end of the active layer is sandwiched between the second electrode and the drain electrode Between the electrodes, the passivation layer covers the exposed surfaces of the source, drain, and active layers.
[权利要求 2] 根据权利要求 1所述的薄膜晶体管， 其特征在于， 所述源极与所述第 一电极接触， 所述漏极与所述第二电极接触。  [Claim 2] The thin film transistor according to claim 1, wherein the source electrode is in contact with the first electrode, and the drain electrode is in contact with the second electrode.
[权利要求 3] 根据权利要求 2所述的薄膜晶体管， 其特征在于， 所述第一金属层与 所述栅绝缘层的黏附性大于所述第二金属层与所述栅绝缘性的黏附性 [Claim 3] The thin film transistor according to claim 2, wherein the adhesion between the first metal layer and the gate insulation layer is greater than the adhesion between the second metal layer and the gate insulation
[权利要求 4] 根据权利要求 3所述的薄膜晶体管， 其特征在于， 所述第二金属层的 材质为铜。 [Claim 4] The thin film transistor according to claim 3, wherein a material of the second metal layer is copper.
[权利要求 5] 根据权利要求 4所述的薄膜晶体管， 其特征在于， 所述第一金属层的 材质选自钼、 铬、 钛中的一种。  [Claim 5] The thin film transistor according to claim 4, wherein a material of the first metal layer is selected from one of molybdenum, chromium, and titanium.
[权利要求 6] 一种阵列基板， 其特征在于， 包括如权利要求 2所述的薄膜晶体管。  [Claim 6] An array substrate, comprising the thin film transistor according to claim 2.
[权利要求 7] 根据权利要求 6所述的阵列基板， 其特征在于， 所述源极与所述第一 电极接触， 所述漏极与所述第二电极接触。 [Claim 7] The array substrate according to claim 6, wherein the source electrode is in contact with the first electrode, and the drain electrode is in contact with the second electrode.
[权利要求 8] 根据权利要求 7所述的阵列基板， 其特征在于， 所述第一金属层与所 述栅绝缘层的黏附性大于所述第二金属层与所述栅绝缘性的黏附性。  [Claim 8] The array substrate according to claim 7, wherein the adhesion between the first metal layer and the gate insulation layer is greater than the adhesion between the second metal layer and the gate insulation .
[权利要求 9] 根据权利要求 8所述的阵列基板， 其特征在于， 所述第二金属层的材 质为铜。  [Claim 9] The array substrate according to claim 8, wherein a material of the second metal layer is copper.
[权利要求 10] 根据权利要求 9所述的薄阵列基板， 其特征在于， 所述第一金属层的 材质选自钼、 铬、 钛中的一种。  [Claim 10] The thin array substrate according to claim 9, wherein a material of the first metal layer is selected from one of molybdenum, chromium, and titanium.
[权利要求 11] 种薄膜晶体管的制备方法， 其特征在于， 所述制备方法包括步骤： 提供一衬底； 在所述衬底上形成栅极和栅绝缘层， 所述栅绝缘层覆盖所述栅极； 在所述栅绝缘层上形成第一金属层， 所述第一金属层包括间隔设置于 所述栅绝缘层上的第一电极和第二电极； [Claim 11] A method for manufacturing a thin film transistor, wherein the method includes the steps of: providing a substrate; Forming a gate and a gate insulating layer on the substrate, the gate insulating layer covering the gate; forming a first metal layer on the gate insulating layer, the first metal layer including a gap disposed on the gate A first electrode and a second electrode on the gate insulation layer;
在所述第一金属层上形成有源层、 第二金属层， 所述第二金属层包括 间隔设置的源极和漏极， 所述有源层的一端夹设于所述第一电极与所 述源极之间， 所述有源层的另一端夹设于所述第二电极与所述漏极之 间；  An active layer and a second metal layer are formed on the first metal layer. The second metal layer includes a source electrode and a drain electrode disposed at intervals. One end of the active layer is sandwiched between the first electrode and the first electrode. Between the sources, the other end of the active layer is sandwiched between the second electrode and the drain;
沉积钝化层， 所述钝化层覆盖于所述源极、 漏极、 有源层裸露的表面  Depositing a passivation layer covering the exposed surfaces of the source, drain, and active layers
[权利要求 12] 根据权利要求 11所述的制备方法， 其特征在于， 在所述第一金属层上 形成有源层、 第二金属层具体包括： [Claim 12] The manufacturing method according to claim 11, wherein forming an active layer on the first metal layer, and the second metal layer specifically include:
在所述第一金属层上沉积有源材料层；  Depositing an active material layer on the first metal layer;
在所述有源材料层上涂布第三光阻层， 通过第三道光罩对所述第三光 阻层进行曝光， 使所述第三光阻层图案化， 形成第三光阻区域； 通过蚀刻制程移除未被所述第三光阻区域覆盖的有源材料层， 形成有 源层， 所述有源层的一端与所述第一电极接触并覆盖部分第一电极， 所述有源层的另一端与所述第二电极接触并覆盖部分第二电极； 在所述栅绝缘层、 第一电极、 第二电极和有源层上沉积第二金属材料 层；  Coating a third photoresist layer on the active material layer, exposing the third photoresist layer through a third photomask, and patterning the third photoresist layer to form a third photoresist region; An active material layer not covered by the third photoresist region is removed by an etching process to form an active layer. One end of the active layer is in contact with the first electrode and covers a portion of the first electrode. The other end of the source layer is in contact with the second electrode and covers part of the second electrode; depositing a second metal material layer on the gate insulating layer, the first electrode, the second electrode, and the active layer;
在所述第二金属材料层上涂布第四光阻层， 通过第四道光罩对所述第 四光阻层进行曝光， 使所述第四光阻层图案化， 形成相互间隔的第四 光阻区域；  A fourth photoresist layer is coated on the second metal material layer, the fourth photoresist layer is exposed through a fourth photomask, and the fourth photoresist layer is patterned to form fourth spacers that are spaced from each other. Photoresist area
通过蚀刻制程移除未被所述第四光阻区域覆盖的第二金属材料层， 形 成第二金属层， 所述第二金属层包括间隔设置的源极和漏极， 所述有 源层的一端夹设于所述第一电极与所述源极之间， 所述有源层的另一 端夹设于所述第二电极与所述漏极之间， 所述源极与所述第一电极接 触， 所述漏极与所述第二电极接触。  The second metal material layer not covered by the fourth photoresist region is removed by an etching process to form a second metal layer. The second metal layer includes a source electrode and a drain electrode disposed at intervals. One end is sandwiched between the first electrode and the source, the other end of the active layer is sandwiched between the second electrode and the drain, and the source and the first The electrode is in contact, and the drain is in contact with the second electrode.
[权利要求 13] 根据权利要求 11所述的制备方法， 其特征在于， 在所述第一金属层上 形成有源层、 第二金属层包括： [Claim 13] The manufacturing method according to claim 11, characterized in that, on the first metal layer Forming an active layer and a second metal layer include:
在所述第一金属层上沉积有源材料层； Depositing an active material layer on the first metal layer;
在所述有源材料层上沉积第二金属材料层； Depositing a second metal material layer on the active material layer;
在所述第二金属材料层上涂覆第三光阻层， 通过第三道光罩对所述第 三光阻层进行灰阶曝光， 使所述第三光阻层图案化， 形成第三光阻区 域， 所述第三光阻区域包括中间部和位于该中间部两侧的侧部， 所述 中间部的厚度小于侧部的厚度； Apply a third photoresist layer on the second metal material layer, perform grayscale exposure on the third photoresist layer through a third mask, and pattern the third photoresist layer to form a third light The third photoresistive region includes a middle portion and side portions on both sides of the middle portion, and the thickness of the middle portion is smaller than the thickness of the side portions;
通过蚀刻制程移除未被所述第三光阻区域覆盖的有源材料层、 第二金 属材料层， 形成有源层， 所述有源层的一端与所述第一电极接触， 所 述有源层的另一端与所述第二电极接触； An active material layer and a second metal material layer not covered by the third photoresist region are removed by an etching process to form an active layer, and one end of the active layer is in contact with the first electrode, and The other end of the source layer is in contact with the second electrode;
对所述第三光阻区域进行灰化处理， 以去除中间部并减少侧部的厚度 ， 保留部分侧部； Performing ashing treatment on the third photoresist region to remove the middle portion and reduce the thickness of the side portion, and to retain a portion of the side portion;
通过蚀刻制程移除未被所述部分侧部覆盖的第二金属材料层， 形成第 二金属层， 所述第二金属层包括间隔设置的源极和漏极， 所述有源层 的一端夹设于所述第一电极与所述源极之间， 所述有源层的另一端夹 设于所述第二电极与所述漏极之间。 The second metal material layer not covered by the partial side is removed by an etching process to form a second metal layer, the second metal layer includes a source electrode and a drain electrode spaced apart, and one end of the active layer is clamped. It is provided between the first electrode and the source electrode, and the other end of the active layer is sandwiched between the second electrode and the drain electrode.
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