CN109873001A - Array substrate and preparation method thereof - Google Patents
Array substrate and preparation method thereof Download PDFInfo
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- CN109873001A CN109873001A CN201910141227.0A CN201910141227A CN109873001A CN 109873001 A CN109873001 A CN 109873001A CN 201910141227 A CN201910141227 A CN 201910141227A CN 109873001 A CN109873001 A CN 109873001A
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- 239000000758 substrate Substances 0.000 title claims abstract description 76
- 238000002360 preparation method Methods 0.000 title abstract description 12
- 239000010410 layer Substances 0.000 claims abstract description 228
- 239000011241 protective layer Substances 0.000 claims abstract description 98
- 229920002120 photoresistant polymer Polymers 0.000 claims description 62
- 229910052751 metal Inorganic materials 0.000 claims description 33
- 239000002184 metal Substances 0.000 claims description 33
- 238000004519 manufacturing process Methods 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 25
- 229910044991 metal oxide Inorganic materials 0.000 claims description 18
- 150000004706 metal oxides Chemical class 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 8
- 239000007791 liquid phase Substances 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims description 4
- 230000008859 change Effects 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 description 15
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 12
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 239000004411 aluminium Substances 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 7
- 229910052733 gallium Inorganic materials 0.000 description 7
- 229910052738 indium Inorganic materials 0.000 description 7
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 7
- 239000004973 liquid crystal related substance Substances 0.000 description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 description 6
- 239000011787 zinc oxide Substances 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- 239000011733 molybdenum Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 229920001621 AMOLED Polymers 0.000 description 3
- 239000002994 raw material Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000005265 energy consumption Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 238000010422 painting Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention provides a kind of array substrates and preparation method thereof.The array substrate includes gate insulating layer, active layer, source-drain electrode, the first protective layer and the second protective layer.The active layer and the source-drain electrode are set on the gate insulating layer, and the source-drain electrode is connected to the active layer.First protective layer is set on the gate insulating layer and the active layer.Second protective layer is set on the source-drain electrode and first protective layer.
Description
Technical field
The present invention relates to display field, especially a kind of array substrate and preparation method thereof.
Background technique
Liquid crystal display device (Liquid Crystal Display, abbreviation LCD) has thin fuselage, power saving, radiationless etc.
Many merits are widely used, such as: mobile phone, personal digital assistant (PDA), digital camera, computer screen or
Laptop screen etc..
Organic Light Emitting Diode (Organic Light-Emitting Diode, abbreviation OLED) display, also referred to as has
Electroluminescent display is a kind of emerging panel display apparatus, due to its simple with preparation process, at low cost, power consumption
It is low, light emission luminance is high, operating temperature wide adaptation range, volume are frivolous, fast response time, and be easily achieved colored display and big
Screen shows, is easily achieved and matches with driver ic, is easily achieved the advantages that Flexible Displays, thus has wide
Application prospect.
OLED can be divided into passive matrix OLED (Passive Matrix Organic Light- according to driving method
Emitting Diode, abbreviation PMOLED) and active array type OLED (Active Matrix Organic Light-
Emitting Diode, abbreviation AMOLED) two major classes, i.e. directly addressing and film transistor matrix two classes of addressing.Wherein,
AMOLED has the pixel in array arrangement, belongs to active display type, and luminous efficacy is high, is typically used as high-definition big
Size finder.
Thin film transistor (TFT) (Thin Film Transistor, abbreviation TFT) is current liquid crystal display device and active matrix
Main driving element in type OLED display, is directly related to the developing direction of high performance flat display device.Film is brilliant
Body pipe has various structures, and the material for preparing the thin film transistor (TFT) of corresponding construction also has a variety of, and amorphous silicon (a-Si) material is
Relatively common one kind.
As liquid crystal display device and OLED display develop towards large scale and high-resolution direction, traditional a-
The mobility that Si only has the left and right 1cm2/ (Vs) can no longer meet requirement, with indium gallium zinc oxide (Indium Gallium
Zinc Oxide, abbreviation IGZO) have for the metal oxide materials of representative more than the mobility more than 10cm2/ (Vs), and
The good compatibility of the preparation of respective films transistor and the producing line that existing a-Si is semiconductor driving, rapidly becomes aobvious in recent years
Show the emphasis of field research and development.
It is had the advantage that relative to traditional a-Si TFT, IGZO TFT
1, the resolution ratio for improving display backboard, under the premise of guaranteeing identical transmitance, IGZO TFT shows point of backboard
Resolution can accomplish the 2 times or more of a-Si TFT, and the carrier concentration in IGZO material is high, and mobility is big, can reduce TFT's
Volume guarantees the promotion of resolution ratio；
2, the energy consumption of display device is reduced, for IGZO TFT compared with a-Si TFT, LTPS TFT, leakage current is less than 1pA；It drives
Dynamic frequency is reduced to 2-5Hz by original 30-50Hz, passes through special process, it might even be possible to reach 1Hz, although reducing the drive of TFT
Dynamic number, still can maintain the orientation of liquid crystal molecule, not influence the quality of picture, to reduce the power consumption of display backboard；
In addition, the high mobility of IGZO semiconductor material makes the TFT of smaller size can provide enough charging abilities and higher
Capacitance, and improve the aperture opening ratio of liquid crystal display panel, the effective area that light penetrates becomes larger, can with less back board module or
Low power consumption reaches identical brightness, reduces energy consumption；
3, by using modes such as intermittent drivings, the noise that can reduce liquid crystal display drive circuit examines touch screen
It being influenced caused by slowdown monitoring circuit, the ball pen tip of the brushstyle of a writing or painting that higher sensitivity or even tip may be implemented also is able to respond, and due to
Picture without update when can cut off the power, therefore its showed in energy-efficient effect it is more outstanding.
Currently, IGZO generally uses etch stopper type as the TFT of semiconductor active layer, due to there is etching barrier layer
(Etch Stop Layer, ESL) exists, the etching process of source-drain electrode, etching barrier layer can be effectively protected IGZO not by
To influence, guarantee that TFT has excellent characteristic of semiconductor.But the preparation process of the IGZO TFT of ESL type is complex, needs
By 6 yellow light techniques, it is unfavorable for reducing cost, therefore industry is generally pursued that light shield technique is less, cost is lower, device lean
The exploitation of the IGZO TFT of high back channel etching (Back Channel Etch, the BCE) type of change degree.
But BCE type IGZO TFT in the prior art is because back channel is needed by the damage for the techniques such as etching subsequent
Protective layer deposition process in using oxygen plasma bombardment will carry on the back channel passivation, and this technique simultaneously can be to IGZO TFT
Chinese raw materials is that the source-drain electrode of metal causes oxidation equivalent damage, so as to cause the binding force between protective layer and source-drain electrode layer
There is the problems such as film layer bulge falls off in difference, and promotes the bad stability of IGZO TFT.
Summary of the invention
The object of the present invention is to provide a kind of array substrates and preparation method thereof, to solve in the prior art due to protective layer
Oxidation equivalent damage is caused to source-drain electrode, it is poor so as to cause the binding force between protective layer and source-drain electrode layer, promote indium gallium zinc
The problems such as bad stability of oxide thin film transistor.
To achieve the above object, the present invention provides a kind of array substrate comprising gate insulating layer, active layer, source and drain electricity
Pole, the first protective layer and the second protective layer.The active layer and the source-drain electrode are set on the gate insulating layer, institute
It states source-drain electrode and is connected to the active layer.First protective layer is set on the gate insulating layer and the active layer.Institute
The second protective layer is stated on the source-drain electrode and first protective layer.
Further, the array substrate further includes substrate, grid and pixel electrode.The grid is set to the substrate
On, the gate insulating layer is set in the substrate, and covers the grid.The pixel electrode is set to second protective layer
On, and connect with the source-drain electrode.
The present invention also provides a kind of production methods of array substrate as described above comprising following steps:
Form gate insulating layer.
Active layer is formed on the gate insulating layer.
Source-drain electrode is formed on the gate insulating layer, with photoresist layer on the source-drain electrode, and the source and drain is electric
Pole is connected to the active layer.
The first protective layer is formed on the gate insulating layer, the active layer and the photoresist layer.
Remove first protective layer on the photoresist layer and photoresist layer.
The second protective layer is formed on first protective layer and the source-drain electrode.
It further, include: to deposit a metal layer on the active layer in forming source-drain electrode step, in the gold
Belong to and be coated with a photoresist layer on layer, and by the photoresist pattern layers, is then formed the etching metal layer by wet etching
The source-drain electrode remains extra photoresist layer on the source-drain electrode.
It further, include: to pass through in removing the first protective layer step on the photoresist layer and photoresist layer
Liquid phase stripping method removes first protective layer on the photoresist layer and the photoresist layer on the source-drain electrode.
Further, it is described prepare it is further comprising the steps of before gate insulating layer step:
One substrate is provided.Grid is formed on the substrate.
It is further comprising the steps of after forming the second protective layer step:
It forms pixel electrode: forming pixel electrode, and the pixel electrode and the source and drain on second protective layer
Electrode connection.
The present invention also provides the production methods of another array substrate as described above comprising following steps:
Form gate insulating layer.
Active layer and source-drain electrode are formed on the gate insulating layer, there is photoresist layer on the source-drain electrode.
The first protective layer is formed on the gate insulating layer, the active layer and the photoresist layer.
Remove first protective layer on the photoresist layer and photoresist layer.
The second protective layer is formed on first protective layer and the source-drain electrode.
Further, include: in forming active layer and source-drain electrode step
A metal oxide layer is formed in the gate insulating layer.
A metal layer is deposited on the metal oxide layer.
It is coated with a photoresist layer on the metal layer, and by the photoresist pattern layers, then passes through intermediate tone mask method
Simultaneously by the metal oxide layer and described metal layer patterning, the active layer and the source-drain electrode, the source are formed
Remain extra photoresist layer on drain electrode.
It further, include: to pass through in removing the first protective layer step on the photoresist layer and photoresist layer
Liquid phase stripping method removes first protective layer on the photoresist layer and the photoresist layer on the source-drain electrode.
Further, further include step in the gate insulating layer step money for preparing:
One substrate is provided.Grid is formed on the substrate.
It is further comprising the steps of after forming the second protective layer step:
It forms pixel electrode: forming pixel electrode, and the pixel electrode and the source and drain on second protective layer
Electrode connection.
The invention has the advantages that a kind of array substrate provided in the present invention, real respectively by two layers of protective layer of deposition
Now it is passivated two kinds of functions of active layer and covering protection metal layer.Wherein, passivation active layer is realized by the first protective layer, then passed through
Second protective layer realizes covering protection source-drain electrode.The production method of the array substrate is additionally provided in the present invention, at it
It is passivated its active layer without using oxygen plasma bombardment in production method, only need to deposit two layers of protective layer respectively, it will not be right
Source-drain electrode causes oxidation equivalent damage, the binding force between protective layer and source-drain electrode layer is increased, from without bulge
The problems such as falling off improves the production yield and stability of product, promotes user experience.
Detailed description of the invention
Fig. 1 is the layer structure schematic diagram of array substrate in the embodiment of the present invention 1 or 2；
Fig. 2 is the flow diagram of array substrate manufacturing method in the embodiment of the present invention 1；
Fig. 3 is the flow diagram of array substrate manufacturing method in the embodiment of the present invention 2.
Component is expressed as follows in figure:
Array substrate 100；
Substrate 1；Grid 2；
Gate insulating layer 3；Active layer 4；
Source-drain electrode 5；First protective layer 6；
Second protective layer 7；Pixel electrode 8.
Specific embodiment
The preferred embodiment of the present invention is introduced below with reference to Figure of description, it was demonstrated that the present invention can be implemented, the invention
Embodiment can keep its technology contents more clear and be easy to understand to the those of skill in the art complete description present invention.
The present invention can be emerged from by many various forms of inventive embodiments, and protection scope of the present invention is not limited only to text
In the embodiment mentioned.
In the accompanying drawings, the identical component of structure is indicated with same numbers label, everywhere the similar component of structure or function with
Like numeral label indicates.The size and thickness of each component shown in the drawings are to be arbitrarily shown, and there is no limit by the present invention
The size and thickness of each component.Apparent in order to make to illustrate, some places suitably exaggerate the thickness of component in attached drawing.
In addition, the explanation of following inventive embodiments is to can be used to implement to illustrate the present invention with reference to additional diagram
Specific inventive embodiments.Direction terms mentioned in the present invention, for example, "upper", "lower", "front", "rear", "left", "right",
"inner", "outside", " side " etc. are only the directions with reference to annexed drawings, and therefore, the direction term used is in order to more preferable, more clear
Illustrate to Chu and understand the present invention, rather than indicates or imply signified device or element and must have a particular orientation, with spy
Fixed orientation construction and operation, therefore be not considered as limiting the invention.In addition, term " first ", " second ", " third "
Etc. being used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance.
When certain components are described as " " another component "upper", the component can be placed directly within another component
On；There may also be an intermediate member, the component is placed on the intermediate member, and the intermediate member is placed in another component
On.When a component is described as " installation to " or " being connected to " another component, the two can be understood as direct " installation " or
" connection " or a component " are installed extremely " indirectly by an intermediate member or " being connected to " another component.
Embodiment 1
As shown in Figure 1, providing a kind of array substrate 100 in the embodiment of the present invention, the array substrate 100 includes that grid is exhausted
Edge layer 3, active layer 4, source-drain electrode 5, the first protective layer 6 and the second protective layer 7.
The gate insulating layer 3 can be the materials such as silica, silicon nitride, aluminium oxide.The active layer 4 and the source and drain
Electrode 5 be set to the gate insulating layer 3 on, and the source-drain electrode 5 be located at the active layer 4 both ends and with it is described active
Layer 4 connects.Wherein, the material of the active layer 4 is metal oxide, and the metal oxide is indium gallium zinc oxide.It is described
The raw material of source-drain electrode 5 are metal, and the metal is aluminium or copper.First protective layer 6 is set to 3 He of gate insulating layer
On the active layer 4, for being passivated and protecting the active layer 4.Second protective layer 7 is set to the source-drain electrode 5 and institute
It states on the first protective layer 6, for source-drain electrode 5 described in covering protection.
The array substrate 100 further includes substrate 1, grid 2 and pixel electrode 8.The substrate 1 can be substrate of glass
1, flexible substrates 1 etc..The grid 2 is set in the substrate 1, and the gate insulating layer 3 is set in the substrate 1 and covering institute
Grid 2 is stated, the grid 2 can be the alloy of any metal or two or more compositions in molybdenum, aluminium, copper, silver etc..It is described
Pixel electrode 8 is set on second protective layer 7, and is connect with the source-drain electrode 5.
The present invention also provides a kind of production method of array substrate as described above 100 in implementing, the production method
Process is as shown in Fig. 2, specific production step includes:
Step S101) substrate 1 is provided, the substrate 1 can be substrate of glass 1, flexible substrates 1 etc..
Step S102) form grid 2: form a grid 2 in the substrate 1, the material of the grid 2 can for molybdenum,
Any one metal or the two or more alloys being composed in aluminium, copper, silver etc..
Step S103) form gate insulating layer 3: a gate insulating layer 3 is formed on the base, while the grid is exhausted
Edge layer 3 is covered on the grid 2, and the material of the gate insulating layer 3 can be silica, silicon nitride, aluminium oxide etc..
Step S104) it is formed on active layer 4: a metal oxide layer, the metal are deposited on the gate insulating layer 3
The material of oxide skin(coating) is indium gallium zinc oxide.Then will be described metal oxide patterning, form the active layer 4.
Step S105) form source-drain electrode 5: a metal layer is deposited on the gate insulating layer 3, the metal layer is simultaneously
It is covered on the active layer 4.The material of the metal layer can be one of aluminium or copper.Then it applies on the metal layer
One photoresist layer of cloth, and by exposure, development by the photoresist pattern layers, the photoresist layer is insulating materials.Finally by wet
Method is etched the etching metal layer, forms the source-drain electrode 5.The source-drain electrode 5 is located at the both ends of the active layer 4,
And it is connect with the active layer 4.Remain extra photoresist layer on the source-drain electrode 5.
Step S106) form the first protective layer 6: by chemical vapour deposition technique in the gate insulating layer 3, described active
One first protective layer 6 is deposited on layer 4 and the photoresist layer.
Step S107) first protective layer 6 on the removal photoresist layer and photoresist layer: passing through liquid phase stripping method will
The first protective layer 6 removing on the photoresist layer and the photoresist layer on the source-drain electrode 5.
Step S108) form the second protective layer 7: by chemical vapour deposition technique in first protective layer 6 and the source
One second protective layer 7 is formed on drain electrode 5, then patterns second protective layer 7.
Step S109) form pixel electrode 8: pixel electrode 8, and pixel electricity are formed on second protective layer 7
Pole 8 is connect with the source-drain electrode 5.
In embodiments of the present invention, provide a kind of array substrate 100 with and preparation method thereof.The array substrate 100
On deposited two layers of protective layer, wherein by the first protective layer 6 realize passivation active layer 4, then by the second protective layer 7 realize
Covering protection source-drain electrode 5.It is passivated its active layer 4 without using oxygen plasma bombardment in its production method, need to only be divided
Two layers of protective layer is not deposited, and oxidation equivalent damage will not be caused to source-drain electrode 5, is increased between protective layer and 5 layers of source-drain electrode
Binding force promote user experience from the production yield and stability for the problems such as falling off without bulge, improving product
Sense.
Embodiment 2
As shown in Figure 1, providing a kind of array substrate 100 in the embodiment of the present invention, the array substrate 100 includes that grid is exhausted
Edge layer 3, active layer 4, source-drain electrode 5, the first protective layer 6 and the second protective layer 7.
The gate insulating layer 3 can be the materials such as silica, silicon nitride, aluminium oxide.The active layer 4 and the source and drain
Electrode 5 be set to the gate insulating layer 3 on, and the source-drain electrode 5 be located at the active layer 4 both ends and with it is described active
Layer 4 connects.Wherein, the material of the active layer 4 is metal oxide, and the metal oxide is indium gallium zinc oxide.It is described
The raw material of source-drain electrode 5 are metal, and the metal is aluminium or copper.First protective layer 6 is set to 3 He of gate insulating layer
On the active layer 4, for being passivated and protecting the active layer 4.Second protective layer 7 is set to the source-drain electrode 5 and institute
It states on the first protective layer 6, for source-drain electrode 5 described in covering protection.
The array substrate 100 further includes substrate 1, grid 2 and pixel electrode 8.The substrate 1 can be substrate of glass
1, flexible substrates 1 etc..The grid 2 is set in the substrate 1, and the gate insulating layer 3 is set in the substrate 1 and covering institute
Grid 2 is stated, the grid 2 can be the alloy of any metal or two or more compositions in molybdenum, aluminium, copper, silver etc..It is described
Pixel electrode 8 is set on second protective layer 7, and is connect with the source-drain electrode 5.
The present invention also provides a kind of production method of array substrate as described above 100 in implementing, the production method
Process is as shown in figure 3, specific production step includes:
Step S201) substrate 1 is provided, the substrate 1 can be substrate of glass 1, flexible substrates 1 etc..
Step S202) form grid 2: form a grid 2 in the substrate 1, the material of the grid 2 can for molybdenum,
Any one metal or the two or more alloys being composed in aluminium, copper, silver etc..
Step S203) form gate insulating layer 3: a gate insulating layer 3, while the grid are formed in the substrate 1
Insulating layer 3 is covered on the grid 2, and the material of the gate insulating layer 3 can be silica, silicon nitride, aluminium oxide etc..
Step S204) form active layer 4 and source-drain electrode 5: a metal oxide is deposited on the gate insulating layer 3
Layer, the metal oxide are indium gallium zinc oxide.A metal layer is deposited on the metal oxide layer again, the metal can
Think one of aluminium or copper.Then it is coated with a photoresist layer on the metal layer, and by exposing, developing the photoresist layer
Patterning, the photoresist layer are insulating materials.Finally by intermediate tone mask method (Half-tone Mask) in one of light shield journey
By the metal oxide layer and described metal layer patterning under sequence, the metal oxide layer forms the active layer 4, described
Metal layer forms the source-drain electrode 5.The source-drain electrode 5 is located at the both ends of the active layer 4, and connects with the active layer 4
It connects.Remain extra photoresist layer on the source-drain electrode 5.
Step S205) form the first protective layer 6: by chemical vapour deposition technique in the gate insulating layer 3, described active
One first protective layer 6 is deposited on layer 4 and the photoresist layer.
Step S206) first protective layer 6 on the removal photoresist layer and photoresist layer: passing through liquid phase stripping method will
The first protective layer 6 removing on the photoresist layer and the photoresist layer on the source-drain electrode 5.
Step S207) form the second protective layer 7: by chemical vapour deposition technique in first protective layer 6 and the source
One second protective layer 7 is formed on drain electrode 5, then patterns second protective layer 7.
Step S208) form pixel electrode 8: pixel electrode 8, and pixel electricity are formed on second protective layer 7
Pole 8 is connect with the source-drain electrode 5.
The production method provided in the embodiment of the present invention, by intermediate tone mask method by the gold under one to light shield program
Belong to oxide skin(coating) and the metal layer etches simultaneously, while generating in the active layer 4 and the source-drain electrode 5, with embodiment 1
Production method compare and reduce preparation step, preparation flow is simpler.
In embodiments of the present invention, provide a kind of array substrate 100 with and preparation method thereof.The array substrate 100
On deposited two layers of protective layer, wherein by the first protective layer 6 realize passivation active layer 4, then by the second protective layer 7 realize
Covering protection source-drain electrode 5.It is passivated its active layer 4 without using oxygen plasma bombardment in its production method, need to only be divided
Two layers of protective layer is not deposited, and oxidation equivalent damage will not be caused to source-drain electrode 5, is increased between protective layer and 5 layers of source-drain electrode
Binding force promote user experience from the production yield and stability for the problems such as falling off without bulge, improving product
Sense.
Although describing the present invention herein with reference to specific embodiment, it should be understood that, these realities
Apply the example that example is only principles and applications.It should therefore be understood that can be carried out to exemplary embodiment
Many modifications, and can be designed that other arrangements, without departing from spirit of the invention as defined in the appended claims
And range.It should be understood that different appurtenances can be combined by being different from mode described in original claim
Benefit requires and feature described herein.It will also be appreciated that the feature in conjunction with described in separate embodiments can be used
In other described embodiments.
Claims (10)
1. a kind of array substrate characterized by comprising
Gate insulating layer；
Active layer and source-drain electrode are set on the gate insulating layer, and the source-drain electrode is connected to the active layer；
First protective layer is set on the gate insulating layer and the active layer；And
Second protective layer is set on the source-drain electrode and first protective layer.
2. array substrate as described in claim 1, which is characterized in that further include:
Substrate；And
Grid is set in the substrate, and the gate insulating layer is set in the substrate and the covering grid；
Pixel electrode is set on second protective layer, and connect with the source-drain electrode.
3. a kind of production method of array substrate as described in claim 1, which comprises the following steps:
Form gate insulating layer；
Active layer is formed on the gate insulating layer；
Source-drain electrode is formed on the gate insulating layer, with photoresist layer on the source-drain electrode, and the source-drain electrode connects
It is connected to the active layer；
The first protective layer is formed on the gate insulating layer, the active layer and the photoresist layer；
Remove first protective layer on the photoresist layer and photoresist layer；
The second protective layer is formed on first protective layer and the source-drain electrode.
4. the production method of array substrate as claimed in claim 3, which is characterized in that wrapped in forming source-drain electrode step
It includes: depositing a metal layer on the active layer, be coated with a photoresist layer on the metal layer, and by the photoresist layer pattern
Change, the etching metal layer is then formed, it is extra to remain on the source-drain electrode by the source-drain electrode by wet etching
Photoresist layer.
5. the production method of array substrate as claimed in claim 3, which is characterized in that removing the photoresist layer and photoresist
Include: in the first protective layer step on layer by liquid phase stripping method by the source-drain electrode the photoresist layer and
First protective layer removing on the photoresist layer.
6. the production method of array substrate as claimed in claim 3, which is characterized in that
It is described prepare it is further comprising the steps of before gate insulating layer step:
One substrate is provided；
Grid is formed on the substrate；
It is further comprising the steps of after forming the second protective layer step:
Pixel electrode is formed on second protective layer, and the pixel electrode is connect with the source-drain electrode.
7. a kind of production method of array substrate as described in claim 1, which comprises the following steps:
Form gate insulating layer；
Active layer and source-drain electrode are formed on the gate insulating layer, there is photoresist layer on the source-drain electrode；
The first protective layer is formed on the gate insulating layer, the active layer and the photoresist layer；
Remove first protective layer on the photoresist layer and photoresist layer；
The second protective layer is formed on first protective layer and the source-drain electrode.
8. the production method of array substrate as claimed in claim 7, which is characterized in that
Include: in forming active layer and source-drain electrode step
A metal oxide layer is formed in the gate insulating layer；
A metal layer is deposited on the metal oxide layer；
It is coated with a photoresist layer on the metal layer, and by the photoresist pattern layers, then simultaneously by intermediate tone mask method
By the metal oxide layer and described metal layer patterning, the active layer and the source-drain electrode, the source and drain electricity are formed
Remain extra photoresist layer on extremely.
9. the production method of array substrate as claimed in claim 7, which is characterized in that removing the photoresist layer and photoresist
Include: in the first protective layer step on layer by liquid phase stripping method by the source-drain electrode the photoresist layer and
First protective layer removing on the photoresist layer.
10. such as the production method for the array substrate that claim 7 is stated, which is characterized in that
Further include step in the gate insulating layer step money for preparing:
One substrate is provided；
Grid is formed on the substrate；
It is further comprising the steps of after forming the second protective layer step:
Pixel electrode is formed on second protective layer, and the pixel electrode is connect with the source-drain electrode.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910141227.0A CN109873001A (en) | 2019-02-26 | 2019-02-26 | Array substrate and preparation method thereof |
| PCT/CN2019/082419 WO2020172959A1 (en) | 2019-02-26 | 2019-04-12 | Array substrate and method for manufacturing same, and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910141227.0A CN109873001A (en) | 2019-02-26 | 2019-02-26 | Array substrate and preparation method thereof |
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| CN109873001A true CN109873001A (en) | 2019-06-11 |
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| CN201910141227.0A Pending CN109873001A (en) | 2019-02-26 | 2019-02-26 | Array substrate and preparation method thereof |
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- 2019-04-12 WO PCT/CN2019/082419 patent/WO2020172959A1/en active Application Filing
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| US6818923B2 (en) * | 2002-04-17 | 2004-11-16 | Lg. Philips Lcd Co., Ltd. | Thin film transistor array substrate and manufacturing method thereof |
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| WO2020172959A1 (en) | 2020-09-03 |
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