CN108804025B

CN108804025B - Method for reducing retention errors of flash memory and solid state disk

Info

Publication number: CN108804025B
Application number: CN201810188565.5A
Authority: CN
Inventors: 许毅; 姚兰; 郑春阳
Original assignee: Shenzhen Union Memory Information System Co Ltd
Current assignee: Shenzhen Union Memory Information System Co Ltd
Priority date: 2018-03-07
Filing date: 2018-03-07
Publication date: 2021-10-01
Anticipated expiration: 2038-03-07
Also published as: CN108804025A

Abstract

The invention discloses a method for reducing retention errors of a flash memory and a solid state disk.A background self-checking operation is used for checking whether data have errors or not, if the data have errors, error correction is carried out through an error correction algorithm, and the method is characterized in that the background self-checking control is triggered in an idle state and a forced state, and the background self-checking checks a data space of M size each time; the forced state is forcibly started at different time intervals according to the erasing times of the whole hard disk, and the larger the erasing times, the smaller the time interval. The efficiency of in-place writing is higher than that of writing to a new physical page, the corrected data is still in place, the mapping relation with the logical address is not changed, and then invalid physical pages cannot be generated in the physical block, so that a garbage disposal mechanism in the solid state disk cannot be triggered.

Description

Method for reducing retention errors of flash memory and solid state disk

Technical Field

The invention relates to the technical field of storage, in particular to a method for reducing retention errors of a flash memory and a solid state disk.

Background

The Flash cell uses the voltage value of a Floating Gate Transistor (Floating Gate Transistor) to represent the stored data, and the Flash cell of an mlc (multi Level cell) Flash memory can store two bit values: least Significant bit LSB (least Significant bit) and most Significant bit MSB (most Significant bit), fig. 1 is a schematic diagram of FLASH cells of a FLASH memory of MLC, each FLASH cell includes an LSB and an MSB, and each bit has two states, so that a FLASH cell has four states. Fig. 2 is a schematic voltage distribution diagram of a memory cell of a Flash memory of an MLC, where a Flash cell has four states represented by different voltages, specifically: state 1 is the erased state, the voltage value is 0, the stored bit value is 11, state 2 or state 3 is the incomplete writing state, the voltage value is between the erased state and the complete state, the stored bit value is 10 or 01, state 4 is the complete state, the voltage is the maximum, the stored bit value is 00, wherein reference voltage 1, reference voltage 2, reference voltage 3 is a reference value given by the particle manufacturer, if the floating gate transistor voltage is at a value less than 1, reference voltage, then 11 data is considered stored, if the floating gate transistor voltage value is between [ reference voltage 1, reference voltage 2], then 10 data is considered to be stored, if the floating gate transistor voltage value is between [ reference voltage 2, reference voltage 3], then 01 data is deemed to be stored, if the floating gate transistor voltage value is greater than reference voltage 3, then 00 data is considered to be stored.

The Retention error (Retention error) is: if the Flash memory is not used for a long time, for example, the Flash memory is in a power-down state for a long time, electrons in the Flash cell leak, the voltage value of the Flash cell decreases, the distribution state shifts to the left, for example, 00 shifts to 01,10 shifts to 11, that is, data stored in the Flash memory has errors, and a retention error is a characteristic of the Flash memory.

As described above, the Retention error (Retention error) is: if the Flash memory is not used for a long time (for example, in a long-term power-down state), the electronic in the Flash cell leaks, the voltage value thereof decreases, and the distribution state shifts to the left, fig. 3 is a schematic diagram showing a retention error, for example, if data written in a certain Flash cell is 01, which is a state 3, and the voltage value is between [ reference voltage 2, reference voltage 3], then the solid state disk is in an occasional use state, that is, powered on occasionally, and the Flash cell is not read and written during the power-on period, the electronic in the Flash cell gradually leaks, the voltage gradually decreases, when the change lasts long enough, the voltage thereof is certainly smaller than the reference voltage 2, that is, the Flash cell changes from the state 3 to the state 2, as shown in fig. 3, then if the Flash cell is read, the read voltage thereof is found to be between [ reference voltage 1, reference voltage 2], the stored data is determined to be 10, i.e. data error occurred! Usually, solid state disks are all provided with error correction algorithms, if the error bits generated in a physical page are not too many, the error correction algorithms can correct the errors and transmit the corrected errors to a host, but the retention errors have the characteristics that the longer the retention (power failure) time is, the more serious the electronic leakage is, the more bits with errors are, and when the error correction algorithms can not be corrected, the errors really occur!

In the prior art, a self-adaptive dynamic self-checking algorithm is adopted in a solid state disk to detect a flash memory, so that possible retention errors are found and eliminated in advance, and once the retention errors are accumulated to a certain degree, data are corrected and then rewritten into a new physical page. The method can effectively reduce the occurrence of retention errors, but has the obvious defect that corrected data is written into a new physical page, the original old physical page is marked as invalid, a garbage recovery mechanism of the solid state disk can erase the block where the old physical page is located sooner or later, particularly in the later life period of large P/E number (erase value, flash memory block must be erased and then written), the retention errors are accumulated more and more quickly, and the frequent scheduling of a garbage recovery strategy can seriously affect the read-write performance of a host.

Disclosure of Invention

In view of the above drawbacks, the present invention is directed to how to reduce retention errors of a solid state disk.

In order to achieve the purpose, the invention provides a method for reducing retention errors of a flash memory, which is characterized in that a background self-check operation background is used for checking whether data stored in a solid state disk is in error or not, if the data is in error, error correction is carried out through an error correction algorithm, the method is characterized in that the background self-check control is triggered in an idle state and triggered in a forced state, the background self-check checks a data space with the size of M each time, M in the idle state is selected to be M1, M2 is selected in the forced state, and M2 is 0.2M 1-0.6M 1; the forced state is forcibly started at different time intervals according to the erasing times of the whole hard disk, and the larger the erasing times, the smaller the time interval.

The method for reducing the retention error of the flash memory is characterized in that a background self-checking operation background only checks valid data stored in the whole disk of the solid state disk, and ignores invalid data and data pages which are not stored.

The method for reducing the retention error of the flash memory is characterized in that M1 is selected to be 10MB, and M2 is selected to be 5 MB; the erasing times of the whole hard disk are the total erasing times of the solid state disk or the average erasing times of each block.

The method for reducing the retention errors of the flash memory is characterized in that after the background self-checking operation detects that the data have errors, the error correction is carried out through an error correction algorithm, and the corrected data are directly written back to the original physical page.

A solid hard disk is characterized in that a method for reducing retention errors of a flash memory is adopted, whether data stored in the whole disk of the solid hard disk are in errors is checked through a background self-checking operation background, if the data are in errors, error correction is carried out through an error correction algorithm, the background self-checking control is triggered in an idle state and triggered in a forced state, the background self-checking checks a data space with the size of M each time, M in the idle state is selected to be M1, M2 in the forced state is selected, and M2 is 0.2M 1-0.6M 1; the forced state is forcibly started at different time intervals according to the erasing times of the whole hard disk, and the larger the erasing times, the smaller the time interval.

The solid state disk is characterized in that the background self-checking operation background only checks valid data stored in the whole solid state disk, and ignores invalid data and data pages which are not stored.

The solid hard disk is characterized in that M1 is 10MB, and M2 is 5 MB; the erasing times of the whole hard disk are the total erasing times of the solid state disk or the average erasing times of each block.

The solid hard disk is characterized in that after the background self-checking operation detects that data are wrong, error correction is carried out through an error correction algorithm, the original physical page is not erased, and the data after error correction are directly written back to the original physical page.

The invention has the beneficial effects that: the efficiency of in-place writing is higher than the efficiency of writing to a new physical page, and what is more critical is that compared with the prior art, the corrected data is still in place, the mapping relation with the logical address is not changed, and then an invalid physical page cannot be generated in the physical block, so that a garbage disposal mechanism in the solid state disk cannot be triggered, and by matching with a dynamic self-adaptive self-detection mechanism in the prior art, the occurrence of retention errors can be effectively reduced, the performance of a host computer cannot be influenced, and the life cycle of the flash memory can be indirectly improved.

Drawings

FIG. 1 is a schematic diagram of a FLASH cell of a FLASH memory of MLC;

FIG. 2 is a schematic voltage distribution of a memory cell of a flash memory of MLC;

FIG. 3 is a schematic diagram of the occurrence of a retention error;

FIG. 4 is a graph of the relationship of factors affecting retention errors;

FIG. 5 is a flow diagram of a firmware background self-test;

FIG. 6 is a schematic diagram of a data writing process;

FIG. 7 is a background self-test flow diagram for in-place writes.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Fig. 4 is a relationship diagram of factors affecting retention errors, where the X-axis is the number of erase times P/E, and the Y-axis is BER (Bit Error Rate, the proportion of Bit flipping errors, which characterizes the data reliability of flash memory, and the smaller the data, the more reliable the data), as can be seen from the diagram: 1. the retention error is closely related to the P/E value, and the larger the P/E value is, the larger the proportion of the occurrence of Bit upset is. 2. The retention error is closely related to the retention time, and the longer the retention time is, the larger the proportion of the occurrence of Bit inversion.

Analysis shows that the retention errors are accumulated slowly along with time and gradually exceed the error correction capability of an error correction algorithm, so that the whole disk data is read by adding a periodic background, whether the data have errors is detected, if the errors do not occur, no operation is performed, otherwise, whether the occurring errors are about to exceed the error correction capability of the error correction algorithm is judged, because the error correction capability is known under the condition that the error correction algorithm is known, if the error correction capability is far not reached, no operation is performed, if the error correction capability of the error correction algorithm is about to be reached, the error correction algorithm is started to correct the data, then the corrected data is written into a new physical address, and the step of performing background self-check on a certain physical page is performed.

Due to the fact that background self-checking is added, normal host read-write requests cannot be influenced, however, under certain scenes, for example, a data center host always has read-write requests, if background self-checking is not started all the time, the time is long, retention errors are inevitably generated, and therefore comprehensive consideration is given to the fact that triggering conditions of the background self-checking are as follows:

1: triggering when the system is idle, namely starting when no host request exists, meanwhile, in order to not influence the subsequent possible read-write request efficiency, dividing the background self-check into a plurality of sections, setting each section as 10MB data volume, self-checking one section each time when the system is idle, then quitting the task, trying to respond to the front-end request, if no request exists, continuing to self-check the next section, and the firmware needs to remember the self-check process.

2: setting a time threshold and a start timestamp, when a host continues to have a read-write request, an idle period can not be generated, but a retention error can not be generated, so that the firmware needs to time, when the time exceeds the threshold, background self-checking is forcibly carried out, and the data volume of each self-checking section needs to be smaller to be 5MB in order to not influence the host request as much as possible. Secondly, the setting of the threshold is also set differently, it can be seen from fig. 4 that the retention errors are closely related to the number of P/es, and assuming that the error correction capability of BCH (error correction algorithm for MLC flash in solid state disk) algorithm is 0.001, the retention errors occurring during the period can be corrected by BCH when the number of P/es is less than 300 and the time threshold is set to be one year, the retention errors occurring during the period can be corrected by BCH algorithm when the number of P/es is greater than 300 and less than 1000 and the time threshold is set to be 1 week, the retention errors occurring during the period can be corrected by BCH algorithm, which is to dynamically adaptively adjust the period of forced self-check, and basically ensure that the retention errors occurring during the period can be corrected by BCH. Once forced full-disk self-check is triggered, the firmware needs to self-check the physical data volume of 5MB every second, that is, during the self-check, the host reading bandwidth is reduced by 5MB/s, the performance loss is not obvious, and the normal host sequential reading performance reaches over 500 MB/s.

Due to the existence of a wear leveling strategy (leveling the wear degree of flash memory blocks, which is not described herein) in the solid state disk, the P/E number of each flash memory Block (Block) in the flash memory is basically the same, so the firmware only needs to maintain a whole P/E number.

Once self-checking is triggered (whether idle period self-checking or forced self-checking), the data in the flash memory is read by taking a physical page as a unit in the firmware, whether an error occurs or not is judged, if the error occurs and the error Bit is about to reach the error correction capability, an error correction algorithm is started to correct the data, correct data is written into a new physical address, and the detailed steps are the steps of background self-checking on the physical page.

FIG. 5 is a flow chart of firmware background self-test, which shows the flow of firmware self-test for a small segment (for example, forced self-test 5 MB) of physical flash memory. Self-checking one segment each time, reading one physical page each time when self-checking starts, judging whether the error is about to reach the error correction capability, if so, starting BCH algorithm error correction, and writing the error-corrected data into a new physical address; if the error does not reach the capacity to be corrected, directly judging whether the self-checking data volume exceeds 5MB, if so, ending the self-checking. By adding the background self-checking algorithm, all retention errors possibly occurring in the life cycle of the flash memory can be basically solved, the algorithm has the capability of dynamically and adaptively adjusting the self-checking cycle, about one percent of host performance can be influenced under individual conditions, and the user experience can not be basically influenced.

The corrected data is written into a new physical page, the original old physical page is marked as invalid, a garbage recovery mechanism of the solid state disk can erase the block where the old physical page is located sooner or later, particularly in the later life of a large P/E number (an erase value, a flash memory block needs to be erased and then written), the speed of accumulation of retention errors is faster and faster, and the read-write performance of a host can be seriously influenced due to frequent scheduling of a garbage recovery strategy.

The flash memory writing process is that the flash memory chip determines the amount M of electrons injected into the physical page and the voltage V according to the written data content (distribution and number of binary 0 and 1), then injects electrons in small batches for multiple times, reads the voltage on the physical page after injecting a small part of electrons each time, if the voltage does not reach V, continuously injects a small part of electrons until the voltage on the read physical page is equal to V, and the writing process is completed, as shown in fig. 6. The retention error itself is characterized in that the electrons are gradually lost to cause voltage reduction, and can also be regarded as the loss of the electron injection process in the last steps (assuming the last two steps) of the writing process, the state on the old physical page can be regarded as the state when n-1 is checked in fig. 6, the data corrected by the error correction algorithm is the same as the data written into the physical page at the beginning, namely the distribution and the number of binary 0 and 1 of the data content are the same, if the corrected data is written into a new physical page, the small-batch electron injection process from the 1 st time to the n-1 th time is the same as the old physical page, so that the new physical page does not need to be rewritten at all, the erasing operation can be directly performed in situ, the old physical page can be directly rewritten, namely the old physical page continues to inject electrons from the state when n-1 is checked, only two steps are needed to reach the ideal electron quantity M and voltage value V.

The data errors in a physical page caused by retention errors are only caused by electron loss, so the corrected data content (distribution and number of binary 0 and 1) written in place is always the same as the data content written at first. FIG. 7 is a block diagram illustrating a new method for in-place writing, which is to write the corrected data directly to the original physical page, to effectively overcome the disadvantages of the prior art. The efficiency of the in-place writing is higher than the efficiency of writing to a new physical page, and more importantly, compared with the prior art, the corrected data is still in place, the mapping relation with the logical address is not changed, and then an invalid physical page cannot be generated in the physical block, so that a garbage disposal mechanism in the solid state disk cannot be triggered. Under the condition that the P/E number is close to the limit, the self-checking frequency of the solid state disk is faster and faster, and the value of the technology is considerable.

While the invention has been described with reference to a particular embodiment, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A method for reducing retention errors of a flash memory checks whether data stored in a solid state disk is in errors or not through a background self-check operation background, and if the data stored in the solid state disk is in errors, error correction is performed through an error correction algorithm, the method is characterized in that the background self-check control is triggered in an idle state and triggered in a forced state, the background self-check checks a data space with the size of M each time, M in the idle state is selected to be M1, M2 in the forced state is selected, and M2 is 0.2M 1-0.6M 1; the forced state is forcibly started at different time intervals according to the erasing times of the whole hard disk, and the larger the erasing times, the smaller the time interval.

2. The method of claim 1, wherein the background self-check operation background checks only valid data stored in the solid state disk, and ignores invalid data and data pages not stored.

3. The method of claim 1 or 2, wherein M1 is 10MB, M2 is 5 MB; the erasing times of the whole hard disk are the total erasing times of the solid state disk or the average erasing times of each block.

4. The method according to claim 3, wherein after the background self-check operation detects that the data has an error, the error correction is performed by the error correction algorithm, and the corrected data is directly written back to the original physical page without performing an erase operation on the original physical page.

5. A solid hard disk is characterized in that a method for reducing retention errors of a flash memory is adopted, whether data stored in the whole disk of the solid hard disk are in errors is checked through a background self-checking operation background, if the data are in errors, error correction is carried out through an error correction algorithm, the background self-checking control is triggered in an idle state and triggered in a forced state, the background self-checking checks a data space with the size of M each time, M in the idle state is selected to be M1, M2 in the forced state is selected, and M2 is 0.2M 1-0.6M 1; the forced state is forcibly started at different time intervals according to the erasing times of the whole hard disk, and the larger the erasing times, the smaller the time interval.

6. The solid state disk of claim 5, wherein the background self-check operation background only checks valid data stored in the solid state disk, and ignores invalid data and data pages not stored.

7. The solid hard disk according to claim 5 or 6, characterized in that M1 is selected to be 10MB, M2 is selected to be 5 MB; the erasing times of the whole hard disk are the total erasing times of the solid state disk or the average erasing times of each block.

8. The solid state disk of claim 7, wherein after the background self-check operation detects that the data has an error, the error correction is performed by an error correction algorithm, and then the error-corrected data is directly written back to the same location of the original physical page without performing an erase operation on the original physical page.