CN108595286A - A kind of method and solid state disk promoting reliability of flash memory - Google Patents
A kind of method and solid state disk promoting reliability of flash memory Download PDFInfo
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- CN108595286A CN108595286A CN201810274353.9A CN201810274353A CN108595286A CN 108595286 A CN108595286 A CN 108595286A CN 201810274353 A CN201810274353 A CN 201810274353A CN 108595286 A CN108595286 A CN 108595286A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0727—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a storage system, e.g. in a DASD or network based storage system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0793—Remedial or corrective actions
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Abstract
The invention discloses a kind of methods and solid state disk promoting reliability of flash memory, it is characterized in that solid hard disk controlling backstage increases overall selftest module, when detecting that data page has mistake, pass through correction module, the data of mistake are subjected to error correction recovery, and original position re-writes operation again by the correct data after recovery, the voltage value V2 after the voltage V1 for reading Physical Page is compared after write-in and is corrected works as V1>When V2, applies for a new data block again, the correct data of recovery is written in new data block, and update mapping table.The method verified again after the write-in of original place is proposed, as a result can make the application of the prior art there is no dependence condition really, greatly strengthen versatility.
Description
Technical field
The present invention relates to technical field of memory more particularly to a kind of methods and solid state disk promoting reliability of flash memory.
Background technology
Fig. 1 is the Flash Cell topology examples of MLC flash, and the storage unit cell of Flash uses floating gate transistors
The voltage value of (Floating Gate Transistor) come indicate storage data, MLC (Multi Level Cell) flash memory
Flash cell can store two bit values：LSB (Least Significant Bit) and MSB (Most
Significant Bit), there are four types of states by each Flash cell.
Fig. 2 is the voltage's distribiuting state diagram of Flashcell, and state 1 is erase status, voltage value 0, the bit values of storage
It is 11, state 2 or state 3 are that state is non-fully written, and for voltage value between erasing state and complete state, the bit values of storage are 10
Or 01, state 4 is complete state, and voltage is maximum, and the bit values of storage are 00, wherein reference voltage 1, reference voltage 2, reference voltage 3
It is the reference value that particle manufacturer provides, if floating gate transistors voltage value is less than reference voltage 1, then it is assumed that storage is 11 numbers
According to if floating gate transistors voltage value is between [reference voltage 1, reference voltage 2], then it is assumed that storage is 10 data, such as
Fruit floating gate transistors voltage value is between [reference voltage 2, reference voltage 3], then it is assumed that storage is 01 data, if floated
Gate transistor voltage value is more than reference voltage 3, then it is assumed that storage is 00 data.
Fig. 3 is to be detained mistake to generate schematic diagram, and so-called delay wrong (Retention error) is：If flash memory is long
Phase does not use (such as long-term power-down state), then the electrons in Flash cell leak, voltage value can reduce, point
Cloth state can turn left offset, as shown in figure 3, the data that for example some Flash cell initially writes are 01, it is state 3, voltage
For value between [reference voltage 2, reference voltage 3], solid state disk is in use state once in a while later, i.e., powers on once in a while, and on
The Flash cell are not read and write during electricity, then the electrons on the Flash cell leak gradually, voltage reduces gradually, when
The lasting long enough of this variation, voltage are certain to be less than reference voltage 2, i.e. the Flash cell are become by state 3 for shape
State 2, as shown in figure 3, later if reading the Flash cell, it is found that it is [reference voltage 1, reference voltage 2] it reads voltage
Between, then judge that for 10, that is, error in data occurs for the data of storage！There is error correction algorithm in usual solid state disk, if physics
The wrong bit occurred in page is few, and error correction algorithm is transmitted to host after can also correcting it, but the characteristic for being detained mistake is to be detained
(power down) time is more long, and electronics leakage is more serious, occur mistake bit it is more, error correction algorithm always have entangle not back when, that
Mistake just really occurs.
In order to overcome the problems, such as to be detained mistake, adaptive dynamic self-checking algorithm is used to detect flash memory+original place in solid state disk
Writing Technology finds and eliminates the delay mistake being likely to occur in advance, will if finding to be detained error accumulation to a certain extent
Original place is written in original Physical Page after data correction.This method can effectively reduce the generation for being detained mistake and can be effective really
The triggering of garbage reclamation mechanism is reduced, but the use of the technology has a precondition：Error in data is only simple in Physical Page
Due to be detained mistake caused by.However the technology is often accompanied by writes interference problem in practical applications.It therefore can not
Effectively overcome the mistake.
Invention content
For disadvantages described above, present invention aims at how to solve because the generation for being detained mistake brings data storage errors
The problem of.
To achieve the goals above, the present invention provides a kind of methods promoting reliability of flash memory, it is characterised in that solid
Hard disk controlling backstage increases overall selftest module, when detecting that data page has mistake, by correction module, by the data of mistake
Error correction recovery is carried out, and original position re-writes operation again by the correct data after recovery, compares after write-in and read Physical Page
The voltage V1 and voltage value V2 after correction, works as V1>When V2, apply for a new data block again, the correct data of recovery is written
In new data block, and update mapping table.
The method of promotion reliability of flash memory described in 1, it is characterised in that overall selftest module backstage checks that solid state disk is complete
Whether the data of disk storage occur mistake, then carry out error correction by error correction algorithm in case of mistake, backstage self-test is controlled in sky
It is triggered under triggering and forced regime under not busy state, each backstage self-test checks the data space of M sizes, the M choosings under idle state
It is selected as M1, it is 0.2M1~0.6M1 that M2, M2 are selected under forced regime；The forced regime is selected according to the erasing times of hard disk entirety
Different time interval force starts is selected, erasable number is bigger, and time interval is smaller.
The method for reducing flash memory and being detained mistake, it is characterised in that self-test operations backstage in backstage only checks solid state disk
The valid data stored totally, the data page ignored invalid data and do not stored.
The method for reducing flash memory and being detained mistake, it is characterised in that select M1 for 10MB, M2 5MB；Hard disk is whole
Erasable number be the total erasing times or each piece of average erasing times of solid state disk.
The method for reducing flash memory and being detained mistake, it is characterised in that backstage self-test operations detect that mistake occurs for data
Afterwards, after carrying out error correction by error correction algorithm, not to original physical page into erasing operation, the data after error correction are directly write back into original physical
On page.
A kind of solid state disk, it is characterised in that solid hard disk controlling backstage increases overall selftest module, detects data page
There are when mistake, by correction module, the data of mistake are subjected to error correction recovery, and by the original position again of the correct data after recovery
Operation is re-write, the voltage value V2 after the voltage V1 for reading Physical Page is compared after write-in and is corrected works as V1>When V2, Shen again
Please a new data block, the correct data of recovery is written in new data block, and update mapping table.
The method of the promotion reliability of flash memory, it is characterised in that overall selftest module backstage checks that solid state disk is overall
Whether the data of storage occur mistake, then carry out error correction by error correction algorithm in case of mistake, backstage self-test was controlled in the free time
It is triggered under triggering and forced regime under state, each backstage self-test checks the data space of M sizes, the M selections under idle state
For M1, it is 0.2M1~0.6M1 that M2, M2 are selected under forced regime；The forced regime is selected according to the erasing times of hard disk entirety
Different time interval force starts, erasable number is bigger, and time interval is smaller.
The method for reducing flash memory and being detained mistake, it is characterised in that self-test operations backstage in backstage only checks solid state disk
The valid data stored totally, the data page ignored invalid data and do not stored.
The method for reducing flash memory and being detained mistake, it is characterised in that select M1 for 10MB, M2 5MB；Hard disk is whole
Erasable number be the total erasing times or each piece of average erasing times of solid state disk.
The method for reducing flash memory and being detained mistake, it is characterised in that backstage self-test operations detect that mistake occurs for data
Afterwards, after carrying out error correction by error correction algorithm, not to original physical page into erasing operation, the data after error correction are directly write back into original physical
On page.
The present invention proposes the method that verifies again after the write-in of original place, as a result can make really the application of the prior art there is no according to
The condition of relying, greatly strengthens versatility.
Description of the drawings
Fig. 1 is the Flash Cell topology examples of MLC flash；
Fig. 2 is the voltage's distribiuting state diagram of Flash cell；
Fig. 3 is to be detained mistake to generate schematic diagram；
Fig. 4 is the factor and relational graph for influencing to be detained mistake；
Fig. 5 is firmware backstage self-test flow chart；
Fig. 6 is the process schematic of flash memory write-in；
Fig. 7 is the factor example for influencing to write interference；
Fig. 8 is to be detained mistake with influence of the interference to Physical Page 2 is write to illustrate；
Fig. 9 close on Physical Page write interference cause voltage increase schematic diagram；
Figure 10 is the modified flow figure using adaptive dynamic self-checking+original place Writing Technology.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other without creative efforts
Embodiment shall fall within the protection scope of the present invention.
Fig. 6 is the process schematic of flash memory write-in：Flash chip according to the data content of write-in (Binary Zero and 1 distribution
With quantity) determine the amount of electrons M and voltage V being injected on Physical Page, then small lot injects electronics several times, injects every time
After sub-fraction electronics, the voltage read on Physical Page is checked, if not up to V, continues to inject sub-fraction electronics,
It is equal to V until reading out the voltage on Physical Page, then ablation process is completed, as shown in Figure 6.And the characteristics of being detained mistake itself, is
Electronics is lost gradually causes voltage to reduce, and can also regard ablation process finally a few step (assuming that being the last two steps) electron injections as
The loss of process, then the state on old Physical Page can regard as in Fig. 6 check n-1 when state, entangled by error correction algorithm
Data after just, be with the data for being written the Physical Page at the beginning it is the same, i.e., data content Binary Zero and 1 distribution
It is the same with quantity, if the data after correction are written to new physical page, the 1st n-1 small lot injection on earth
It is the same in electronic processes and old Physical Page, so basic just It is not necessary to be re-written to new Physical Page, completely
Directly old Physical Page can be write in original place, i.e., old Physical Page continues to inject electronics from state when checking n-1, it is only necessary to two
Step can reach ideal amount of electrons M and voltage value V.
Fig. 4 is the factor for influencing to be detained mistake and relational graph and the relationship between them, and X-axis is the (erasing time of P/E numbers
Number, flash memory characteristics：Flash block can just be write after must wiping), Y-axis is that (Bit overturning mistakes occur BER for Bit Error Rate
Ratio, it characterizes the data reliability of flash memory, and more small data is more reliable), as can be seen from the figure：
1, delay mistake is in close relations with P/E values, and P/E is bigger, and the ratio that Bit overturnings occur is bigger.
2, delay mistake is in close relations with the residence time, and the residence time is longer, and the ratio that Bit overturnings occur is bigger, this is
It analyzed above.
Since delay mistake is to reach the error correcting capability beyond error correction algorithm gradually as the time accumulates gradually, then I
Can periodically read overall data from the background, seen whether that data have occurred that mistake, if mistake does not occur,
Do not do any operation then, otherwise look at the mistake occurred whether will be more than error correction algorithm error correcting capability (known to error correction algorithm
In the case of, error correcting capability is also known), if not reaching error correcting capability much also, any operation is not done, if will
Reach the error correcting capability of error correction algorithm, then enables error correction algorithm and correct data, then the data original place after correction is rewrited, with
On be to some Physical Page carry out backstage self-test the step of.
Since but be backstage self-test, cannot influence normal host read-write requests certainly, but under certain scenes (such as
Data center) host is that have read-write requests always, if not enabling backstage self-test always, the time is grown, and necessarily will produce stagnant
Mistake is stayed, so considering, the trigger condition of backstage self-test is：
1, it is triggered when idle, i.e., no host starts when asking, while being imitated in order to not influence follow-up possible read-write requests
Rate, backstage self-test are separated into multistage, and every section is set as 10MB data volumes, and one section of self-test when idle every time is then log out task, attempts
Front end request is responded, if again without request, continues lower section of self-test, firmware needs to remember the process of self-test.
2, time threshold is set and initial time stamp not will produce sky in the case where host persistently there are read-write requests
The not busy phase, but delay mistake cannot be generated again, so firmware needs timing, it has been more than threshold value when the time, has then forced to carry out backstage
Self-test, of course for host request is not influenced as possible, the data volume of every section of self-test needs smaller, is set as 5MB.Its subthreshold is set
It sets also than more elegant, it is in close relations with P/E numbers to be detained mistake as can be seen from Figure 4, it is assumed that BCH (dodges in solid state disk for MLC
The error correction algorithm deposited) algorithm error correcting capability be 0.001, then when P/E numbers be less than 300 when setting time threshold be 1 year, the phase
Between the delay mistake that occurs can be corrected by BCH, when P/E be more than 300 be less than 1000 when setting time threshold be 1 month, during which
The delay mistake of generation can be corrected by BCH algorithms, and when P/E is more than 1000 less than 3000, setting time threshold is 1 week, phase
Between the delay mistake that occurs can be corrected by BCH algorithms, this is exactly the period that dynamic self-adapting forces self-test, and basic
It can ensure that the delay mistake occurred within this period can be corrected by BCH.Overall self-test, firmware is forced to need once triggering this
Will be every the physical data amount of one second self-test 5MB, i.e., during self-test, host tape reading width can reduce 5MB/s, this performance damage
Mistake is not obvious (normal host sequence reading performance reaches 500MB/s or more).
3, due to the presence of abrasion equilibrium strategy (degree of wear of balanced flash block, this will not be repeated here) in solid state disk,
The P/E numbers of each flash block (Block) are substantially the same in flash memory, so firmware only needs to safeguard the P/E numbers of an entirety
.
Once 4, triggering self-test (either idle periods self-test, or force self-test), it is unit to press Physical Page inside firmware
Data in flash memory is read, and judges whether that mistake occurs, being up to error correcting capability in case of wrong and mistake Bit then starts
Error correction algorithm corrects data, and correct data original place be written again once, and step is as detailed above to the self-test of Physical Page backstage
Step.
Flow chart 5 illustrates the flow of a bit of (for the forcing self-test 5MB) physical flash of firmware self-test.Increase backstage
Self-checking algorithm+original place Writing Technology, can solve in flash memory life cycle all delay mistakes that may occur and can be effective substantially
The triggering of garbage reclamation mechanism is reduced, which has ability of the dynamic self-adapting from the overhaul period, can shadow under individual cases
The host performance for ringing 1 percent or so, does not interfere with user experience substantially.
But there are two preconditions for processing in this way：
1, error in data is simple since electronics is lost caused by (delay mistake) in Physical Page.
2, the correction data content (Binary Zero and 1 distribution and quantity) of the original place write-in centainly number with being written at the beginning
According to content striking resemblances.
Condition 2 is to meet certainly, and condition 1 may not meet in some scenarios, can be right after certain Physical Page is written such as original place
Interference problem is write in other Physical Page generations in physical block, this will limit the application of the prior art.
Adaptive dynamic self-checking+original place Writing Technology depends on：Error in data is simple due to being detained in Physical Page
Mistake causes.However original place write-in itself is also write operation, it will produce other Physical Page in physical block and writes interference, so-called
Write interference refer to some Physical Page carry out write operation when, will produce larger voltage, this voltage can subtle increase face
The threshold voltage of nearly Physical Page, this increased degree depend on being currently located the P/E numbers of physical block and write the number of interference, directly
The factor of interference is write in the influence of visible Fig. 7 of understanding of sight.
Fig. 8 is to be detained mistake with influence of the interference to Physical Page 2 is write to illustrate, and the erasing times of physical block are larger in figure, and
It writes full data aft engine not read for a long time, then the threshold voltage of Physical Page Page2 and Page3 can slowly drop as time goes by
It is low, when voltage drop to a certain extent, adaptive dynamic self-checking inside SSD+original place write-in process can rewrite Physical Page 2 and 3, so
And due to writing the presence of interference, when rewriteeing Physical Page 3, the threshold voltage of Physical Page 2 can be promoted slightly a bit, as original place is written
Number reach a certain amount, the threshold voltage of Physical Page 2 is certain to be more than ideal value, and the threshold voltage variation of Physical Page 2 is such as
The Physical Page that closes on of Fig. 9 writes interference voltage is caused to increase shown in schematic diagram, eventually more increasing mostly until state changes, i.e. data
Mistake occurs, and can not entangle back.
In conclusion Figure 10 is the modified flow figure using adaptive dynamic self-checking+original place Writing Technology, certain extreme
Under the conditions of, the threshold voltage of Physical Page does not reduce, and increases, original place wiring method can't resolve the problem at this time.
Voltage value size V2 after comparing the voltage V1 for reading Physical Page in adaptive dynamic self-checking and correcting, if V1<V2, then this
When be detained erroneous effects account for it is leading, using original place wrting method, if V1>V2, then that closes on Physical Page at this time writes interference shadow
Ringing accounts for leading, using replay shooting method, i.e., correct data is write to new Physical Page, because original place writing mode can not reduce
Voltage on flash memory Physical Page.
Interference number is write for theory reach very big magnitude and just will appear write the case where interference effect accounts for leading position,
One of but ensure that the correctness of user data is to store the primary liability of product, without, so this must be solved the problems, such as.New skill
Art relieves the pain spot of the prior art
Above disclosed is only an embodiment of the present invention, cannot limit the right model of the present invention with this certainly
It encloses, those skilled in the art can understand all or part of the processes for realizing the above embodiment, and is wanted according to right of the present invention
Equivalent variations made by asking still fall within the range that the present invention is covered.
Claims (10)
1. a kind of method promoting reliability of flash memory, it is characterised in that solid hard disk controlling backstage increases overall selftest module, examines
When measuring data page and there is mistake, by correction module, the data of mistake are subjected to error correction recovery, and by the positive exact figures after recovery
Operation is re-write according to original position again, the voltage value V2 after the voltage V1 for reading Physical Page is compared after write-in and is corrected works as V1>V2
When, apply for a new data block again, the correct data of recovery is written in new data block, and update mapping table.
2. the method according to claim 1 for promoting reliability of flash memory, it is characterised in that overall selftest module backstage checks
Whether the data that solid state disk stores totally occur mistake, then carry out error correction by error correction algorithm in case of mistake, from the background certainly
Prosecution system is triggered and is triggered under forced regime in an idle state, and each backstage self-test checks the data space of M sizes, idle shape
M under state is selected as M1, and it is 0.2M1~0.6M1 that M2, M2 are selected under forced regime；The forced regime is according to hard disk entirety
Erasing times select different time interval force starts, and erasable number is bigger, and time interval is smaller.
3. the method according to claim 2 for reducing flash memory and being detained mistake, it is characterised in that backstage self-test operations backstage is only
Check the valid data that solid state disk stores totally, the data page ignored invalid data and do not stored.
4. the method according to claim 2 or 3 for reducing flash memory and being detained mistake, it is characterised in that select M1 for 10MB, M2
For 5MB；The erasable number of hard disk entirety is the total erasing times or each piece of average erasing times of solid state disk.
5. the method according to claim 4 for reducing flash memory and being detained mistake, it is characterised in that backstage self-test operations detect
After mistake occurs for data, after carrying out error correction by error correction algorithm, not to original physical page into erasing operation, directly by the number after error correction
According to writing back on original physical page.
6. a kind of solid state disk, it is characterised in that solid hard disk controlling backstage increases overall selftest module, detects that data page is deposited
In mistake, by correction module, the data of mistake are subjected to error correction recovery, and by the original position weight again of the correct data after recovery
New write operation, the voltage value V2 after the voltage V1 for reading Physical Page is compared after write-in and is corrected, works as V1>When V2, apply again
One new data block, the correct data of recovery is written in new data block, and update mapping table.
7. the method according to claim 6 for promoting reliability of flash memory, it is characterised in that overall selftest module backstage checks
Whether the data that solid state disk stores totally occur mistake, then carry out error correction by error correction algorithm in case of mistake, from the background certainly
Prosecution system is triggered and is triggered under forced regime in an idle state, and each backstage self-test checks the data space of M sizes, idle shape
M under state is selected as M1, and it is 0.2M1~0.6M1 that M2, M2 are selected under forced regime；The forced regime is according to hard disk entirety
Erasing times select different time interval force starts, and erasable number is bigger, and time interval is smaller.
8. the method according to claim 7 for reducing flash memory and being detained mistake, it is characterised in that backstage self-test operations backstage is only
Check the valid data that solid state disk stores totally, the data page ignored invalid data and do not stored.
9. the method according to claim 7 or 8 for reducing flash memory and being detained mistake, it is characterised in that select M1 for 10MB, M2
For 5MB；The erasable number of hard disk entirety is the total erasing times or each piece of average erasing times of solid state disk.
10. the method according to claim 9 for reducing flash memory and being detained mistake, it is characterised in that backstage self-test operations detect
After mistake occurs for data, after carrying out error correction by error correction algorithm, not to original physical page into erasing operation, directly by the number after error correction
According to writing back on original physical page.
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| CN114995753A (en) * | 2022-05-25 | 2022-09-02 | 华中科技大学 | Method and device for improving reliability of 3DNAND solid state disk |
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Application publication date: 20180928 |