CN108804025A - A kind of method and solid state disk for reducing flash memory and being detained mistake - Google Patents
A kind of method and solid state disk for reducing flash memory and being detained mistake Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0727—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a storage system, e.g. in a DASD or network based storage system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0653—Monitoring storage devices or systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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Abstract
The invention discloses methods and solid state disk that a kind of reduction flash memory is detained mistake, check whether data occur mistake by backstage self-test operations backstage, error correction is then carried out by error correction algorithm in case of mistake, it is characterized in that self-test control in backstage is triggered and triggered under forced regime in an idle state, each backstage self-test checks the data space of M sizes；The forced regime selects different time interval force starts according to the erasing times of hard disk entirety, and erasable number is bigger, and time interval is smaller.The efficiency of original place write-in is than writing the efficient of new physical page, the data of correction are still in situ, do not change with the mapping relations of logical address, invalid Physical Page is not will produce in physical block so, so the garbage disposal mechanism inside solid state disk will not be triggered, coordinate the mechanism of dynamic self-adapting self-test in the prior art, can effectively reduce the generation for being detained mistake, host performance can not be influenced again, moreover it is possible to indirectly promote flash memory life cycle.
Description
Technical field
The present invention relates to technical field of memory more particularly to a kind of methods and solid state disk for reducing flash memory and being detained mistake.
Background technology
Flash cell indicate to deposit using the voltage value of floating gate transistors (Floating Gate Transistor)
The Flash cell of the data of storage, MLC (Multi Level Cell) flash memory can store two bit values：Least significant bit
LSB (Least Significant Bit) and most significant bit MSB (Most Significant Bit), Fig. 1 are MLC mono-
The storage unit FLASH cell schematic diagrames of flash memory, each Flash cell include LSB and MSB, and each position has
Two states, therefore there are four types of states by a Flash cell.Fig. 2 is that the voltage's distribiuting of the storage unit of mono- flash memory of MLC shows
It is intended to, a Flash cell is different voltage there are four types of status and appearance, specially：State 1 is erase status, and voltage value is
0, the bit values of storage are 11, and state 2 or state 3 are that state is non-fully written, and voltage value is deposited between erasing state and complete state
The bit values of storage are 10 or 01, and state 4 is complete state, and voltage is maximum, and the bit values of storage are 00, wherein reference voltage 1, with reference to electricity
Pressure 2, reference voltage 3, reference voltage 3 is the reference value that particle manufacturer provides, if floating gate transistors voltage value is less than ginseng
Examine voltage 1, then it is assumed that storage is 11 data, if floating gate transistors voltage value [reference voltage 1, reference voltage 2] it
Between, then it is assumed that storage is 10 data, if floating gate transistors voltage value between [reference voltage 2, reference voltage 3], then
Think storage is 01 data, if floating gate transistors voltage value is more than reference voltage 3, then it is assumed that storage is 00 data.
So-called delay wrong (Retention error) is：If flash memory does not use for a long time, for example is chronically at power down
State, then the electrons in Flash cell leak, voltage value can reduce, and distribution can turn left offset, such as
00, which floats to 01,10, floats to 11, i.e., mistake has occurred in the data stored in flash memory, is detained the characteristic that mistake is flash memory.
As previously mentioned, so-called delay wrong (Retention error) is：If flash memory does not use (such as long for a long time
Phase power-down state), then the electrons in Flash cell leak, voltage value can reduce, and distribution can be toward left avertence
It moves, Fig. 3 is to occur to be detained wrong schematic diagram, such as the data that some Flash cell initially writes are 01, are state 3, voltage
For value between [reference voltage 2, reference voltage 3], solid state disk is in use state once in a while later, i.e., powers on once in a while, and on
The Flash cell are not read and write during electricity, then the electrons on the Flash cell leak gradually, voltage reduces gradually, when
The lasting long enough of this variation, voltage are certain to be less than reference voltage 2, i.e. the Flash cell are become by state 3 for shape
State 2, as shown in figure 3, later if reading the Flash cell, it is found that it is [reference voltage 1, reference voltage 2] it reads voltage
Between, then judge that for 10, that is, error in data occurs for the data of storage！There is error correction algorithm in usual solid state disk, if physics
The wrong bit occurred in page is few, and error correction algorithm is transmitted to host after can also correcting it, but the characteristic for being detained mistake is to be detained
(power down) time is more long, and electronics leakage is more serious, occur mistake bit it is more, error correction algorithm always have entangle not back when, that
Mistake just really occurs！
The prior art is to detect flash memory using adaptive dynamic self-checking algorithm in solid state disk, finds in advance and eliminates possibility
The delay mistake of appearance, once find be detained error accumulation to a certain extent if by data correction after be rewritten to new Physical Page
In.This method can effectively reduce the generation for being detained mistake really, but it is exactly by the data after correction that it, which has clearly disadvantageous,
It writes in new Physical Page, original old Physical Page is marked as in vain, and the garbage reclamation mechanism of solid state disk sooner or later can be this
Block where old physical page wipes out, life especially larger in P/E numbers (erasing number, flash block are written again after must wiping)
Later stage, the speed for being detained error accumulation are getting faster, and garbage collection strategy is frequently dispatched, it will seriously affect the read-write of host
Energy.
Invention content
For disadvantages described above, present invention aims at the delay mistakes for how reducing solid hard disk.
To achieve the goals above, the present invention provides a kind of method that reduction flash memory is detained mistake, pass through backstage self-test
Operation backstage checks whether the data that solid state disk stores totally occur mistake, is then carried out by error correction algorithm in case of mistake
Error correction, it is characterised in that self-test control in backstage is triggered and triggered under forced regime in an idle state, and each backstage self-test checks M
The data space of size, the M under idle state are selected as M1, and it is 0.2M1~0.6M1 that M2, M2 are selected under forced regime；It is described strong
State processed selects different time interval force starts according to the erasing times of hard disk entirety, and erasable number is bigger, time interval
It is smaller.
The method for reducing flash memory and being detained mistake, it is characterised in that self-test operations backstage in backstage only checks solid state disk
The valid data stored totally, the data page ignored invalid data and do not stored.
The method for reducing flash memory and being detained mistake, it is characterised in that select M1 for 10MB, M2 5MB；Hard disk is whole
Erasable number be the total erasing times or each piece of average erasing times of solid state disk.
The method for reducing flash memory and being detained mistake, it is characterised in that backstage self-test operations detect that mistake occurs for data
Afterwards, after carrying out error correction by error correction algorithm, directly the data after error correction are write back on original physical page.
A kind of solid hard disk, it is characterized in that the method that flash memory is detained mistake that reduces is used, after the self-test operations of backstage
Platform checks whether the data that solid state disk stores totally occur mistake, and then error correction is carried out by error correction algorithm in case of mistake,
Backstage self-test control is triggered and is triggered under forced regime in an idle state, and each backstage self-test checks the data space of M sizes,
M under idle state is selected as M1, and it is 0.2M1~0.6M1 that M2, M2 are selected under forced regime；The forced regime is according to hard disk
Whole erasing times select different time interval force starts, and erasable number is bigger, and time interval is smaller.
The solid hard disk, it is characterised in that it is effective that self-test operations backstage in backstage only checks that solid state disk stores totally
Data, the data page ignored invalid data and do not stored.
The solid hard disk, it is characterised in that select M1 for 10MB, M2 5MB；The erasable number of hard disk entirety is solid
The total erasing times of state hard disk or each piece of average erasing times.
The solid hard disk, it is characterised in that after backstage self-test operations detect that mistake occurs for data, calculated by error correction
After method carries out error correction, not to original physical page into erasing operation, directly the data after error correction are write back on original physical page.
Advantageous effect of the present invention：The efficiency of original place write-in than writing the efficient of new physical page, more crucially with it is existing
There is technology to compare, the data of correction are still in situ, do not change with the mapping relations of logical address, then in physical block not
Invalid Physical Page is will produce, so the garbage disposal mechanism inside solid state disk will not be triggered, coordinates dynamic in the prior art
The mechanism of adaptive self-test can effectively reduce the generation for being detained mistake and not influence host performance, moreover it is possible to indirectly be promoted
Flash memory life cycle.
Description of the drawings
Fig. 1 is the storage unit FLASH cell schematic diagrames of mono- flash memory of MLC；
Fig. 2 is the voltage's distribiuting schematic diagram of the storage unit of mono- flash memory of MLC；
Fig. 3 is to occur to be detained wrong schematic diagram；
Fig. 4 influences the factor relation figure for being detained mistake；
Fig. 5 is firmware backstage self-test flow chart；
Fig. 6 is data writing process schematic diagram；
Fig. 7 is the backstage self-test flow chart of original place write-in.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other without creative efforts
Embodiment shall fall within the protection scope of the present invention.
Fig. 4 influences the factor relation figure for being detained mistake, and X-axis is erasing times P/E numbers, and Y-axis is BER (Bit Error
The ratio of Bit overturning mistakes occurs for Rate, it characterizes the data reliability of flash memory, and more small data is more reliable), it can from figure
To find out：1, delay mistake is in close relations with P/E values, and P/E is bigger, and the ratio that Bit overturnings occur is bigger.2, be detained mistake with it is stagnant
Stay time relationship close, the residence time is longer, and the ratio that Bit overturnings occur is bigger.
Analysis shows that it is to reach the error correcting capability beyond error correction algorithm gradually as the time accumulates gradually to be detained mistake, because
This periodically reads overall data from the background by increasing, and has checked whether that data have occurred that mistake, if do not occurred
Mistake, then do not do any operation, otherwise judges whether the mistake occurred will be more than the error correcting capability of error correction algorithm, because of error correction
In the case of algorithm is known, error correcting capability is also known, if not reaching error correcting capability much also, does not do any operation,
If the error correcting capability of error correction algorithm will be reached, enables error correction algorithm and correct data, then the data after correction are written
It is the step of carrying out backstage self-test to some Physical Page above to new physical address.
Due to increasing backstage self-test, it is necessary to which guarantee cannot influence normal host read-write requests, but certain scenes
Under such as data center's host be to have read-write requests always, if not enabling backstage self-test always, the time is grown, and will necessarily produce
Raw to be detained mistake, so considering, the trigger condition of backstage self-test is：
1：It is triggered when idle, i.e., no host starts when asking, while being imitated in order to not influence follow-up possible read-write requests
Rate, backstage self-test are separated into multistage, and every section is set as 10MB data volumes, and one section of self-test when idle every time is then log out task, attempts
Front end request is responded, if again without request, continues lower section of self-test, firmware needs to remember the process of self-test.
2：Setting time threshold and initial time stamp not will produce sky in the case where host persistently has read-write requests
The not busy phase, but delay mistake cannot be generated again, so firmware needs timing, it has been more than threshold value when the time, has then forced to carry out backstage
Self-test, of course for host request is not influenced as possible, the data volume of every section of self-test needs smaller, is set as 5MB.Its subthreshold is set
It sets different, it is in close relations with P/E numbers to be detained mistake as can be seen from Figure 4, it is assumed that BCH (is directed to MLC in solid state disk
The error correction algorithm of flash memory) algorithm error correcting capability be 0.001, then when P/E numbers be less than 300 when setting time threshold be 1 year,
The delay mistake that period occurs can be corrected by BCH, and when P/E is more than 300 less than 1000, setting time threshold is 1 month, the phase
Between the delay mistake that occurs can be corrected by BCH algorithms, when P/E be more than 1000 be less than 300 when setting time threshold be 1 week,
The delay mistake that period occurs can be corrected by BCH algorithms, this is exactly the period that dynamic self-adapting forces self-test, Er Qieji
Originally it can ensure that the delay mistake occurred within this period can be corrected by BCH.Once triggering forces overall self-test, firmware to need
Every the physical data amount of one second self-test 5MB, i.e., during self-test, host tape reading width can reduce 5MB/s, this performance loss
It is not obvious, normal host sequence reading performance reaches 500MB/s or more.
Due to the presence of abrasion equilibrium strategy (degree of wear of balanced flash block, this will not be repeated here) in solid state disk, dodge
The P/E numbers of each flash block (Block) are substantially the same in depositing, so firmware only needs the P/E numbers of one entirety of maintenance i.e.
It can.
Once triggering self-test (either idle periods self-test, or force self-test), read for unit by Physical Page inside firmware
Data in flash memory is taken, and judges whether that mistake occurs, is to be up to error correcting capability and then start to entangle in case of mistake and mistake Bit
It miscounts method and corrects data, and correct data is written to new physical address, step is as detailed above to the self-test of Physical Page backstage
Step.
Fig. 5 is firmware backstage self-test flow chart, illustrates a bit of (for the forcing self-test 5MB) physics of firmware self-test and dodges
The flow deposited.One segment of each self-test reads a Physical Page every time when self-test starts, and whether misjudgment will reach
To error correcting capability, if it is starts BCH algorithm error correction, the data after error correction are written to new physical address；If mistake does not have
Have to reach and will reach error correcting capability, then directly judges that self-inspection data amount whether more than 5MB, if it is terminates this self-test.
By increasing backstage self-checking algorithm, all delay mistakes that may occur in flash memory life cycle, algorithm tool can be solved substantially
There is ability of the dynamic self-adapting from the overhaul period, 1 percent or so host performance can be influenced under individual cases, substantially not
It can influence user experience.
Data after correction are write in new Physical Page, original old Physical Page is marked as in vain, solid state disk
Garbage reclamation mechanism sooner or later can wipe out the block where the old physical page, and especially in P/E numbers, (erasing number, flash block are necessary
Be written again after erasing) larger later stage of life, the speed for being detained error accumulation is getting faster, and garbage collection strategy is frequently dispatched,
The readwrite performance of host will be seriously affected.
The process of flash memory write-in is, flash chip according to the data content of write-in (Binary Zero and 1 distribution and quantity) really
Surely the amount of electrons M and voltage V being injected on Physical Page, then small lot injects electronics several times, injects sub-fraction every time
After electronics, the voltage on Physical Page is read, if not up to V, continues to inject sub-fraction electronics, until reading out Physical Page
On voltage be equal to V, then ablation process complete, as shown in Figure 6.And the characteristics of being detained mistake itself is that electronics is lost and caused gradually
Voltage reduces, and can also regard the loss of last a few step (assuming that being the last two steps) the electron injection processes of ablation process as, then old
Physical Page on state can regard as in Fig. 6 check n-1 when state, into cross error correction algorithm correct after data, with one
The data for starting to be written the Physical Page be it is the same, i.e., data content Binary Zero and 1 distribution with quantity be it is the same,
If the data after correction are written to new physical page, the 1st time Dao n-1 times small lot injection electronic processes and old physics
The same in page, so basic just It is not necessary to be re-written to new Physical Page, completely can directly original place do not need
Erasing operation is carried out, old Physical Page is arrived in directly manifolding, i.e., old Physical Page continues to inject electronics from state when checking n-1,
Only need two steps that can reach ideal amount of electrons M and voltage value V.
It is caused by the simple loss due to electronics to be detained error in data in Physical Page caused by mistake, and original place is write
Data content of the correction data content (Binary Zero and 1 distribution and quantity) entered centainly with being written at the beginning is the same.Figure
7 in view of the deficiencies of the prior art, it is proposed that the method for new original place write-in, that is, the data after correction are written directly to
In Physical Page originally, the shortcomings that capable of effectively making up the prior art.The efficiency of this original place write-in is than writing new physical page
Efficient, more crucially compared with prior art, the data of correction are still in situ, not with the mapping relations of logical address
Change, then invalid Physical Page is not will produce in physical block, so the garbage disposer inside solid state disk will not be triggered
System coordinates the mechanism of dynamic self-adapting self-test in the prior art, can effectively reduce the generation for being detained mistake and not influence to lead
Machine performance, moreover it is possible to indirectly promote flash memory life cycle (because reducing garbage reclamation, the operation of erasing can be reduced).In P/
E numbers are close in the case of the limit, and the frequency of solid state disk self-test is getting faster, and the value which embodies also just more may be used
It sees.
Above disclosed is only an embodiment of the present invention, cannot limit the right model of the present invention with this certainly
It encloses, those skilled in the art can understand all or part of the processes for realizing the above embodiment, and is wanted according to right of the present invention
Equivalent variations made by asking still fall within the range that the present invention is covered.
Claims (8)
1. a kind of method for reducing flash memory and being detained mistake checks the number that solid state disk stores totally by backstage self-test operations backstage
According to whether mistake occurring, error correction is then carried out by error correction algorithm in case of mistake, it is characterised in that backstage self-test is controlled in sky
It is triggered under triggering and forced regime under not busy state, each backstage self-test checks the data space of M sizes, the M choosings under idle state
It is selected as M1, it is 0.2M1~0.6M1 that M2, M2 are selected under forced regime；The forced regime is selected according to the erasing times of hard disk entirety
Different time interval force starts is selected, erasable number is bigger, and time interval is smaller.
2. the method according to claim 1 for reducing flash memory and being detained mistake, it is characterised in that backstage self-test operations backstage is only
Check the valid data that solid state disk stores totally, the data page ignored invalid data and do not stored.
3. the method according to claim 1 or 2 for reducing flash memory and being detained mistake, it is characterised in that select M1 for 10MB, M2
For 5MB；The erasable number of hard disk entirety is the total erasing times or each piece of average erasing times of solid state disk.
4. the method according to claim 3 for reducing flash memory and being detained mistake, it is characterised in that backstage self-test operations detect
After mistake occurs for data, after carrying out error correction by error correction algorithm, not to original physical page into erasing operation, directly by the number after error correction
According to writing back on original physical page.
5. a kind of solid hard disk passes through backstage self-test operations backstage it is characterized in that using the method that flash memory is detained mistake that reduces
It checks whether the data that solid state disk stores totally occur mistake, error correction is then carried out by error correction algorithm in case of mistake, after
Platform self-test control is triggered and is triggered under forced regime in an idle state, and each backstage self-test checks the data space of M sizes, empty
M under not busy state is selected as M1, and it is 0.2M1~0.6M1 that M2, M2 are selected under forced regime；The forced regime is whole according to hard disk
The erasing times of body select different time interval force starts, and erasable number is bigger, and time interval is smaller.
6. solid hard disk according to claim 5, it is characterised in that self-test operations backstage in backstage only checks that solid state disk is complete
The valid data of disk storage, the data page ignored invalid data and do not stored.
7. solid hard disk according to claim 5 or 6, it is characterised in that select M1 for 10MB, M2 5MB；Hard disk is whole
Erasable number be the total erasing times or each piece of average erasing times of solid state disk.
8. solid hard disk according to claim 7, it is characterised in that after backstage self-test operations detect that mistake occurs for data,
After carrying out error correction by error correction algorithm, not to original physical page into erasing operation, the data after error correction are directly write back into original physical page
Same position.
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