CN108417487A - The process of groove-shaped shield grid power device - Google Patents
The process of groove-shaped shield grid power device Download PDFInfo
- Publication number
- CN108417487A CN108417487A CN201810120395.7A CN201810120395A CN108417487A CN 108417487 A CN108417487 A CN 108417487A CN 201810120395 A CN201810120395 A CN 201810120395A CN 108417487 A CN108417487 A CN 108417487A
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- Prior art keywords
- etching
- groove
- carries out
- power device
- grid power
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Links
- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000005530 etching Methods 0.000 claims abstract description 40
- 230000003647 oxidation Effects 0.000 claims abstract description 25
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 23
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 15
- 229920005591 polysilicon Polymers 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000001039 wet etching Methods 0.000 claims abstract description 12
- 238000002347 injection Methods 0.000 claims abstract description 10
- 239000007924 injection Substances 0.000 claims abstract description 10
- 239000013078 crystal Substances 0.000 claims description 4
- 230000000717 retained effect Effects 0.000 claims description 3
- 230000001360 synchronised effect Effects 0.000 claims description 2
- 238000009826 distribution Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000013049 sediment Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
Abstract
The invention discloses a kind of processes of groove-shaped shield grid power device, including：The first step, etching groove, dielectric layer deposited simultaneously carry out first time polycrystalline silicon deposit and etching on substrate；Second step carries out second in the case where unglazed photoresist defines to first time polysilicon and etches；Third walks, and carries out high-density plasma oxidation film deposit；4th step carries out CMP to high-density plasma oxidation film；5th step, then high-density plasma oxidation film is returned and is carved；6th step carries out intermediate oxide layer wet etching；7th step forms gate oxide and polycrystalline silicon deposit；8th step carries out body area's injection；9th step, the subsequent technique for carrying out source region injection, making contact.The present invention can improve the V of deviceTHDistribution.
Description
Technical field
The present invention relates to semiconductor devices and manufacturing fields, particularly relate to a kind of technique of groove-shaped shield grid power device
Method.
Background technology
As shown in Figure 1, the basic technology of groove-shaped shield grid power device product is：It completes and deposits in etching groove
After polysilicon, polysilicon poly1 carries out first time etching, and etching terminates in crystal column surface；The second of polysilicon poly2 is carried out again
Secondary etching, under the definition of photoresist, etching depth is deep into 1~1.5 μm or less deeply of substrate；Carry out high-density plasma shallow lake
Product HDP fills groove；CMP is carried out again, retains hdp film thickness more than silicon chip surfaceCarry out intermediate oxidation film
Wet etching, under the definition of photoresist, etching depth is 0.8~1.2 μm or so below substrate surface；Groove internal oxidition film forms sediment
Product, polycrystalline silicon deposit and time quarter；Body area, source region injection；Form the subsequent techniques such as contact.Under basic technology, in order to avoid
The oxide layer of polysilicon poly1 side walls, polysilicon poly1 join domain remaining thickness are etched into when intermediate oxidation film wet etching
AboutOxide layer.
What poly1 join domains retainedOxide layer, because film forming and CMP technological fluctuation, WIW
(within wafer, wafer face in), WTW (wafer to wafer, chip between) difference is very big.The thickness of the oxide layer
The body area of influence of fluctuations poly1 join domains is injected, to cause threshold voltage VTHIt is unstable.Groove-shaped shield grid power device
Product VTHDistribution dispersion, VTHTarget 3V, and error just has 1V in practical face.
Invention content
Technical problem to be solved by the present invention lies in provide a kind of process of groove-shaped shield grid power device, shape
At device have stable set in threshold voltage.
To solve the above problems, the process of groove-shaped shield grid power device of the present invention, including：
The first step, etching groove, dielectric layer deposited simultaneously carry out first time polycrystalline silicon deposit and etching on substrate；
Second step carries out second in the case where unglazed photoresist defines to first time polysilicon and etches；
Third walks, and carries out high-density plasma oxidation film deposit；
4th step carries out CMP to high-density plasma oxidation film；
5th step, then high-density plasma oxidation film is returned and is carved；
6th step carries out intermediate oxidation film wet etching；
7th step forms gate oxide and polycrystalline silicon deposit；
8th step carries out body area's injection；
9th step, the subsequent technique for carrying out source region injection, making contact.
Further, in the first step, first time etching polysilicon, etching terminal is crystal column surface.
Further, in the second step, second of etching is the generally etching of unglazed photoresist, join domain and die region
Domain synchronizes etching, and etching depth is to go deep into 1~1.5 μm of substrate or less.
Further, in the 4th step, the film thickness retained after CMP is
Further, it in the 5th step, returns to carve to return using wet method and carve, according to residual film thickness adjust automatically wet method after CMP
The condition of etching, oxidation film surface is with substrate surface difference in height after etching
Further, in the 6th step, intermediate oxidation film wet etching be photoresist definition under, etching depth be away from
0.8~1.2 μm of substrate surface or less.
The process of groove-shaped shield grid power device of the present invention, performs etching to first time polysilicon
When, join domain is unobstructed, with die area synchronize etch into groove, after HDP CMP additional wet etching to silicon face,
Join domain is deep into groove and source contact, improves the V of deviceTHDistribution.
Description of the drawings
Fig. 1 is the schematic diagram of the oxidation film using photoresist protection join domain in traditional handicraft.
Fig. 2 is the residual schematic diagram of oxidation film after removal photoresist in traditional technique.
Fig. 3~11 are present invention process step schematic diagrams.
Figure 12 is the V based on the device under traditional handicraft and present invention processTHIt is distributed box-shaped figure.
Figure 13 is present invention process flow chart of steps.
Reference sign
1 is polysilicon, and 2 be oxidation film, and 3 be HDP oxidation films, and 4 be photoresist, and 5 be gate oxide energy, and 6 be polysilicon gate
Pole, 7 be body area, and 8 be contact hole.
Specific implementation mode
The process of groove-shaped shield grid power device of the present invention, step are distinguished shown in 3~Figure 11 of corresponding diagram,
Including：
The first step, etching groove, dielectric layer deposited simultaneously carry out first time polycrystalline silicon deposit and etching on substrate；Etching is eventually
Point is crystal column surface.
Second step carries out second in the case where unglazed photoresist defines to first time polysilicon and etches；Second of etching
For the generally etching of unglazed photoresist, join domain etching synchronous with die area, etching depth be go deep into 1~1.5 μm of substrate with
Under.
Third walks, and carries out high-density plasma oxidation film deposit.
4th step carries out CMP to high-density plasma oxidation film, and the film thickness retained after CMP is
5th step, then high-density plasma oxidation film is returned and is carved, it returns to carve to return using wet method and carve, according to residual-film thickness after CMP
Degree automatically controls the condition of wet etching, and oxidation film surface is with substrate surface difference in height after etching
6th step carries out intermediate oxidation film wet etching；Intermediate oxidation film wet etching is the etching under photoresist definition
Condition is fixed, and etching depth is 0.8~1.2 μm away from substrate surface or less.
7th step forms gate oxide and polycrystalline silicon deposit.
8th step carries out body area's injection.
9th step, the subsequent technique for carrying out source region injection, making contact.
By above-mentioned technique, join domain of the invention is to go deep into groove and source contact.The injection in body area is to VTH shadows
Sound is limited.By box-shaped figure as shown in figure 12, the VTH distributions for the device under traditional handicraft on the left of solid line are erected in figure, most
Height is higher than 3.2V, device that is minimum more to disperse close to 2.1V, entire VTH, and being formed using the present invention, and VTH is distributed more steady
Fixed to concentrate, shown in the box-shaped figure on the right side of perpendicular solid line, VTH highests are only that 0.5V and being distributed more is concentrated with minimum differ.
It these are only the preferred embodiment of the present invention, be not intended to limit the present invention.Those skilled in the art is come
It says, the invention may be variously modified and varied.All within the spirits and principles of the present invention, any modification made by is equal
Replace, improve etc., it should all be included in the protection scope of the present invention.
Claims (6)
1. a kind of process of groove-shaped shield grid power device, it is characterised in that：Including following processing step：
The first step, etching groove, dielectric layer deposited simultaneously carry out first time polycrystalline silicon deposit and etching on substrate；
Second step carries out second in the case where unglazed photoresist defines to first time polysilicon and etches；
Third walks, and carries out high-density plasma oxidation film deposit；
4th step carries out CMP to high-density plasma oxidation film；
5th step, then high-density plasma oxidation film is returned and is carved；
6th step carries out intermediate oxide layer wet etching；
7th step forms gate oxide and polycrystalline silicon deposit；
8th step carries out body area's injection；
9th step, the subsequent technique for carrying out source region injection, making contact.
2. the process of groove-shaped shield grid power device as described in claim 1, it is characterised in that：The first step
In, first time etching polysilicon, etching terminal is crystal column surface.
3. the process of groove-shaped shield grid power device as described in claim 1, it is characterised in that：The second step
In, second of etching is the generally etching of unglazed photoresist, and join domain etching synchronous with die area, etching depth is deeply lining
1~1.5 μm of bottom or less.
4. the process of groove-shaped shield grid power device as described in claim 1, it is characterised in that：4th step
In, the film thickness retained after CMP is
5. the process of groove-shaped shield grid power device as described in claim 1, it is characterised in that：5th step
In, it returns to carve to return using wet method and carve, according to the condition of residual film thickness adjust automatically wet etching after CMP, film surface is aoxidized after etching
It is with substrate surface difference in height
6. the process of groove-shaped shield grid power device as described in claim 1, it is characterised in that：6th step
In, intermediate oxidation film wet etching is under photoresist definition, and etching depth is 0.8~1.2 μm away from substrate surface or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810120395.7A CN108417487A (en) | 2018-02-07 | 2018-02-07 | The process of groove-shaped shield grid power device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810120395.7A CN108417487A (en) | 2018-02-07 | 2018-02-07 | The process of groove-shaped shield grid power device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108417487A true CN108417487A (en) | 2018-08-17 |
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ID=63127933
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810120395.7A Pending CN108417487A (en) | 2018-02-07 | 2018-02-07 | The process of groove-shaped shield grid power device |
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| Country | Link |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112133628A (en) * | 2020-09-29 | 2020-12-25 | 上海华虹宏力半导体制造有限公司 | Method for improving surface roughness of shielding grid |
| CN112701043A (en) * | 2020-12-28 | 2021-04-23 | 广州粤芯半导体技术有限公司 | Method for manufacturing semiconductor device |
| CN117080075A (en) * | 2023-08-28 | 2023-11-17 | 深圳市美浦森半导体有限公司 | Novel SGT manufacturing method and structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102623339A (en) * | 2011-01-26 | 2012-08-01 | 上海华虹Nec电子有限公司 | Method for improving thickness uniformity of intermediate oxide layer of double-layer grid MOS structure |
| CN102623340A (en) * | 2011-01-26 | 2012-08-01 | 上海华虹Nec电子有限公司 | Method for preparing groove-type double-layer grid MOS device |
| US20120280307A1 (en) * | 2011-05-02 | 2012-11-08 | Alpha And Omega Semiconductor Incorporated | Integrating schottky diode into power mosfet |
-
2018
- 2018-02-07 CN CN201810120395.7A patent/CN108417487A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102623339A (en) * | 2011-01-26 | 2012-08-01 | 上海华虹Nec电子有限公司 | Method for improving thickness uniformity of intermediate oxide layer of double-layer grid MOS structure |
| CN102623340A (en) * | 2011-01-26 | 2012-08-01 | 上海华虹Nec电子有限公司 | Method for preparing groove-type double-layer grid MOS device |
| US20120280307A1 (en) * | 2011-05-02 | 2012-11-08 | Alpha And Omega Semiconductor Incorporated | Integrating schottky diode into power mosfet |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112133628A (en) * | 2020-09-29 | 2020-12-25 | 上海华虹宏力半导体制造有限公司 | Method for improving surface roughness of shielding grid |
| CN112701043A (en) * | 2020-12-28 | 2021-04-23 | 广州粤芯半导体技术有限公司 | Method for manufacturing semiconductor device |
| CN117080075A (en) * | 2023-08-28 | 2023-11-17 | 深圳市美浦森半导体有限公司 | Novel SGT manufacturing method and structure |
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Application publication date: 20180817 |