CN104701165B - The forming method of transistor - Google Patents
The forming method of transistor Download PDFInfo
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- CN104701165B CN104701165B CN201310647757.5A CN201310647757A CN104701165B CN 104701165 B CN104701165 B CN 104701165B CN 201310647757 A CN201310647757 A CN 201310647757A CN 104701165 B CN104701165 B CN 104701165B
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Abstract
The present invention provides a kind of forming method of transistor, including：Substrate is provided；At least one pseudo- grid structure is formed over the substrate, and dummy gate structure includes gate dielectric layer, cap and pseudo- grid from bottom to top；Source region and drain region are formed in the substrate that the pseudo- grid expose;The dielectric layer between the pseudo- grid upper caldding layer；The pseudo- grid are removed using the etching agent including oxygen, opening is formed at pseudo- grid script position, forms metal gates in said opening.When removing the pseudo- grid, oxygen proportion declines with the time in etching agent, the bias voltage of plasma etching declines with the time, so that while pseudo- grid are removed into clean, the pseudo- grid for other transistors being connected on the interlayer dielectric layer on the outside of pseudo- grid, with the pseudo- grid influence smaller, make the opening pattern that is formed after removal puppet grid preferable, and the cap below pseudo- grid is kept good pattern.
Description
Technical field
The present invention relates to semiconductor applications, and in particular to a kind of forming method of transistor.
Background technology
In high K dielectric/rear metal gate engineering of transistor, complete high annealing carry out it is ion-activated after, it is necessary to
Pseudo- grid（Such as polysilicon gate）Remove, metal gate electrode is then refilled, to form high K dielectric/rear metal-gate structures.
With reference to figure 1, a kind of schematic diagram of the forming method of transistor of prior art is illustrated.Formed in substrate 01 shallow
Channel separating zone 08, pseudo- grid structure of the side formed with NMOS tube of shallow channel isolation area 08, opposite side is formed with PMOS
Pseudo- grid structure, each pseudo- grid structure is as included gate dielectric layer 03, cap 06, pseudo- grid 02.
According to existing rear grid technique, it is necessary to remove pseudo- grid 02 therein after above-mentioned pseudo- grid structure is formed..Reference chart
2, prior art is general first 07 to cover NMOS tube part with photoresist, then using anisotropic dry etching such as plasma
(Reactive Ion Etching, RIE) is etched to remove the pseudo- grid 02 for the PMOS that material is polysilicon, etching agent is from acid
Property gas and oxygen mixed gas, wherein sour gas is as reacting gas, and the effect of oxygen is adjustment etch rate, and
And oxygen can be with the etching stop layer in the pseudo- outside of grid 02（Contact etch stop layer, CESL）04 or inter-level dielectric
Layer（Inter-level dielectric, ILD）05 reaction, generates oxide, can play the lateral quarter for reducing dry etching
The effect of erosion.
But the forming method of the transistor of prior art, the open bottom easily formed in the pseudo- grid 02 of removal form more
Crystal silicon residual 09.
In addition, as shown in figure 3, in some cases, such as some regions in nonvolatile memory, positioned at substrate
NMOS puppet grid 02A, NMOS gate dielectric layer 03A, NMOS cap 06A of NMOS tube and the PMOS puppet grid of PMOS on 01 '
02B, PMOS gate dielectric layer 03B, PMOS cap 06B are connected to each other as a whole, in photoresist 07 ' covering NMOS tube part
And when etching PMOS puppet grid 02B, depressed part easily is formed in NMOS puppet grid 02A side wall, so as to have impact on the property of transistor
Energy.
The content of the invention
The present invention solves the problems, such as to be to provide a kind of forming method of transistor, reduces and remove the open bottom that pseudo- grid are formed
The residual polycrystalline silicon problem in portion.
To solve the above problems, the present invention provides a kind of Transistor forming method, including：
Substrate is provided；
At least one pseudo- grid structure is formed over the substrate, and dummy gate structure includes gate dielectric from bottom to top
Layer, cap and pseudo- grid；
Source region and drain region are formed in the substrate that dummy gate structure is exposed；
The dielectric layer between dummy gate structure upper caldding layer；
The pseudo- grid are removed using the etching agent including oxygen, opening are formed at pseudo- grid script position, and going
During pseudo- grid, the ratio that oxygen accounts for etching agent declines with the time；
Metal gates are formed in said opening.
Optionally, using plasma etching removes the pseudo- grid, and during the pseudo- grid are removed, plasma is carved
The bias voltage of erosion declines with the time.
Optionally, after source region and drain region is formed, also include before forming interlayer dielectric layer：In the side wall and puppet of pseudo- grid
Etching barrier layer is formed on the substrate that grid expose.
Optionally, the material of the pseudo- grid is polysilicon, using including oxygen etching agent remove the pseudo- grid the step of
In, the etching agent also includes hydrogen bromide.
Optionally, in the step of removing the pseudo- grid, the flow of hydrogen bromide often assigns to 500 mark conditions milli in 50 mark condition milliliters
In the range of rising every point, the flow of oxygen is in the range of 2 mark condition milliliters often assign to 10 every point of mark condition milliliters, the gas of etching cavity
It is pressed in the range of 2 millitorrs to 80 millitorrs.
Optionally, in the step of removing the pseudo- grid using the etching agent including oxygen, oxygen proportion in etching agent
Decline linearly over time,
Optionally, during removing the pseudo- grid using the etching agent including oxygen, oxygen proportion in etching agent
Drop in the range of from 2% to 5% in the range of 0.2% to 1%.
Optionally, during removing the pseudo- grid using the etching agent including oxygen, oxygen proportion in etching agent
Drop to 0.6% from 3%.
Optionally, during removing the pseudo- grid using the etching agent including oxygen, the power of plasma etching exists
In the range of 100 watts to 2000 watts.
Optionally, in the step of removing the pseudo- grid using the etching agent including oxygen, the biased electrical of plasma etching
Pressure declines linearly over time.
Optionally, bias voltage initial value is in the range of 50V to 200V, the model of the final value of bias voltage in 10V to 30V
In enclosing.
Optionally, during removing the pseudo- grid using the etching agent including oxygen, the biased electrical of plasma etching
Pressure is from 50V to dropping to 10V.
Compared with prior art, technical scheme has advantages below：
During removing pseudo- grid, the ratio that oxygen accounts for etching agent declines with the time.When plasma etching just starts, oxygen
Account for that the ratio of etching agent is higher, can play and reduce laterally etched effect, the influence to interlayer dielectric layer is smaller；Oxygen accounts for quarter
The ratio of erosion agent declines with the time, and when etching into pseudo- grid bottom, the intensity of plasma etching accounts for the ratio of etching agent because of oxygen
Decline and strengthen, the bottom of pseudo- grid can be removed clean.
Further, when plasma etching starts, bias voltage is higher, plasma be biased voltage influence obtain compared with
Big acceleration, make the anisotropy of plasma etching strong, it is laterally etched less, therefore when removing a pseudo- grid, with it
Another adjacent pseudo- grid have more smooth side wall；In addition, when removing pseudo- grid bottom, the intensity of plasma etching is because partially
Put voltage to decline and reduce, can ensure that the cap below pseudo- grid keeps good pattern.
Brief description of the drawings
Fig. 1 to Fig. 3 is a kind of schematic diagram of the forming method of transistor of prior art；
Fig. 4 is the flow chart of the embodiment of forming method one of transistor of the present invention；
Fig. 5 to Fig. 8 is the schematic diagram of each step in method shown in Fig. 4；
Fig. 9 is the schematic diagram of another embodiment of forming method of transistor of the present invention；
Figure 10 is the graph of a relation of bias voltage and etch period in embodiment illustrated in fig. 9.
Embodiment
Formed by pseudo- grid technique in the Transistor forming method of metal gates, in the open bottom that the pseudo- grid of removal are formed
Portion forms residual polycrystalline silicon.
Analysis removes the process of pseudo- grid：Oxygen excessively easily causes what the etching intensity of dry etching declined when removing pseudo- grid
Problem, it is unnet so as to cause polysilicon to remove, and then form residual polycrystalline silicon in the open bottom that the pseudo- grid of removal are formed.
With reference to figure 4, the flow chart of the embodiment of forming method one of transistor of the present invention, the shape of transistor of the present invention are shown
Include step in general below into method：
Step S1, there is provided substrate；
Step S2, forms at least one pseudo- grid structure over the substrate, and dummy gate structure includes grid from bottom to top
Pole dielectric layer, cap and pseudo- grid；
Step S3, source region and drain region are formed in the substrate that the pseudo- grid expose;
Step S4, the dielectric layer between the pseudo- grid upper caldding layer；
Step S5, the pseudo- grid are removed using the etching agent including oxygen, opening is formed at pseudo- grid script position,
And during pseudo- grid are removed, the ratio that oxygen accounts for etching agent declines with the time；
Step S6, forms metal gates in said opening；
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
With reference to figure 5 to Fig. 8, the schematic diagram of each step in embodiment illustrated in fig. 4 is shown.
Step S1 is performed as shown in Figure 5, there is provided substrate 100.In the present embodiment, the substrate 100 is silicon substrate, at it
In his embodiment, the substrate 100 can also be other Semiconductor substrates such as germanium silicon substrate or silicon-on-insulator substrate, to this
Any restrictions are not done in invention.
In the present embodiment, with CMOS transistor（Complementary Metal Oxide
Semiconductor, CMOS）Exemplified by, forming method of the present invention is illustrated, complimentary oxide transistor include PMOS and
NMOS.After substrate 100 is provided, isolation structure 101 is formed also in substrate 100, the isolation structure 101 is isolated for shallow trench
Structure, in other embodiments, the isolation structure can also be carrying out local oxide isolation.The isolation structure 101 is used for institute
State substrate 100 and be divided into nmos area substrate and PMOS areas substrate, in other embodiments, the isolation structure can not also be formed
101。
With continued reference to Fig. 5, step S2 is performed, substrate surface forms PMOS puppet grid structures, the PMOS in the PMOS areas
Pseudo- grid structure includes PMOS gate dielectric layer 102A, PMOS cap 103A, PMOS puppet grid 105A from bottom to top, described
Nmos area substrate surface forms NMOS puppet grid structures, and the NMOS puppets grid structure includes NMOS gate dielectric layer from bottom to top
102B, NMOS cap 103B, NMOS puppet grid 105B.
Specifically, in the present embodiment, the PMOS gate dielectric layers 102A, NMOS gate dielectric layer 102B material are
Hafnium oxide, hafnium oxide have higher dielectric constant as a kind of hafnium.
The material of PMOS puppets grid 105A, NMOS puppet grid 105B is polysilicon, and polysilicon is the conventional material of pseudo- grid.
The material of PMOS cap 103A, the NMOS cap 103B is titanium nitride, as PMOS gate dielectric layers
102A, NMOS gate dielectric layer 102B protective layer.
But the present invention is covered PMOS gate dielectric layers 102A, NMOS gate dielectric layer 102B, PMOS cap 103A, NMOS
Cap layers 103B, PMOS puppet grid 105A, NMOS puppet grid 105B specific material is not limited.
With continued reference to Fig. 5, step S3 is performed, using the PMOS puppets grid structure, NMOS puppet grid structures as mask, in PMOS areas
Source region, drain region are formed respectively in substrate, nmos area substrate（It is not shown）.
In the present embodiment, the source region in PMOS areas substrate, drain region are formed using stress germanium silicon, nmos area substrate
Source region, drain region are formed using carborundum, but the present invention is not limited to source region, the specific forming method in drain region and material.
In the present embodiment, forming source region, after drain region, the surface of substrate 100 and PMOS puppet grid structure,
The side walls of NMOS puppet grid structures forms etching barrier layer 104, as the etching barrier layer of subsequent technique, in other embodiments,
The etching barrier layer 104 can not also be formed.
With continued reference to Fig. 5, step S4 is performed, in the etching barrier layer 104 and the PMOS puppets grid structure, NMOS puppet grid
Dielectric layer 106 between structure upper caldding layer.
Specifically, the material of the interlayer dielectric layer 106 is silica, but the present invention is to the material of interlayer dielectric layer 106
It is not limited.
Next cmp is carried out to the interlayer dielectric layer 106, to expose PMOS puppet grid structure, NMOS puppet grid
The upper surface of structure.
With reference to figure 6, step S5 is performed, plasma etching is carried out to the PMOS puppets grid structure to remove PMOS puppet grid
105A, to form the opening 201 of corresponding PMOS puppet grid 105A shapes.
In the present embodiment, remove the PMOS puppets grid 102A and carried out respectively with removing the NMOS puppets grid 105B, therefore,
Before plasma etching is carried out to the PMOS puppets grid structure, patterned mask layer is first covered on the substrate of nmos area
107, it is mask with the patterned mask layer 107, plasma etching is carried out to the PMOS puppets grid structure.
In the present embodiment, specifically, the etching agent of plasma etching is the mixed gas of hydrogen bromide and oxygen, described
Hydrogen bromide is reacting gas.During dry etching, oxygen accounts for the ratio of the mixed gas of hydrogen bromide and oxygen with the time
Drop.Other mixed gas including oxygen can also be used in other embodiments.
It should be noted that during plasma etching, the flow of hydrogen bromide often assigns to 500 in 50 mark condition milliliters
In the range of marking every point of condition milliliter, the flow of oxygen is in the range of 2 mark condition milliliters often assign to 10 every point of mark condition milliliters, etch chamber
The air pressure of body is in the range of 2 millitorrs to 80 millitorrs, and the power of plasma etching is in the range of 100 watts to 2000 watts.
With reference to figure 7, the relation between the ratio and etch period that oxygen accounts for is shown, wherein X represents etch period, Y tables
Show that oxygen accounts for the ratio of the mixed gas of hydrogen bromide and oxygen, in the present embodiment, the etch period of plasma etching is 2 points
Clock, in 2 minutes, oxygen accounts for the ratio of the mixed gas of hydrogen bromide and oxygen and linearly decreased to from 3% in plasma etching
0.6%。
In other embodiments, the etch period of plasma etching can also be in the range of 30 seconds to 2 minutes.
When plasma etching starts, the ratio that oxygen accounts for the mixed gas of hydrogen bromide and oxygen is 3%, is at this moment played
Corrasion hydrogen bromide proportion is relatively fewer, and the intensity of plasma etching is relatively low, and oxygen proportion is relatively existing
Send out at the top for having the etching barrier layer 104 and interlayer dielectric layer 106 that technology is higher, passes through oxygen and PMOS puppet grid 102A side walls
Life is reacted and generates oxide-film, can preferably be reduced laterally etched so that the top of interlayer dielectric layer 106 and PMOS puppet grid
The etching barrier layer 104 of 102A side walls keeps good pattern, improves the performance of the transistor ultimately formed.
The ratio that oxygen accounts for etching agent declines with the time, and when etching into PMOS puppet grid 102A bottoms, oxygen accounts for hydrogen bromide
Be 0.6% with the ratio of the mixed gas of oxygen, that is to say, that now the proportion of oxygen is smaller and the ratio of hydrogen bromide compared with
Height, hydrogen bromide ratio as reacting gas is higher PMOS puppet grid 102A bottom can be removed it is clean, so as to reduce polycrystalline
The problem of silicon remains.
When the initial value of oxygen proportion is excessive, etch rate influences production capacity slowly excessively, and can cause the top of opening 201
The residual polycrystalline silicon in portion；When the initial value of oxygen proportion is too small, laterally etched bigger than normal, interlayer dielectric layer when etching originates
The pattern of 106 top and the etching barrier layer 104 of PMOS puppet grid 102A side walls is easily deteriorated by laterally etched.Work as oxygen
When the final value of proportion is excessive, plasma etching will at the end of etching intensity it is too small, be likely to result in pseudo- grid 102A
Bottom residual polycrystalline silicon；When the final value of oxygen proportion is too small, plasma etching will at the end of etching intensity
It is excessive and laterally etched more, it can influence positioned at the PMOS cap 103A of the bottom of opening 201 and positioned at the bottom side of opening 201
The pattern of the etching barrier layer 104 of wall.
Optionally, drop in the range of oxygen proportion is from 2% to 5% in etching agent in the range of 0.2% to 1%.
As shown in fig. 7, with the progress of plasma etching, oxygen accounts for the mixed of hydrogen bromide and oxygen in plasma etching
The ratio for closing gas declines, and in the present embodiment, oxygen proportion linear decline, such be advantageous in that is easy to control, and
The change of oxygen proportion is uniform, avoids causing PMOS puppet grid 102A because of the suddenly change of the etching intensity of plasma etching
The side wall of etching barrier layer 104 in outside is uneven.
In other embodiments, oxygen account for the mixed gas of hydrogen bromide and oxygen ratio can also use include be segmented under
Other of drop decline mode, the invention is not limited in this regard.
It should also be noted that, in other embodiments, because PMOS puppet grid 102A height may change, wait from
Daughter etching etch period might be less that 30 seconds or more than 2 minutes, the invention is not limited in this regard.
As shown in figure 8, performing step S6, PMOS metal gates 110 are formed in said opening, due to after step S5,
The top of interlayer dielectric layer 106 and the etching barrier layer 104 of PMOS puppet grid 102A side walls keep good pattern, i.e., described to open
The side wall of mouth is more smooth, and the side wall of the PMOS metal gates 110 formed in said opening is also more smooth, and PMOS metal gates
The bottom of pole 110 does not have residual polycrystalline silicon, improves the performance of transistor.
The step of after PMOS metal gates 110 are formed, continuously forming NMOS metal gates, forming NMOS metal gates is wrapped
Include：The patterned photoresist layer 107 is removed, the NMOS puppet grid 105B in the NMOS puppets grid structure is then removed, is going
During NMOS puppet grid 105B, using plasma etching removes NMOS puppet grid 105B, and etching agent is sour gas and oxygen
The mixed gas of gas, the ratio that oxygen accounts for etching agent decline with the time, it is possible to reduce remove the opening that NMOS puppet grid 105B is formed
Residual polycrystalline silicon problem caused by bottom.
In other embodiments, during removing NMOS puppet grid 105B, the ratio that oxygen accounts for etching agent can also be fixed
Value, wet etching can also be used to remove NMOS puppet grid 105B.
NMOS metal gates are formed in the opening formed after removing NMOS puppet grid 105B（It is not shown）, form NMOS metals
Technique is technology customary in the art used by grid, be will not be repeated here.
With reference to figure 9, the schematic diagram of another embodiment of forming method of transistor of the present invention is shown.Fig. 9 is illustrated that can
With the transistor applied to nonvolatile memory, the NMOS puppet grid 105B' of nmos pass transistor, NMOS gate dielectric layer 102B',
NMOS cap 103B' PMOS puppet grid 105A', PMOS gate dielectric layer 102A', PMOS cap with PMOS transistor respectively
103A' is connected to each other as a whole.
Generally use plasma etching removes the PMOS puppets grid 105A'.Wherein, the bias voltage of plasma etching
Effect be to accelerate plasma, obtain bigger energy, the anisotropy of plasma etching accordingly strengthens, i.e., along vertical
The square etching of substrate is strengthened, and the laterally etched relative reduction in parallel substrate direction.It is but easy with the raising of bias voltage
The PMOS cap 103A' below PMOS puppet grid 102A' is caused to sustain damage, and relatively low bias voltage can cause in NMOS crystalline substances
The region that the NMOS puppet grid 105B' of body pipe and the PMOS puppet grid 105A' of PMOS transistor are connected to each other as a whole, by PMOS puppet grid
After 105A' is etched, remaining NMOS puppets grid 105B' side wall easily produces depression.
In order to reduce the generation of side walls collapse, forming method and Fig. 5 to embodiment illustrated in fig. 8 of the present embodiment transistor
Something in common repeats no more, and the difference of the present embodiment is：During PMOS puppet grid 105A' is removed, plasma is carved
The bias voltage of erosion declines with the time.
With reference to figure 10, the relation between bias voltage and etch period in the present embodiment is shown, when wherein M represents etching
Between, N represents bias voltage, and in the present embodiment, the etch period of plasma etching is 2 minutes, in 2 minutes, plasma
The bias voltage of body etching drops to 10V from 50V.
In other embodiments, in the range of the etch period of plasma etching can also be 30 seconds to 2 minutes.
In the present embodiment, when the leading portion of plasma etch process, the bias voltage of plasma etching is higher, this
When, the anisotropy of plasma etching is stronger, laterally etched less, while enabling to etch PMOS puppet grid 105A',
The NMOS puppet grid 105B' of the remaining adjacent nmos pass transistor being connected with PMOS puppet grid 105A' side wall is more smooth.
When plasma etching closes to an end, bias voltage drops to close to 10V, and so relatively low bias voltage can be protected
After card etches away PMOS puppet grid 105A', PMOS cap 103A' keeps good pattern, while avoids in NMOS puppet grid 105B'
Side wall produce depression, so as to avoid being formed at NMOS puppet grid 105B' positions with raised metal gate, and then improve
The performance of the transistor ultimately formed.
In addition, work as in plasma etch process, when the ratio that oxygen accounts for the mixed gas of hydrogen bromide and oxygen declines,
Also it can play and reduce laterally etched effect, be beneficial to the NMOS puppet grid of nmos pass transistor for keeping PMOS puppet grid 105A' connected
The good pattern of 105B' side wall.
In the present embodiment, the initial value of bias voltage is 50V, final value 10V in plasma etching, in other implementations
In example, because PMOS puppet grid 105A' material is different, the concentration of etching agent is different, and the bias voltage of plasma etching rises
Initial value is in the range of 50V to 200V, and the final value of bias voltage is in the range of 10V to 30V.
It should be noted that the power of plasma etching is in the range of 100 watts to 2000 watts.
In the present embodiment, the bias voltage of plasma etching linearly declines, and such be advantageous in that is easy to control, and
Bias voltage change is uniform, avoids causing on the outside of PMOS puppet grid 102A' because of the suddenly change of laterally etched etching intensity
The side wall for the NMOS puppet grid 105B' being connected in etching barrier layer 104' side walls and adjacent transistor with PMOS puppet grid 102A' is recessed
Convex injustice., can also be by the way of segmented decline but the mode that the present invention declines to bias voltage is not restricted.
Optionally, during NMOS puppet grid 105B' is removed, the bias voltage of plasma etching declines with the time.
The Transistor forming method of the present embodiment can remove a transistor while avoiding producing residual polycrystalline silicon
Pseudo- grid after can also make the pseudo- grid of adjacent another transistor that there is smooth side wall, so as to improve the performance of transistor.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (12)
- A kind of 1. forming method of transistor, it is characterised in that including：Substrate is provided；At least one pseudo- grid structure is formed over the substrate, and dummy gate structure includes gate dielectric layer, lid from bottom to top Cap layers and pseudo- grid；Source region and drain region are formed in the substrate that dummy gate structure is exposed；The dielectric layer between dummy gate structure upper caldding layer；The pseudo- grid are removed using the etching agent including oxygen, opening is formed at pseudo- grid script position, and it is pseudo- removing During grid, the ratio that oxygen accounts for etching agent declines with the time；Metal gates are formed in said opening.
- 2. forming method as claimed in claim 1, it is characterised in that using plasma etching removes the pseudo- grid, is going During except the pseudo- grid, the bias voltage of plasma etching declines with the time.
- 3. forming method as claimed in claim 1, it is characterised in that after source region and drain region is formed, form inter-level dielectric Also include before layer：Etching barrier layer is formed on the substrate that the side wall of pseudo- grid and pseudo- grid are exposed.
- 4. forming method as claimed in claim 1, it is characterised in that the material of the pseudo- grid is polysilicon, using including oxygen The etching agent of gas was removed in the step of pseudo- grid, and the etching agent also includes hydrogen bromide.
- 5. forming method as claimed in claim 4, it is characterised in that in the step of removing the pseudo- grid, the stream of hydrogen bromide For amount in the range of 50 mark condition milliliters often assign to 500 every point of mark condition milliliters, the flow of oxygen often assigns to 10 mark conditions in 2 mark condition milliliters In the range of every point of milliliter, the air pressure of etching cavity is in the range of 2 millitorrs to 80 millitorrs.
- 6. forming method as claimed in claim 1, it is characterised in that the pseudo- grid are removed using the etching agent for including oxygen In step, oxygen proportion declines linearly over time in etching agent.
- 7. the forming method as described in claim 1 or 6, it is characterised in that the puppet is removed using the etching agent for including oxygen During grid, drop in the range of oxygen proportion is from 2% to 5% in etching agent in the range of 0.2% to 1%.
- 8. forming method as claimed in claim 7, it is characterised in that the pseudo- grid are removed using the etching agent for including oxygen During, oxygen proportion drops to 0.6% from 3% in etching agent.
- 9. forming method as claimed in claim 1, it is characterised in that the pseudo- grid are removed using the etching agent for including oxygen During, the power of plasma etching is in the range of 100 watts to 2000 watts.
- 10. forming method as claimed in claim 2, it is characterised in that the pseudo- grid are removed using the etching agent for including oxygen The step of in, the bias voltage of plasma etching declines linearly over time.
- 11. the forming method as described in claim 2 or 10, it is characterised in that model of the bias voltage initial value in 50V to 200V In enclosing, the final value of bias voltage is in the range of 10V to 30V.
- 12. forming method as claimed in claim 11, it is characterised in that the pseudo- grid are removed using the etching agent for including oxygen During, the bias voltage of plasma etching is from 50V to dropping to 10V.
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| CN102117750A (en) * | 2009-12-30 | 2011-07-06 | 中国科学院微电子研究所 | MOSFET structure and manufacturing method thereof |
| CN102270600A (en) * | 2010-06-04 | 2011-12-07 | 中芯国际集成电路制造(上海)有限公司 | Forming method of through hole |
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| CN102117750A (en) * | 2009-12-30 | 2011-07-06 | 中国科学院微电子研究所 | MOSFET structure and manufacturing method thereof |
| CN102270600A (en) * | 2010-06-04 | 2011-12-07 | 中芯国际集成电路制造(上海)有限公司 | Forming method of through hole |
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