CN107768375B

CN107768375B - Method for forming split gate

Info

Publication number: CN107768375B
Application number: CN201710884971.0A
Authority: CN
Inventors: 许鹏凯; 习艳军; 杨渝书
Original assignee: Shanghai Huali Microelectronics Corp
Current assignee: Shanghai Huali Microelectronics Corp
Priority date: 2017-09-26
Filing date: 2017-09-26
Publication date: 2020-02-21
Anticipated expiration: 2037-09-26
Also published as: CN107768375A

Abstract

The invention provides a method for forming a split gate grid, which improves the process for forming the split gate grid and simultaneously obtains a selection grid and a control grid with vertical appearances under a split gate structure. Compared with the method for forming the control grid by adopting the polysilicon side wall etching in the prior art, the method adopts the two-time forming and self-aligning method, so that the control grid which simultaneously meets the requirements of the size and shape process can be easily obtained under the split grid structure. The process flow reduces the difficulty of grid etching in the original process flow, and simultaneously, the conditions such as the growth thickness of a film layer and the like in the process development are easier to determine.

Description

Method for forming split gate

Technical Field

The present invention relates to the field of semiconductor integrated circuit manufacturing, and more particularly, to a method for forming a split gate.

Background

The 2TFlash device can effectively reduce the problems of over-erasure, but the use of its Select Gate (SG) also increases the area of the storage region. In order to more effectively increase the storage area utilization rate, a Split Gate (Split Gate) structure may be adopted. Under the structure, a Control Gate (CG) is adjacent to the selection Gate, so that the area utilization rate of the storage region is effectively increased. In addition, in order to further increase the utilization rate of the storage area, the same source is adopted by the two storage units. For example, the select gates in two adjacent memory cells are close to the source, and the control gates are at the periphery of the select gates, close to the drain, as shown in fig. 1. A common source terminal is arranged between two selection gates in the Area shown in Area 101, and a common drain terminal is arranged between two control gates in the Area shown in Area 102.

In the prior art, the Split Gate process first forms a select Gate of a vertical stacked structure, and then forms a control Gate by a polysilicon sidewall etching process, such as a sidewall control Gate shown in fig. 1. When the technology is adopted, the size of the polysilicon of the side wall is larger, and the utilization rate of the area of the storage region is further weakened. In addition, the production process requires that the critical dimension and thickness of the control gate obtained by etching can meet the process requirements, and meanwhile, the bottom of the side wall control gate is required to keep a vertical appearance. These all make the development of the etching process of the sidewall control gate more difficult.

For the split gate structure, if the polysilicon gate with the vertical morphology can be used for replacing the polysilicon gate with the sidewall morphology, on one hand, the area utilization rate of the storage region is improved, and on the other hand, the control gate with the morphology and the film thickness meeting the requirements can be obtained more easily. On the basis, if the critical dimension of the control gate can also meet the process requirement, the scheme has great advantages compared with the existing scheme.

Disclosure of Invention

The invention provides a grid forming method of a split gate, which improves the forming process of a selection grid and a control grid in the process flow of the split gate, changes the method for forming the control grid by a side wall process in the original process flow, finally forms the control grid with a laminated structure in a vertical shape on the premise of not changing the vertical shape of the selection grid, reduces the difficulty of the forming process of the control grid, and is easier to obtain the control grid with the shape and the size meeting the process requirements.

The new process flow comprises the following steps:

forming an initial film layer according to the post-formed gate film layer structure, wherein the initial film layer is sequentially arranged on a gate oxide layer, a polycrystalline silicon layer, a silicon oxide layer and a silicon nitride layer on a substrate layer from bottom to top;

exposing and etching the initial film layer to form a plurality of groove structures;

growing a storage medium layer on the structure;

growing a polycrystalline silicon film layer on the structure, carrying out chemical mechanical polishing, and stopping polishing until the storage medium layer is polished, so that the groove is filled with polycrystalline silicon;

etching the exposed storage medium layer to make the etching process stop on the silicon nitride layer;

etching the exposed polysilicon, and adjusting the height of the polysilicon in the groove;

growing a silicon oxide film layer, then carrying out chemical mechanical polishing, and stopping when the polishing process reaches the silicon nitride layer, so that the silicon oxide film layer is filled in the upper part of the polycrystalline silicon in the groove;

adjusting the height difference by taking the exposed silicon oxide film layer as a mask, and adjusting the thickness of the silicon nitride layer to a required thickness;

coating photoresist on the surface of the structure, exposing to display a control grid electrode exposure area, removing a silicon nitride layer in the exposure area through wet etching on the basis, and removing the residual silicon oxide film layer and the residual polysilicon film layer of the central grid structure of the exposure area through a dry etching method;

removing the photoresist, and removing the exposed storage medium layer by adopting isotropic etching;

removing all the silicon oxide film layer on the top of the control grid by adopting a wet etching method to form the control grid;

coating photoresist on the surface of the structure, then exposing the selective grid exposure area, then carrying out dry etching by taking the selective grid exposure area as a mask, and stopping the etching process on the silicon oxide layer;

after the photoresist is removed, the selective grid electrode exposure area is subjected to glue coating, exposure and etching treatment again, the rest silicon oxide layer and the polysilicon layer in the exposure area are removed in the etching process, the etching process is stopped on the grid electrode oxide layer, and finally the photoresist is completely removed, so that the selective grid electrode and all grid electrode structures of the split grid electrode can be obtained.

Further, the storage medium layer comprises a silicon oxide-silicon nitride-silicon oxide film layer.

The grid forming method of the split grid improves the grid forming process of the split grid, and obtains the selection grid and the control grid in vertical shapes under the split grid structure. Compared with the method for forming the control grid by adopting the polysilicon side wall etching in the prior art, the method adopts the two-time forming and self-aligning method, so that the control grid which simultaneously meets the requirements of the size and shape process can be easily obtained under the split grid structure. The process flow reduces the difficulty of grid etching in the original process flow, and simultaneously, the conditions such as the growth thickness of a film layer and the like in the process development are easier to determine. Furthermore, the invention also improves the area utilization rate of the storage area.

Drawings

Fig. 1 is a schematic diagram of the structure of a control gate and a select gate formed by a conventional split gate process.

Fig. 2a to 2p are schematic structural diagrams illustrating a method for forming a split gate according to a preferred embodiment of the invention.

Detailed Description

The following description will be given with reference to the accompanying drawings, but the present invention is not limited to the following embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is noted that the drawings are in greatly simplified form and that non-precision ratios are used for convenience and clarity only to aid in the description of the embodiments of the invention.

Referring to fig. 2a to 2p, fig. 2a to 2p are schematic structural diagrams illustrating a method for forming a gate of a split gate according to a preferred embodiment of the invention.

The invention provides a grid forming method of a split gate, which comprises the following steps:

forming an initial film layer 200 according to a gate (select gate) film layer structure formed later, where the initial film layer 200 includes a gate oxide layer 210, a polysilicon layer 220, a silicon oxide layer 230, and a silicon nitride layer 240, which are sequentially disposed on the substrate layer 100 from bottom to top, as shown in fig. 2 a;

exposing and etching the initial film layer 200 to form a plurality of trench structures, as shown in fig. 2 b;

growing a storage medium layer 300 on the above structure, as shown in fig. 2c, wherein the storage medium layer 300 includes a silicon oxide-silicon nitride-silicon oxide film layer;

growing a polysilicon film 400 on the structure, performing chemical mechanical polishing, and stopping polishing until the storage medium layer 300 is polished, so that the trenches are filled with the polysilicon 400, as shown in fig. 2 d;

etching the exposed storage medium layer 300, so that the etching process is stopped on the silicon nitride layer 240, as shown in fig. 2 e;

etching the exposed polysilicon 400 to adjust the height thereof in the trench, as shown in fig. 2 f;

growing the silicon oxide film 500, followed by chemical mechanical polishing, and stopping when the polishing process reaches the silicon nitride layer 240, so that the upper portion of the polysilicon 400 in the trench is filled with the silicon oxide film 500, as shown in fig. 2 g;

adjusting the height difference by using the exposed silicon oxide film 500 as a mask, and adjusting the thickness of the silicon nitride layer 240 to a desired thickness, as shown in fig. 2 h;

coating a photoresist 600 on the surface of the structure, exposing to display the control gate exposed area, as shown in fig. 2i, removing the silicon nitride layer 240 in the exposed area by wet etching on the basis, and removing the remaining silicon oxide film 230 and the polysilicon film 220 in the central gate structure of the exposed area by dry etching, as shown in fig. 2 j;

removing the photoresist 600, and removing the exposed storage medium layer 300 by using isotropic etching, as shown in fig. 2 k;

removing all the silicon oxide film layer 500 on the top of the control gate by wet etching to form a control gate CG as shown in FIG. 2 l;

coating a photoresist 600 on the surface of the structure, then exposing the selective gate exposure area as shown in fig. 2m, then carrying out dry etching by taking the selective gate exposure area as a mask, stopping the etching process on the silicon oxide layer 230, and avoiding the loss of polysilicon as shown in fig. 2 n;

after the photoresist 600 is removed, the select gate exposed area is again subjected to photoresist coating, exposure (as shown in fig. 2 o) and etching treatment, the etching process removes the remaining silicon oxide layer 230 and the polysilicon layer 220 in the exposed area, stops the etching process on the gate oxide layer 210, and finally removes all the photoresist 600, so as to obtain the select gate SG and all the gate structures of the split gate, as shown in fig. 2 p.

In summary, the split-gate forming method provided by the invention improves the split-gate forming process, and obtains the selection gate and the control gate with vertical appearances under the split-gate structure. Compared with the method for forming the control grid by adopting the polysilicon side wall etching in the prior art, the method adopts the two-time forming and self-aligning method, so that the control grid which simultaneously meets the requirements of the size and shape process can be easily obtained under the split grid structure. The process flow reduces the difficulty of grid etching in the original process flow, and simultaneously, the conditions such as the growth thickness of a film layer and the like in the process development are easier to determine. Furthermore, the invention also improves the area utilization rate of the storage area.

Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention should be determined by the appended claims.

Claims

1. A method for forming a split gate includes the following steps:

forming an initial film layer according to the post-formed gate film layer structure, wherein the initial film layer comprises a gate oxide layer, a first polycrystalline silicon layer, a first silicon oxide layer and a silicon nitride layer which are sequentially arranged on the substrate layer from bottom to top;

growing a storage medium layer on the bottom wall and the side wall of the groove structure and the silicon nitride layer;

growing a second polysilicon layer on the storage medium layer, carrying out chemical mechanical polishing, and stopping polishing until the storage medium layer is polished, so that the groove is filled with polysilicon;

growing a second silicon dioxide layer, then carrying out chemical mechanical polishing, and stopping when the polishing process reaches the silicon nitride layer, so that the upper part of the polysilicon in the groove is filled with the second silicon dioxide layer;

adjusting the thickness of the silicon nitride layer to a required thickness by taking the exposed second silicon dioxide layer as a mask;

coating photoresist on the surfaces of the silicon nitride layer and the second silicon dioxide layer, exposing to open a control grid electrode exposure area, removing the silicon nitride layer in the exposure area through wet etching on the basis, and removing the first silicon oxide layer and the first polysilicon layer which are left in the central grid structure of the exposure area through a dry etching method;

removing the second silicon dioxide layer on the top of the control grid by adopting a wet etching method to form the control grid;

coating photoresist on the surfaces of the silicon nitride layer, the control grid and the grid oxide layer, then exposing a selective grid exposure area, and then carrying out dry etching by taking the selective grid exposure area as a mask plate, and stopping the etching process on the silicon oxide layer;

after the photoresist is removed, the selective grid electrode exposure area is subjected to glue coating, exposure and etching treatment again, the remaining first silicon oxide layer and the first polycrystalline silicon layer in the exposure area are removed in the etching process, the etching process is stopped on the grid electrode oxide layer, and finally the photoresist is completely removed, so that the selective grid electrode and all grid electrode structures of the split grid electrode can be obtained.

2. The method of claim 1, wherein the storage dielectric layer comprises a silicon oxide-silicon nitride-silicon oxide film.