CN102623340A

CN102623340A - Method for preparing groove-type double-layer grid MOS device

Info

Publication number: CN102623340A
Application number: CN2011100279393A
Authority: CN
Inventors: 丛茂杰; 缪进征; 金勤海
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2011-01-26
Filing date: 2011-01-26
Publication date: 2012-08-01
Anticipated expiration: 2031-01-26
Also published as: CN102623340B

Abstract

The invention discloses a method for preparing a groove-type double-layer grid MOS device, comprising the following steps: after depositing a first layer of polysilicon, carrying out back-etching on the first layer of polysilicon in all grooves to reduce the depth of the first layer of polysilicon to a predetermined depth, and forming a first layer of polysilicon grid; after forming the first layer of polysilicon grid, filling the grooves by depositing a dielectric layer, then covering a position of the first layer of polysilicon grid preset for metal connecting, by utilizing photoetching technology with photoresist, and forming an intermediate dielectric layer between the double layers of the grid in the grooves by etching the exposed dielectric layer; and in the preparation process of a contact hole, etching the dielectric layer to the first layer of polysilicon grid preset for metal connecting. Method of the invention assists in simplifying a preparation flow, thereby reducing production cost.

Description

Groove type double-layer grid MOS preparation of devices method

Technical field

The present invention relates to a kind of groove type double-layer grid MOS preparation of devices method.

Background technology

Double-deck grid MOS structure is a kind of power MOS (Metal Oxide Semiconductor) device commonly used.The technological process that has general double-deck grid MOS structure now is:

The hard mask layer of growth etching groove on substrate is generally one deck or two-layer silicon oxide layer earlier;

Then the position of lithographic definition groove is followed etching and is formed groove;

Afterwards in trench wall growth oxide layer;

Then deposit ground floor polysilicon filling groove carries out the etching first time to the ground floor polysilicon afterwards, removes to be positioned at the ground floor polysilicon on the groove;

Photoetching then protection part ground floor polysilicon (promptly be used for connect as the ground floor polysilicon part) carries out the second step etching of ground floor polysilicon, the desired depth to the groove;

Adopt high-density plasma (HDP) technology deposition oxidation film (also claiming the HDP oxide-film), filling groove;

Adopt cmp (CMP) technology to grind the HDP oxide-film, to the thick HDP oxide-film of residue 3000 dusts on substrate;

Wet etching makes the HDP oxide-film of residue 2500 dusts on the ground floor polysilicon in the groove, forms the intermediate oxide layer of double-deck grid;

Then be the growth of grid oxic horizon, the deposit of second layer polysilicon and etching, the preparation (see figure 1) of whole double-deck grid MOS is accomplished in the formation of tagma and source region formation and contact hole, metal and passivation layer etc.

In above-mentioned flow process, the ground floor polysilicon needs twice etching, and a photoetching make whole flow process comparatively complicated, and preparation cost is higher.

Summary of the invention

The technical problem that the present invention will solve provides a kind of groove type double-layer grid MOS preparation of devices method, and it has the flow process of simplification.

For solving the problems of the technologies described above, groove type double-layer grid MOS preparation of devices method of the present invention comprises the steps:

After the deposit of ground floor polysilicon, the ground floor polysilicon in all grooves returned carve to desired depth, form the ground floor polysilicon gate;

After the ground floor polysilicon gate forms; The dielectric layer deposited filling groove; Utilize photoetching process to make photoresist cover preset carrying out on the ground floor polysilicon gate position that metal connects afterwards, then the dielectric layer that comes out of etching forms the middle dielectric layer between the double-deck grid in groove;

Prepare in the process at contact hole, the said dielectric layer of etching is to the preset ground floor polysilicon gate that carries out the metal connection.

Among the groove-shaped upper strata grid MOS preparation method among the present invention, the erosion that anti-carves of ground floor polysilicon is comprehensive etching, does not need photoetching.And when contact hole prepares; Ground floor polysilicon (ground floor polysilicon gate) exit etching depth is darker; The dielectric layer etching requires that silicon is had very high selection ratio; Usually require to reach more than 15: 1, thereby the loss amount of source class exit and second layer polysilicon exit silicon can be controlled in 1000 dusts.Adopt method of the present invention, simplified preparation flow, thereby reduced production cost.

Description of drawings

Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:

Fig. 1 is the prepared groove type double-layer grid MOS structural representation of existing method;

Fig. 2 is for adopting the structural representation behind the etching groove in the method for the present invention;

Fig. 3 is the structural representation after the ground floor polysilicon gate forms in the employing method of the present invention;

Fig. 4 is the structural representation after second layer polysilicon gate forms in the employing method of the present invention;

Fig. 5 is the structural representation after contact hole forms in the employing method of the present invention;

Fig. 6 is the structural representation after metal level forms in the employing method of the present invention.

Embodiment

Groove-shaped upper strata grid MOS preparation method of the present invention, improvement and optimization for to original technology are mainly reflected in the following aspects:

(1) after the deposit of ground floor polysilicon, the ground floor polysilicon in all grooves returned carve to desired depth, form the ground floor polysilicon gate.What be the ground floor polysilicon anti-carves erosion for comprehensive etching, does not need photoetching.The degree of depth of all ground floor polysilicons is all identical.

(2) after the ground floor polysilicon gate forms; The dielectric layer deposited filling groove; Utilize photoetching process to make photoresist cover preset carrying out on the ground floor polysilicon gate position that metal connects afterwards, then the dielectric layer that comes out of etching forms the middle dielectric layer between the double-deck grid in groove.This step is with former identical in steps, is in the original step, the photoresist protection be the ground floor polysilicon gate it under, and in the present invention, the photoresist protection be that dielectric layer on the ground floor polysilicon gate is not etched.

(3) prepare in the process at contact hole, the said dielectric layer of etching is to the preset ground floor polysilicon gate that carries out the metal connection.The etching depth of the contact hole on the ground floor polysilicon gate is darker.Contact hole etching is divided into two stages, at first is etching dielectric layer, etch silicon afterwards.On the ground floor polysilicon gate, need the dielectric layer of etching thicker (reaching 1.15 microns places below the silicon face usually).So adopt dielectric layer that silicon is had the very etching condition of high selectivity, require usually to reach more than 15: 1, thereby the loss amount of the silicon of source class exit and second layer polysilicon exit is controlled in 1000 dusts.The etching of contact hole silicon and existing technology are basic identical, make the source class exit contact hole etching degree of depth reach desired value, usually 2000 dust to 5000 dusts below silicon face.Through above-mentioned improvement, reduce production costs.

Following brief account is used the preparation method's of groove type double-layer grid MOS of the present invention instance.

At first form the groove (see figure 2) on the etched substrate.Usually before etching, also can on groove, deposit adopt photoetching process to define position of groove etc. afterwards as the hard mask layer of etching.

Then at trench wall somatomedin layer.This dielectric layer is generally silicon oxide layer, forms through hot oxygen technology.

Deposit ground floor polysilicon on substrate is with filling groove.The deposit of polysilicon can be adopted CVD method usually.

Next anti-carve the desired depth in erosion ground floor polysilicon to the groove, form ground floor polysilicon gate (see figure 3).This desired depth is the degree of depth of ground floor polysilicon in the double-deck grid structure.And in common process, the etching of polysilicon was divided into for two steps usually, and first etching is removed and is positioned at the ground floor polysilicon on the groove, and the protection of photoetching then is as the part polysilicon of ground floor polysilicon exit, and then the polysilicon in the etching groove is to desired depth.In the method for the present invention, omit photoetching process one time, saved a mask blank.

After the ground floor polysilicon gate forms, the preparation middle dielectric layer.Be the dielectric layer deposited filling groove earlier, utilize photoetching process to make photoresist cover the predetermined position that forms the ground floor polysilicon gate that connects afterwards, follow the dielectric layer that etching comes out and in groove, form the middle dielectric layer between the double-deck grid.

Then at the sidewall of groove first half growth grid oxic horizon.Usually adopt hot oxygen technology, form compact oxide.

Next be the deposit of second layer polysilicon, filling groove, removal afterwards is positioned at the second layer polysilicon on the groove, forms second layer polysilicon gate (see figure 4).The deposit of second layer polysilicon is similar with the ground floor polysilicon, can adopt identical technology.

Be conventional technological process below; The formation in active area and tagma; Follow the deposit interlayer dielectric layer, then lithographic definition goes out the position of contact hole, and the etching interlayer dielectric layer is respectively at the source electrode exit afterwards; Form source electrode contact hole, ground floor polysilicon gate contact hole and second layer polysilicon gate contact hole (see figure 5) on the first polysilicon exit and the second polysilicon exit.In the etching of contact hole, adopt dielectric layer that silicon is had the etching technics of high selectivity, usually greater than being 15: 1.

For depositing metal forms contacting metal and metal wire, accomplish MOS preparation of devices (see figure 6) at last.

Claims

1. a groove type double-layer grid MOS preparation of devices method is characterized in that, comprises the steps:

After the deposit of ground floor polysilicon, the said ground floor polysilicon in all grooves returned carve to desired depth, form the ground floor polysilicon gate;

After said ground floor polysilicon gate forms; Dielectric layer deposited is filled said groove; Utilize photoetching process to make photoresist cover preset carrying out on the ground floor polysilicon gate position that metal connects afterwards, then the said dielectric layer that comes out of etching forms the middle dielectric layer between the double-deck grid in groove;

2. preparation method as claimed in claim 1 is characterized in that, concrete step is:

Step 1 forms groove on the etched substrate;

Step 2 is at said trench wall somatomedin layer;

Step 3, deposit ground floor polysilicon on substrate, this ground floor polysilicon is filled said groove;

Step 4, desired depth in the said ground floor polysilicon of etching to the groove forms the ground floor polysilicon gate;

Step 5, dielectric layer deposited are filled said groove, utilize photoetching process to make photoresist cover the predetermined position that forms the ground floor polysilicon gate that connects afterwards, and then the said dielectric layer that comes out of etching forms the middle dielectric layer between the double-deck grid in groove;

Step 6 is at trenched side-wall growth grid oxic horizon;

Step 7 is carried out the growth of second layer polysilicon and is filled said groove, and the said second layer polysilicon of etching forms second layer polysilicon gate afterwards;

Step 8, the deposit interlayer dielectric layer is followed in the formation in source region and tagma, and then lithographic definition goes out the position of contact hole, and the said interlayer dielectric layer of etching forms source electrode contact hole, ground floor polysilicon gate contact hole and second layer polysilicon gate contact hole afterwards.

3. according to claim 1 or claim 2 preparation method, it is characterized in that: said dielectric layer and interlayer dielectric layer are silicon oxide layer.

4. preparation method as claimed in claim 3 is characterized in that: in the contact hole preparation, comprise and adopt silica that silicon is had the etching condition more than or equal to the ratio of the selection more than 15.