CN108152767A - A kind of magnetic resonance signal real-time processing method based on FPGA - Google Patents
A kind of magnetic resonance signal real-time processing method based on FPGA Download PDFInfo
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- CN108152767A CN108152767A CN201711233672.7A CN201711233672A CN108152767A CN 108152767 A CN108152767 A CN 108152767A CN 201711233672 A CN201711233672 A CN 201711233672A CN 108152767 A CN108152767 A CN 108152767A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R33/20—Arrangements or instruments for measuring magnetic variables involving magnetic resonance
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Abstract
The invention discloses a kind of magnetic resonance signal real-time processing methods based on FPGA, this method establishes the magnetic resonance signal processing system realized using programmable logic device FPGA, realizes high-speed AD real-time data acquisition, storage and transmission with data after the digital down conversion system and down coversion of the variable bandwidth and extraction rate of phase and orthogonal channel.Different parameters can be configured by PC machine, modified to Digital Down Convert structure, to adapt to various specific design requirements using the advantages such as the repeatable programming of FPGA, flexibility be strong by the present invention.
Description
Technical field
The present invention relates to mr techniques, signal processing and data communication.Particularly a kind of magnetic resonance of bandwidth varying
The method of real time signal processing.
Background technology
The real time signal processing of magnetic resonance signal mainly includes signal acquisition, digital down-conversion technology and signal transmission.
And digital down-conversion technology is a vital ring in acquisition of magnetic resonance signals processing.At present, the technology is mainly by dedicated
Digital Down Convert chip is realized, DSP is realized.Special purpose DDC chip is stable and to use difficulty low, but its is expensive, and logical
Road number is restricted, and different customizations can not be carried out according to different demands, and the completion of integral product can be limited to chip
Supply.Although the DSP implementation methods energy various digital signals of high speed processing, since the AD sampling rates of prime are higher and higher,
Requirement of the Digital Signal Processing of high speed for DSP is excessively high, and the system that monolithic dsp chip realizes entire DDC can not only be used only.
Invention content
The purpose of the present invention is in view of the deficiencies of the prior art and provide a kind of magnetic resonance signal based on FPGA it is real-time
Processing method, this method are established the magnetic resonance signal processing system realized using programmable logic device FPGA, provide magnetic
The real-time processing scheme of resonance signal is filled up the bandwidth varying lacked in the market and the Digital Down Convert scheme for extracting rate, is realized
The storage and transmission of data after the high-speed sampling and down coversion of magnetic resonance signal.
Realizing the specific technical solution of the object of the invention is：
A kind of magnetic resonance signal real-time processing method based on FPGA, feature are that this method includes step in detail below：
Step 1：Establish acquisition of magnetic resonance signals system
Foundation includes power module, high speed serialization A/D chip, programmable logic device（FPGA）, DDR3 memory modules, PCI9054
Chip, pci bridge chip, storage medium, PC machine acquisition of magnetic resonance signals system, wherein, power module and high speed serialization AD cores
Piece, programmable logic device, DDR3 memory modules, PCI9054 chips are connected；High speed serialization A/D chip and programmable logic device
Part is connected；Programmable logic device is connected with high speed serialization A/D chip, DDR3 memory modules, PCI9054 chips；DDR3 is deposited
Storage module is connected with programmable logic device；PCI9054 chips and programmable logic device, pci bridge chip, storage medium phase
Connection；Pci bridge chip is connected with PC machine；Storage medium is connected with PCI9054 chips；PC machine is connected with pci bridge chip；
Step 2：High speed serialization AD real-time samplings, specifically include：
2.1：Sampling clock is exported using FPGA, and sends the register of instruction change high speed serialization A/D chip, is at following
Ring generates the pattern of specified training sequence；
2.2：The data read under 2.1 patterns are judged using FPGA, identify whether, tune consistent with specified training sequence
The integrated mode of whole serial data, until gathered data is consistent with specified training sequence；
2.3：It after 2.2 reach, is sent and instructed using FPGA, change the register of high speed serialization A/D chip, be at normal
Sampling configuration；
2.4：Data acquisition and the serioparallel exchange of data are carried out using FPGA；
Step 3：The mixing of data-signal, specifically includes：
3.1：Phase generator and SIN/COS look-up tables are established using FPGA programmings, phase generator generates suitable phase ginseng
It measures and is mapped by searching for table, construct the sine wave of variable frequency, establish digital controlled oscillator（NCO）；
3.2：Parameter/configuration interface is configured using PC machine, is set according to the centre frequency of the carrier wave of prime magnetic resonance signal
Digital controlled oscillator generates the centre frequency of data, exports identical two-way frequency, quadrature in phase in-phase signal and orthogonal letter respectively
Number；
3.3：The data that sampling obtains are converted into after parallel data and are respectively enterd all the way with phase down coversion channel and orthogonal lower change
Frequency channel carries out the down-converted of rear class；
3.4：By digital controlled oscillator generate in-phase signal be multiplied with the data in same phase down coversion channel, orthogonal signalling with it is orthogonal
Data in down coversion channel are multiplied；
3.5：The data of two paths are done into low level interception, respectively obtain the data of two-way 32bit；
Step 4：Digital Down Convert is carried out, is specifically included：
4.1：Parameter/configuration interface is configured using PC machine, obtains extracting the bandwidth of rate and output data；
4.2：The extracting multiple of 2 groups of multistage CIC decimation filters, coefficient, the semi-band filtering of CIC compensating filters are obtained by 4.1
Device group uses the control of the channel of number and output data and the coefficient of FIR filter；
4.3：The coefficient generated by 4.2, the IP kernel that the cic filter in the IP kernel provided is opened using FPGA programming softwares are built
Vertical CIC decimation filters establish half-band filter group and FIR filter using the IP kernel of FIR filter；
4.4：Data after the mixing of two routing steps 3 are respectively by two-stage CIC decimation filters and its corresponding CIC compensation
Wave filter does data low level interception, obtains the data carried out after large sampling rate extraction of two-way 32bit；
4.5：Confirm the usage quantity of half-band filter, select the connection mode of half-band filter group, lead to 4.4 obtained data
The half-band filter group being configured is crossed, low level interception is done to the data of filtered device group, the completion for obtaining two-way 32bit is extracted
Data afterwards；
4.6：By 4.5 the data obtaineds by FIR shaping filters, data are done with low level interception, obtains the data exported to the end, number
According to bandwidth and data transfer rate；
Step 5：Step 4 the data obtained is read out and stored, is specifically included：
5.1：The FIFO IP kernels in the IP kernel provided, which are opened, using FPGA programming softwares establishes pushup storage queue；
5.2：Since pushup storage queue can be written and read operation respectively using different independent clocks, using first entering
First go out storage queue change data output speed and the reading rate of DDR3, by the data deposit large capacity after down coversion
In DDR3, the data volume until storing enough processing；
5.3：Using PCI communication modes, PC machine reading is made to be stored in the data after the down coversion in DDR3, the data obtained is stored
In file in PC machine, in case follow-up data is handled.
Compared with prior art, the beneficial effects of the invention are as follows：
(1) present invention realized using FPGA, can be custom-configured according to different project demands, and can with when it is all
Into, update.It can be changed according to user demand and extract rate and output signal bandwidth, flexibility is strong；
(2) down conversion filter structure provided by the invention can provide high power and extract rate, adapt to the magnetic resonance letter of various bandwidth
Number processing；
(3) present invention stores the data after down coversion using the DDR3 of two panels 1G memories, and the storage of large capacity can make PC
The digital independent of machine possesses time tolerance.And realize the storage and update of real time data, carry out subsequent processing convenient for PC machine；
(4) present invention can be applied not only to magnetic resonance signal processing, can be used for what institute's Digital Down Convert in need was handled
Communication system, universality are extensive.
Description of the drawings
Fig. 1 is the acquisition of magnetic resonance signals system structure diagram of the present invention；
Fig. 2 is the Digital Down Convert structure chart of the present invention；
Fig. 3 is flow diagram of the present invention.
Specific embodiment
Refering to Fig. 1, the acquisition of magnetic resonance signals system of this method includes power module 1, high speed serialization A/D chip 2, can compile
Journey logical device（FPGA）3rd, DDR3 memory modules 4, PCI9054 chips 5, pci bridge chip 6, storage medium 7, PC machine 8.This hair
The bright acquisition of magnetic resonance signals that high speed is carried out by high speed serialization A/D chip 2, and to using programmable logic device（FPGA）3 carry out
Serioparallel exchange.If training sequence matches, programmable logic device（FPGA）3 correct collecting magnetic resonance signals, and programmable
Logical device（FPGA）The conversion of Digital Down Convert is carried out in 3, parameters pass through PCI9054 chips 5, PCI Bridge by PC machine 8
Chip 6 is configured, and later stores transformed data-signal into DDR3 memory modules 4, and PCI9054 chips 5 are by storing
Medium 7 carries out power on configuration, and the data being stored in DDR3 memory modules 4 are after PC machine 8 sends out and reads signal, by PCI9054
Chip 5, pci bridge chip 6 are sent to PC machine 8 and carry out data storage, in case follow-up data is handled.
Referring to Fig.2, the Digital Down Convert structure of the present invention is as follows：Magnetic resonance signal carries out data by high speed serialization AD
After serioparallel exchange, respectively enter all the way with phase down coversion channel and all the way quadrature frequency conversion channel and carry out at the down coversion of rear class
Reason.Parameter/configuration interface is configured using PC machine, numerical control is set according to the centre frequency of the carrier wave of prime magnetic resonance signal
Oscillator generates the centre frequency of data, exports identical two-way frequency, in-phase signal of quadrature in phase and orthogonal signalling respectively；It will
The in-phase signal that digital controlled oscillator generates is multiplied with the data in same phase down coversion channel（It is mixed）, orthogonal signalling with it is orthogonal under
Data in frequency conversion channel are multiplied, and the data of two paths are done low level interception later, respectively obtain the data of two-way 32bit,
Carry out follow-up data extraction and down-converted.Parameter/configuration interface is configured using PC machine, obtain extract rate with
And the bandwidth of output data；Determine the extracting multiple of CIC decimation filters, the coefficient of CIC compensating filters, half-band filter group
Use the channel of number and output data control and FIR filter coefficient；Data after two-way mixing are respectively according to each
From channel pass through CIC decimation filters and its corresponding CIC compensating filter, half-band filter group and FIR shapings
Wave filter finally does data low level interception, it is required that output data, data bandwidth and data transfer rate.
Refering to Fig. 3, after providing power supply for acquisition of magnetic resonance signals system, the access input at high speed serialization A/D chip 2
High-frequency signal.Carry out parameter configuration using PC machine, including digital controlled oscillator generate the centre frequencies of data, data pick-up rate and
Data bandwidth carries out down conversion system configuration according to given parameters, and signal processing is carried out to the obtained signal of sampling, store to
In DDR3, when PC machine provide read signal after by down coversion after the data obtained be uploaded to PC machine, preserve to specified file, in case
Follow-up data processing.
Claims (1)
1. a kind of magnetic resonance signal real-time processing method based on FPGA, which is characterized in that this method includes step in detail below：
Step 1：Establish acquisition of magnetic resonance signals system
Foundation includes power module（1）, high speed serialization A/D chip（2）, programmable logic device（FPGA）（3）, DDR3 storage mould
Block（4）, PCI9054 chips（5）, pci bridge chip（6）, storage medium（7）PC machine（8）Acquisition of magnetic resonance signals system；
Wherein, power module（1）With high speed serialization A/D chip（2）, programmable logic device（3）, DDR3 memory modules（4）、
PCI9054 chips（5）It is connected；High speed serialization A/D chip（2）With programmable logic device（3）It is connected；Programmable logic device
Part（3）With high speed serialization A/D chip（2）, DDR3 memory modules（4）, PCI9054 chips（5）It is connected；DDR3 memory modules（4）With
Programmable logic device（3）It is connected；PCI9054 chips（5）With programmable logic device（3）, pci bridge chip（6）, storage be situated between
Matter（7）It is connected；Pci bridge chip（6）With PC machine（8）It is connected；Storage medium（7）With PCI9054 chips（5）It is connected；PC
Machine（8）With pci bridge chip（6）It is connected；
Step 2：High speed serialization AD real-time samplings, specifically include：
2.1：Sampling clock is exported using FPGA, and sends the register of instruction change high speed serialization A/D chip, is at following
Ring generates the pattern of specified training sequence；
2.2：The data read under 2.1 patterns are judged using FPGA, identify whether, tune consistent with specified training sequence
The integrated mode of whole serial data, until gathered data is consistent with specified training sequence；
2.3：It after 2.2 reach, is sent and instructed using FPGA, change the register of high speed serialization A/D chip, be at normal
Sampling configuration；
2.4：Data acquisition and the serioparallel exchange of data are carried out using FPGA；
Step 3：The mixing of data-signal, specifically includes：
3.1：Phase generator and SIN/COS look-up tables are established using FPGA programmings；
3.2：Continuous Phase Parameter is generated using phase generator and is mapped by searching for table, constructs the sine of variable frequency
Wave establishes digital controlled oscillator（NCO）；
3.3：Parameter/configuration interface is configured using PC machine, is set according to the centre frequency of the carrier wave of prime magnetic resonance signal
Digital controlled oscillator generates the centre frequency of data, exports identical two-way frequency, quadrature in phase in-phase signal and orthogonal letter respectively
Number；
3.4：The data that sampling obtains are converted into after parallel data and are respectively enterd all the way with phase down coversion channel and orthogonal lower change
Frequency channel carries out the down-converted of rear class；
3.5：By digital controlled oscillator generate in-phase signal be multiplied with the data in same phase down coversion channel, orthogonal signalling with it is orthogonal
Data in down coversion channel are multiplied；
3.6：The data of two paths are done into low level interception, respectively obtain the data of two-way 32bit；
Step 4：Digital Down Convert is carried out, is specifically included：
4.1：Parameter/configuration interface is configured using PC machine, obtains extracting the bandwidth of rate and output data；
4.2：The extracting multiple of two groups of multistage CIC decimation filters, coefficient, the semi-band filtering of CIC compensating filters are obtained by 4.1
Device group uses the control of the channel of number and output data and the coefficient of FIR filter；
4.3：The coefficient generated by 4.2, the IP kernel that the cic filter in the IP kernel provided is opened using FPGA programming softwares are built
Vertical CIC decimation filters establish half-band filter group and FIR filter using the IP kernel of FIR filter；
4.4：Data after the mixing of two routing steps 3 are respectively by two-stage CIC decimation filters and its corresponding CIC compensation
Wave filter does data low level interception, obtains the data carried out after large sampling rate extraction of two-way 32bit；
4.5：Half-band filter group and its connection mode has been configured in the use number of the half-band filter group obtained using 4.2,
Low level interception is done to the data of filtered device group, obtains the data after the completion extraction of two-way 32bit；
4.6：By 4.5 the data obtaineds by FIR shaping filters, data are done with low level interception, obtains the data exported to the end, number
According to bandwidth and data transfer rate；
Step 5：Step 4 the data obtained is read out and stored, is specifically included：
5.1：The FIFO IP kernels in the IP kernel provided, which are opened, using FPGA programming softwares establishes pushup storage queue；
5.2：Using pushup storage queue change data output speed and the reading rate of DDR3, by the number after down coversion
In DDR3 according to deposit large capacity, the data volume until storing enough processing；
5.3：Using PCI communication modes, PC machine reading is made to be stored in the data after the down coversion in DDR3, the data obtained is stored
In file in PC machine, in case follow-up data is handled.
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| CN109408434A (en) * | 2018-09-03 | 2019-03-01 | 上海威固信息技术股份有限公司 | A kind of multipath high-speed AD data acquisition and storage system based on FPGA |
| CN109633759A (en) * | 2018-12-12 | 2019-04-16 | 吉林大学 | Ground magnetic resonance signal rapidly extracting device and method based on phase lock amplifying technology |
| CN109669117A (en) * | 2019-01-22 | 2019-04-23 | 华东师范大学 | A kind of adjustable difference LVDS test device of amplitude-frequency |
| CN109918197A (en) * | 2019-02-15 | 2019-06-21 | 中科驭数（北京）科技有限公司 | Data processing equipment |
| CN112015693A (en) * | 2020-07-31 | 2020-12-01 | 成都中安频谱科技有限公司 | Method and system for realizing large-scale DDC (direct digital control) based on FPGA (field programmable Gate array) |
| CN112763956A (en) * | 2020-12-29 | 2021-05-07 | 电子科技大学 | Method for increasing dynamic range of magnetic resonance signal by scrambling technique |
| CN113485177A (en) * | 2021-06-24 | 2021-10-08 | 西安电子科技大学 | Multi-channel signal preprocessing system and method based on FPGA |
| CN117331009A (en) * | 2023-12-01 | 2024-01-02 | 中国科学技术大学先进技术研究院 | Spectrometer receiving method and device |
| CN117872239A (en) * | 2023-11-22 | 2024-04-12 | 北京大学深圳研究生院 | Multi-channel data acquisition system applied to ultra-high field magnetic resonance imaging |
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| CN109408434B (en) * | 2018-09-03 | 2021-11-30 | 上海威固信息技术股份有限公司 | Multi-path high-speed AD data acquisition and storage system based on FPGA |
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| CN109669117A (en) * | 2019-01-22 | 2019-04-23 | 华东师范大学 | A kind of adjustable difference LVDS test device of amplitude-frequency |
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| CN112015693A (en) * | 2020-07-31 | 2020-12-01 | 成都中安频谱科技有限公司 | Method and system for realizing large-scale DDC (direct digital control) based on FPGA (field programmable Gate array) |
| CN112763956A (en) * | 2020-12-29 | 2021-05-07 | 电子科技大学 | Method for increasing dynamic range of magnetic resonance signal by scrambling technique |
| CN112763956B (en) * | 2020-12-29 | 2022-02-15 | 电子科技大学 | Method for increasing dynamic range of magnetic resonance signal by scrambling technique |
| CN113485177A (en) * | 2021-06-24 | 2021-10-08 | 西安电子科技大学 | Multi-channel signal preprocessing system and method based on FPGA |
| CN117872239A (en) * | 2023-11-22 | 2024-04-12 | 北京大学深圳研究生院 | Multi-channel data acquisition system applied to ultra-high field magnetic resonance imaging |
| CN117331009A (en) * | 2023-12-01 | 2024-01-02 | 中国科学技术大学先进技术研究院 | Spectrometer receiving method and device |
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