CN104320088A - Digital down conversion electric circuit - Google Patents

Abstract

The invention discloses a digital down conversion electric circuit. The digital down conversion electric circuit comprises a data preprocessing module and a frequency mixing module, and is characterized in that an I circuit output end of the frequency mixing module and a Q circuit output end of the frequency mixing module are respectively and sequentially connected with a first CIC smoothing extraction circuit, a second CIC smoothing extraction circuit, an HB smoothing extraction circuit and an FIR smoothing extraction circuit, the first CIC smoothing extraction circuit, the second CIC smoothing extraction circuit, the HB smoothing extraction circuit and the FIR smoothing extraction circuit are all connected with a controller, the first CIC smoothing extraction circuit, the second CIC smoothing extraction circuit and the HB smoothing extraction circuit are further connected with bypass option switches, and when one bypass option switch is turned on, extraction rate of the stage circuit corresponding to the bypass option switch which is turned on is 1. The digital down conversion electric circuit has the significant effects of being simple in structure, convenient to control, and capable of flexibly configuring the signal processing bandwidth in a range of 100-400HZ when input signal sampling rate is 102.4MSPS.

Description

A kind of Digital Down Convert circuit

Technical field

The present invention relates to Digital Signal Processing, specifically, is a kind of Digital Down Convert circuit.

Background technology

In the process of receiver back end signal and software radio of extensive use at present, multirate signal processing is the item of digital signal processing technology grown up the nearest more than ten years, it be with filtering, extraction, in be inserted as basic means, by changing the sampling rate of signal to adapt to the needs of various processing digital signal, and Digital Down Convert (Digital Down Convert, DDC) is important component part wherein.

After Digital Down Convert (DDC) is positioned at high-speed a/d converter, according to needs and the disposal ability of follow-up signal process, suitable data sampling rate and process bandwidth are provided, so its arithmetic speed directly limit the most high sampling rate of A/D, and determine the maximum process bandwidth of receiver.

And current commercial digital low-converter has larger limitation, or be that the data sampling rate of input is not high enough, or the processed limited bandwidth system be to provide, compatible and flexibility is poor.

It is a kind of algorithms most in use structure realizing arrowband DDC shown in Fig. 1, comprising digital controlled oscillator (NCO), digital mixer, CIC (Cascaded Integrator Comb, cascaded integrator-comb) decimation filter, HB (Half Band, half band) decimation filter, FIR (Finite Impulse Response, finite impulse response) filter and the module such as optimum configurations and control, owing to adopting cic filter, when realizing arrowband demand, be limited to the maximum extraction yield of cic filter, the process bandwidth range that therefore can provide is little, generally be no more than 1MHz, be difficult to adapt to application demand.

Summary of the invention

Only in view of this, in order to provide wider signal transacting bandwidth, the various different signal transacting demand of flexible adaptation, give full play to the adaptable advantage of software radio, the invention provides a kind of Digital Down Convert circuit, the concrete technical scheme adopted is:

A kind of Digital Down Convert circuit, comprise data preprocessing module and frequency mixing module, described data preprocessing module is for realizing the collection of digital medium-frequency signal, described frequency mixing module comprises digital controlled oscillator, this digital controlled oscillator exports the mutually orthogonal local oscillation signal of two-way and realizes Frequency mixing processing with described intermediate-freuqncy signal, form the output of I road at the output of this frequency mixing module to export with Q road, its key is: the I road output of described frequency mixing module and Q road output are connected with a CIC filtering extraction circuit respectively in turn, 2nd CIC filtering extraction circuit, HB filtering extraction circuit and FIR filtering extraction circuit, described digital controlled oscillator, one CIC filtering extraction circuit, 2nd CIC filtering extraction circuit, HB filtering extraction circuit and FIR filtering extraction circuit are all connected with controller, this controller is for realizing parameter and the logic control of modules, at a described CIC filtering extraction circuit, 2nd CIC filtering extraction circuit and HB filtering extraction circuit are also connected with bypass selector switch, when a certain bypass selector switch is connected, the extraction yield of this that stage circuit corresponding to bypass selector switch is 1.

Can be found out by such scheme, this programme in conventional lower frequency changer circuit structure by setting up one-level CIC filtering extraction circuit, bypass selector switch is set up to CIC filtering extraction circuit at different levels and HB filtering extraction circuit simultaneously, when needs extremely wide process bandwidth time, two CIC filtering extraction circuit and the HB filtering extraction circuit of front end are set to bypass, are played filtering by FIR filtering extraction circuit and are provided the effect of maximum bandwidth; When needs minimum process bandwidth time, two, front end CIC filtering extraction circuit can extract very large extraction yield, again with HB filtering extraction circuit and FIR filtering extraction electrical combination, just larger extraction yield can be obtained, thus be easy to obtain extremely narrow process bandwidth, for being in other process bandwidth that can provide in bandwidth range, according to the controling parameters of the emphasis of application item by each circuit module of controller flexible configuration, thus best effect can be reached.

As further describing, described data preprocessing module comprises parallel/serial modular converter, FIFO buffer module and Logic control module, for adapting to the output of different A/D converter, realizes the sampling of digital medium-frequency signal.

In order to ensure the extraction yield meeting system, the 5 grades of cascades of a described CIC filtering extraction circuit sampling, the 6 grades of cascades of described 2nd CIC filtering extraction circuit sampling.

Further, the cascade progression scope of described HB filtering extraction circuit is 1 ~ 3.

Remarkable result of the present invention is:

Circuit structure is simple, it is convenient to control, when input signal sample rate is 102.4 MSPS (Million samples per second 1,000,000 extractions/second), signal transacting bandwidth can in the scope of 100Hz ~ 40MHz flexible configuration, the corresponding baseband signal data rate exported changes in the scope of 128SPS ~ 51.2MSPS, extends the signal transacting bandwidth of existing digital down converter.

Accompanying drawing explanation

Fig. 1 is the schematic block circuit diagram of existing digital down converter;

Fig. 2 is schematic block circuit diagram of the present invention;

Fig. 3 is the flow chart of data processing figure of digital controlled oscillator (NCO);

Fig. 4 is the flow chart of data processing figure of CIC filtering extraction circuit;

Fig. 5 is the flow chart of data processing figure of HB filtering extraction circuit;

Fig. 6 is the flow chart of data processing figure of FIR filtering extraction circuit.

Embodiment

Below in conjunction with accompanying drawing, the specific embodiment of the present invention and operation principle are described in further detail.

As shown in Figure 2, a kind of Digital Down Convert circuit, comprise data preprocessing module and frequency mixing module, described data preprocessing module comprises parallel/serial modular converter, FIFO buffer module and Logic control module, for adapting to the output of different A/D converter, realize the sampling of digital medium-frequency signal, described frequency mixing module comprises digital controlled oscillator, this digital controlled oscillator exports the mutually orthogonal local oscillation signal of two-way and realizes Frequency mixing processing with described intermediate-freuqncy signal, forms the output of I road export with Q road at the output of this frequency mixing module.

As can be seen from Figure 2, Digital Down Convert circuit receives the digital sample data exported from A/D converter from input after, first realize parallel/serial conversion and FIFO buffering by pretreatment module, form digital medium-frequency signal.

NCO in figure is digital controlled oscillator, can produce the local oscillation signal sin (ω that two-way is mutually orthogonal _cn) with cos (ω _cn), for sampling after digital medium-frequency signal X (n) carry out mixing, to realize the object of frequency conversion, its internal processes is shown in Fig. 3.It adopts look-up table to produce discrete sine signal, with 1/f during work _sfor periodical input data, often input data, the phase accumulator of NCO just increases by 2 π × f _lO/ f _sphase increment, then add that shake (Dither) value searches address as sine table using the phase place after cumulative, export the numerical value on this address, what obtain is exactly the sinusoidal sample value of this point, wherein f _lOfor local oscillating frequency, f _sfor the sample frequency of NCO input signal.

Frequency mixer recited above, carries out mixing calculating by from the digital local oscillator signal of NCO module and the digital intermediate frequency sampling signal of input, exports the mixed frequency signal I that I and Q two-way is mutually orthogonal ₀(n) and Q ₀(n), namely

I ₀(n)＝X(n)×cos(ω _cn)

Q ₀(n)＝X(n)×[-sin(ω _cn)]

After mixing, frequency is converted to base band, completes the frequency spectrum shift of digital intermediate frequency to base band.

I after mixing, the data transfer rate of Q signal are still the sample rate of digital intermediate frequency sampling signal, and data transfer rate is very high, need to carry out reduction of speed rate and extract process, realize undistorted extraction, must optimal design decimation filter to prevent frequency alias; According to system requirements, the mode of multi-stage cascade is adopted to realize the drop data rate process always extracting factor D.

Therefore, in the present invention, the I road output of described frequency mixing module and Q road output are connected with a CIC filtering extraction circuit respectively in turn, 2nd CIC filtering extraction circuit, HB filtering extraction circuit and FIR filtering extraction circuit, described digital controlled oscillator, one CIC filtering extraction circuit, 2nd CIC filtering extraction circuit, HB filtering extraction circuit and FIR filtering extraction circuit are all connected with controller, this controller is for realizing parameter and the logic control of modules, at a described CIC filtering extraction circuit, 2nd CIC filtering extraction circuit and HB filtering extraction circuit are also connected with bypass selector switch, when a certain bypass selector switch is connected, the extraction yield of this that stage circuit corresponding to bypass selector switch is 1.

Two CIC filtering extraction circuit recited above, namely CIC1 and CIC2 in Fig. 2, each CIC filtering extraction circuit is according to different application demands, adopt different cascade numbers, here CIC1 adopts 5 grades of cascades, and CIC2 adopts 6 grades of cascades, and the internal data handling process of the CIC1 module of 5 grades of cascades is shown in Fig. 4, the handling process of the CIC2 module of 6 grades of cascades is similar to the CIC1 module of 5 grades of cascades, just many increases by 1 grade.

By known to the CIC filtering extraction circuit analysis shown in Fig. 4, its impulse response is

The system function of multistage cic filter is

$H_N\left(z\right)={\left[\frac{1}{\mathrm{MR}}\frac{1-z^{-\mathrm{MR}}}{1-z^{-1}}\right]}^N$

Wherein R is delay factor, and general R=1 or 2, M is extracting multiple, and N is CIC cascade progression.

The frequency response of multistage cic filter is

$H_N\left(e^{\mathrm{j\ω}}\right)={\left[\frac{\sin \left(\frac{\mathrm{\ωM}}{2}\right)}{\sin \left(\frac{\mathrm{\ω}}{2}\right)}\right]}^N$

I, Q two-way mixed frequency signal of one CIC1 filtering extraction circuit to input carries out filtering and M ₁doubly extract, obtaining data transfer rate is fs/M ₁i, Q data, then undertaken making second level filtering and M by the 2nd CIC filtering extraction circuit ₂doubly extract, obtaining data transfer rate is f _s/ (M ₁× M ₂) I, Q data, export next stage HB filtering extraction circuit to; The data exported after two-stage CIC extracts can obtain higher extraction yield, more contribute to realizing extremely narrow process bandwidth; And when needing to realize extremely wide process bandwidth, by arranging by-pass switch, the arrival next stage module of the data lossless after mixing can be made.

HB filtering extraction circuit recited above, be the module of a multi-stage cascade, internal data handling process is shown in Fig. 5, and HB filtering extraction circuit has following character:

H(e ^jω)＝1-H(e ^j(π-ω))

H(e ^jπ/2)＝0.5

$h\left(n\right)=\left\{\begin{array}{cc}1,& n=0\\ 0,& n=\±2,\±4,\±6,...\end{array}\right.$

HB multi-stage cascade filtering extraction circuit can flexible configuration cascade progression N, is suitable for realizing M ₃=2 ⁿextraction doubly, cascade progression N is generally 1 ~ 3; Through the process of HB filtering extraction circuit, the data transfer rate of I, Q two paths of signals of output reduces further, after signal input HB filtering extraction circuit, compared with initial samples rate, has dropped to f _s/ (M ₁× M ₂× M ₃).

The same with CIC filtering extraction circuit, HB filtering extraction circuit is configured with by-pass switch too, can arrange flexibly according to application demand, when arrange bypass is carried out to HB filtering extraction circuit time, the data being input to HB filtering extraction circuit can nondestructively export next stage module to.

FIR filtering extraction circuit recited above, Main Function carries out shaping filter to whole channel, and interior data handling process is shown in Fig. 6, and the frequency response of FIR filtering extraction circuit is

$H\left(e^{\mathrm{j\ω}}\right)=\underset{k=0}{\overset{N-1}{\mathrm{\Σ}}}h\left(k\right)e^{-\mathrm{j\ωk}}$

The data of FIR filtering extraction circuit to input carry out shaping filter and M ₄extraction doubly, whether different with HB filtering extraction circuit from CIC filtering extraction circuit, FIR filtering extraction circuit does not establish by-pass switch, but can arrange and extract, and the data transfer rate exported after process is down to the f of initial samples rate _s/ (M ₁× M ₂× M ₃× M ₄).

Through the process of above CIC filtering extraction circuit, HB filtering extraction circuit and FIR filtering extraction circuit, the if sampling signal of input achieves and always extracts factor D=M ₁× M ₂× M ₃× M ₄extraction doubly, and final process bandwidth is obtained after FIR filtering extraction circuit.

In concrete control procedure, parameter and the logic control of modules realize by controller, along with fpga chip performance is more and more stronger, scale is increasing, average unit cost is more and more lower, and whole circuit also can utilize high speed FPGA to realize, by adjusting the controling parameters of modules, when input signal sample rate is 102.4 MSPS, signal transacting bandwidth can in the scope of 100Hz ~ 40MHz flexible configuration.

Claims (4)

1. a Digital Down Convert circuit, comprise data preprocessing module and frequency mixing module, described data preprocessing module is for realizing the collection of digital medium-frequency signal, described frequency mixing module comprises digital controlled oscillator, this digital controlled oscillator exports the mutually orthogonal local oscillation signal of two-way and realizes Frequency mixing processing with described intermediate-freuqncy signal, form the output of I road at the output of this frequency mixing module to export with Q road, it is characterized in that: the I road output of described frequency mixing module and Q road output are connected with a CIC filtering extraction circuit respectively in turn, 2nd CIC filtering extraction circuit, HB filtering extraction circuit and FIR filtering extraction circuit, described digital controlled oscillator, one CIC filtering extraction circuit, 2nd CIC filtering extraction circuit, HB filtering extraction circuit and FIR filtering extraction circuit are all connected with controller, this controller is for realizing parameter and the logic control of modules, at a described CIC filtering extraction circuit, 2nd CIC filtering extraction circuit and HB filtering extraction circuit are also connected with bypass selector switch, when a certain bypass selector switch is connected, the extraction yield of this that stage circuit corresponding to bypass selector switch is 1.

2. a kind of Digital Down Convert circuit according to claim 1, it is characterized in that: described data preprocessing module comprises parallel/serial modular converter, FIFO buffer module and Logic control module, for adapting to the output of different A/D converter, realize the sampling of digital medium-frequency signal.

3. a kind of Digital Down Convert circuit according to claim 1, is characterized in that: the 5 grades of cascades of a described CIC filtering extraction circuit sampling, the 6 grades of cascades of described 2nd CIC filtering extraction circuit sampling.

4. a kind of Digital Down Convert circuit according to claim 1, is characterized in that: the cascade progression scope of described HB filtering extraction circuit is 1 ~ 3.