CN107566071B - A kind of decoding method of IRIG-B direct current code coding and decoding device - Google Patents
A kind of decoding method of IRIG-B direct current code coding and decoding device Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
- H04J3/0605—Special codes used as synchronising signal
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
- H04J3/0614—Systems characterised by the synchronising information used the synchronising signal being characterised by the amplitude, duration or polarity
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
- H04J3/0617—Systems characterised by the synchronising information used the synchronising signal being characterised by the frequency or phase
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
- H04L7/0012—Synchronisation information channels, e.g. clock distribution lines by comparing receiver clock with transmitter clock
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Abstract
The invention belongs to the B code time service field of sync identification, in particular to a kind of decoding method of IRIG-B direct current code coding and decoding device.The present invention includes time receiving module, IRIG-B code output module, IRIG-B code receiving module, time output module, coding/decoding module and constant-temperature crystal oscillator, the signal input part of the coding/decoding module is received respectively from time receiving module, constant-temperature crystal oscillator, the TOD time of IRIG-B code receiving module and pulse per second (PPS), synchronizing frequency, IRIG-B direct current code, and signal output end output IRIG-B direct current code, TOD time and the pulse per second (PPS) of coding/decoding module are respectively to IRIG-B code output module, the signal input part of time output module.The present invention not only realizes the coding of IRIG-B direct current code, modulation carries out in ARM microprocessor system MSS, FPGA modulation unit parallel respectively, demodulation, decoding carry out in FPGA demodulating unit, ARM microprocessor system MSS parallel respectively, and the present invention is also equipped with the advantage that design is simple, time service precision is high, system is reliable and stable.
Description
It is " 2016.01.28 " that the application, which is the applying date, and application No. is " 201610069062.7 ", invention and created name is
The divisional application of " a kind of IRIG-B direct current code coding and decoding device and its decoding method ".
Technical field
The invention belongs to the B code time service field of sync identification, in particular to a kind of IRIG-B direct current code coding and decoding device
Decoding method.
Background technique
IRIG-B code is a kind of serial time format code, is proposed earliest by instrument group (IRIG) between U.S. target range, and by
It is widely used in time synchronization Transmission system.IRIG-B code has the general world, nuclear interface standardizing, is suitable for transmission etc. at a distance
Feature, in China, the test equipment in the fields such as Industry Control, communication, meteorology, space flight, power system measuring and protection is all made of
Time synchronizing standard of the IRIG-B international time standard as timing equipment, and formulated corresponding national military standard.
DC code is IRIG-B direct current code, and the frame period of DC code is 1 second, is made of 100 symbols, each code element 10ms, code
First width is divided into tri- kinds of 8ms, 5ms and 2ms, respectively represents symbol " P ", " 1 ", " 0 ".For the ease of transmitting and extracting in B code
Information has a position identification marking in every 10 symbols, be referred to as P1, P2 ..., P9, P0, frame reference mark is by position
Distinguishing mark P0 and adjacent reference symbol Pr composition, the forward position of Pr is quasi- moment second of every frame, that is, from the quasi- second
From moment, by the second, point, when, the temporal informations such as day encoded, ultimately form DC code.
Mostly using FPGA as core controller, consumed resource is big, synchronous for domestic IRIG-B direct current code encoding and decoding at present
Precision is low, working efficiency and stability are poor.Therefore, the more efficient coding and decoding device of one kind is needed to provide effective encoding and decoding hair
Method.
Summary of the invention
The present invention in order to overcome the above-mentioned deficiencies of the prior art, provides a kind of IRIG-B direct current code coding and decoding device, this
Invention not only realizes the coding of IRIG-B direct current code, modulates respectively in ARM microprocessor system MSS, FPGA modulation unit
Parallel to carry out, demodulation, decoding carry out in FPGA demodulating unit, ARM microprocessor system MSS parallel respectively, and the present invention
It is also equipped with the feature that time service precision is high, system is reliable and stable.
To achieve the above object, present invention employs following technical measures:
A kind of IRIG-B direct current code coding and decoding device, including time receiving module, IRIG-B code output module, IRIG-B code
The signal input part of receiving module, time output module, coding/decoding module and constant-temperature crystal oscillator, the coding/decoding module receives
Respectively from time receiving module, constant-temperature crystal oscillator, the TOD time of IRIG-B code receiving module and pulse per second (PPS), synchronizing frequency,
IRIG-B direct current code, the signal output end of coding/decoding module export IRIG-B direct current code, TOD time and pulse per second (PPS) respectively extremely
The signal input part of IRIG-B code output module, time output module.
Preferably, the coding/decoding module includes system on chip controller, when the system on chip controller is internally integrated
Clock generation module, FPGA modulation unit, FPGA demodulating unit, ARM microprocessor system MSS；
The clock generation module is received respectively from time receiving module, the pulse per second (PPS) of constant-temperature crystal oscillator, synchronizing frequency, institute
State signal output end connection FPGA modulation unit, the FPGA demodulating unit, ARM microprocessor system MSS of clock generation module
Signal input part, the input terminal of the FPGA modulation unit input pulse per second (PPS), and the ARM microprocessor system MSS reception comes from
The TOD time of time receiving module, ARM microprocessor system MSS is for encoding the TOD time and by the TOD after coding
Time, which is sent into FPGA modulation unit, is modulated to obtain synchronous IRIG-B direct current code, the FPGA modulation unit output
IRIG-B direct current code to IRIG-B code output module signal input part；
The FPGA demodulating unit receives the IRIG-B direct current code from IRIG-B code receiving module, and FPGA demodulating unit is used
It is demodulated in IRIG-B direct current code, and decoded IRIG-B direct current code is sent into ARM microprocessor system MSS and is carried out
Decoding, obtains the synchronous TOD time and pulse per second (PPS), ARM microprocessor system MSS, the FPGA demodulating unit exports TOD respectively
Time, pulse per second (PPS) to time output module signal input part.
Preferably, the FPGA modulation unit includes code stream receiving module, the first RAM module for reading and writing, the 2nd RAM read-write mould
Block and the first Read-write Catrol module；The code stream receiving module receives the TOD after ARM microprocessor system MSS coding
The signal output end of time, the code stream receiving module connect the first Read-write Catrol module, the first RAM module for reading and writing, the 2nd RAM
The signal input part of module for reading and writing, the first Read-write Catrol module is for controlling the first RAM module for reading and writing and the 2nd RAM read-write
The read-write operation of module, the first RAM module for reading and writing, the 2nd RAM module for reading and writing output end be all connected with alternative selector
Signal input part, the signal output end of the alternative selector exports IRIG-B direct current code to IRIG-B code output module
Signal input part；
The FPGA demodulating unit includes symbol identification module, decoder module, the 3rd RAM module for reading and writing, the 4th RAM read-write
Module, the second Read-write Catrol module and code stream sending module；The symbol identification module, which receives, comes from IRIG-B code receiving module
IRIG-B direct current code, signal output end connection decoder module, the signal of the second Read-write Catrol module of symbol identification module be defeated
Entering end, the second Read-write Catrol module is used to control the read-write operation of the 3rd RAM module for reading and writing and the 4th RAM module for reading and writing,
The 3rd RAM module for reading and writing, the 4th RAM module for reading and writing output end be all connected with the signal input part of code stream sending module, institute
Code stream sending module is stated to be decoded for decoded IRIG-B direct current code to be sent into ARM microprocessor system MSS.
Further, Microsemi company, the system on chip controller chip model U.S. produces
The M2S025T chip of SmartFusion2 series.
The present invention goes back while providing a kind of decoding method of above-mentioned IRIG-B direct current code coding and decoding device, according to
The corresponding every 1ms of the IRIG-B direct current code is considered as 1bit by IRIG-B direct current code agreement, have pulsewidth be high level 1, otherwise for
Low level 0, then in IRIG-B direct current code three kinds of symbols " P ", " 1 " and " 0 " be expressed as 1111111100 with binary data respectively,
1111100000 and 1100000000, then a frame IRIG-B direct current code is the binary code stream that 100 symbols are 1000bit.
The coding method specific steps include:
S1, ARM microprocessor system MSS receive the TOD time from time receiving module, and when to the TOD received
Between resolved, obtain the second, point, when, day, the moon, year temporal information, and according to IRIG-B direct current code agreement, ARM microprocessor
The temporal information is converted into symbol " P ", the form of " 1 ", " 0 " by system MSS, and is enriched and obtained a frame IRIG- of 100 symbols
B code data are extended to the time code stream of 1000bit；The time code stream is stored in whole by the ARM microprocessor system MSS
In figurate number group；The pulse per second (PPS) of the ARM microprocessor system MSS response from the time receiving module is interrupted, the second arteries and veins
When punching is interrupted, the time code stream in the shaping array is synchronized and is sent to FPGA modulation unit by ARM microprocessor system MSS；
S2, the code stream receiving module receive the time code stream in the shaping array from ARM microprocessor system MSS,
And it is synchronously written in the first RAM module for reading and writing and the 2nd RAM module for reading and writing, the first RAM module for reading and writing and the 2nd RAM read-write
Module uses ping-pong operation, and the 2nd RAM of control is read while the first Read-write Catrol module controls the first RAM module for reading and writing write operation
Writing module read operation controls the read operation of RAM read through model, such circulate operation while controlling the 2nd RAM module for reading and writing write operation；
S3, the clock generation module response from the pulse per second (PPS) of the time receiving module and constant-temperature crystal oscillator when
Clock, when clock generation module generates reading of the homologous clock as the first RAM module for reading and writing and the 2nd RAM module for reading and writing
Clock, the first RAM module for reading and writing and the 2nd RAM module for reading and writing export 1000bit, obtain in turn by data in EMS memory with 1bit word length
To the DC waveform of the IRIG-B direct current code synchronous with the pulse per second (PPS).
The coding/decoding method specific steps include:
S1, the symbol identification module receive the IRIG-B direct current code from IRIG-B code receiving module, according to IRIG-B
Direct current code agreement corresponds to symbol " P ", " 1 " and " 0 " in automatic identification IRIG-B direct current code, and uses 10bit binary element respectively
It is expressed as 1111111100,1111100000 and 1100000000；Using the clock homologous with the local of symbol identification module come
The rising edge and failing edge of IRIG-B direct current code are captured, is generated and the homologous rising edge of local clock and failing edge clock；
According to rising edge, the binary element generated in step S1, decoder module is known automatically for S2, the decoder module
The frame reference mark of other IRIG-B direct current code, the frame head of IRIG-B direct current code is found by the frame reference mark, then when described
When rising edge arrives, binary element is exported, the binary data of complete frame IRIG-B direct current code is obtained, works as decoding
When module identifies the frame reference mark, started counting with the rising edge of the IRIG-B direct current code of input, when meter completely 99, under
The rising edge of one adjacent IRIG-B direct current code be subject to moment second mark, decoder module is by frame reference pulse and quasi- second Shi Kebiao
Will is sent into the port ARM microprocessor system MSS, and pulse per second (PPS) is sent to the signal input part of time output module；
S3, the 3rd RAM module for reading and writing and the 4th RAM module for reading and writing use ping-pong operation, the second Read-write Catrol module
The 4th RAM module for reading and writing read operation is controlled while controlling the 3rd RAM module for reading and writing write operation, controls the 4th RAM module for reading and writing
The 3rd RAM module for reading and writing read operation, such circulate operation, the second Read-write Catrol module control stream hair are controlled while write operation
Send module that the binary data in the 3rd RAM module for reading and writing or the 4th RAM module for reading and writing memory is sent to ARM microprocessor system
It unites in the bus of MSS；
When S4, the ARM microprocessor system MSS response are interrupted from the frame reference pulse, ARM microprocessor system
The synchronous binary data read in bus of MSS, and be decoded, according to IRIG-B direct current code agreement, ARM microprocessor system
MSS extract in the binary data second, point, when, day, the moon, year temporal information and be converted into TOD time of ASCII fromat；
When the pulse per second (PPS) of the MSS response from FPGA demodulating unit is interrupted, the ARM microprocessor system MSS is synchronous by the TOD time
It is sent to the signal input part of output module.
The beneficial effects of the present invention are:
1), the present invention includes time receiving module, IRIG-B code output module, IRIG-B code receiving module, time output
Module, coding/decoding module and constant-temperature crystal oscillator, the signal input part of the coding/decoding module, which is received, receives mould respectively from the time
Block, constant-temperature crystal oscillator, the TOD time of IRIG-B code receiving module and pulse per second (PPS), synchronizing frequency, IRIG-B direct current code, encoding and decoding mould
Signal output end output IRIG-B direct current code, TOD time and the pulse per second (PPS) of block are exported to IRIG-B code output module, time respectively
The signal input part of module.The present invention not only realizes the coding of IRIG-B direct current code, modulation respectively in ARM microprocessor system
Carried out parallel in MSS, FPGA modulation unit, demodulate, decode respectively in FPGA demodulating unit, ARM microprocessor system MSS simultaneously
Row carries out, and the present invention is also equipped with the advantage that design is simple, time service precision is high, system is reliable and stable.
2), the SmartFusion2 system of Microsemi company, system on chip controller chip model U.S. production
The M2S025T chip of column, the system on chip controller are internally integrated clock generation module, FPGA modulation unit, FPGA demodulation
Unit, ARM microprocessor system MSS；Has the high advantage of processing speed fast, low-power consumption, safety and reliability.
3), using the coding and decoding device and decoding method in the present invention, the precision for realizing coding and decoding is high, and is
The fast advantage of the speed of service of uniting.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of IRIG-B direct current code coding and decoding device of the present invention；
Fig. 2 is IRIG-B direct current code symbol diagram；
Fig. 3 is DC signal bit stream waveform diagram；
Fig. 4 is the RTL view of coding/decoding module of the invention；
Fig. 5 is the RTL view of FPGA modulation unit of the invention；
Fig. 6 is the RTL view of FPGA demodulating unit of the invention.
The meaning of label symbol is as follows in figure:
10-time 20-IRIG-B of receiving module code output modules
30-IRIG-B code 40-time of receiving module output modules
50-60-constant-temperature crystal oscillators of coding/decoding module
Clock-clock generation module Reg_wrp-code stream receiving module
The first RAM module for reading and writing RAM module for reading and writing of TPSRAM_0-the 2nd of TPSRAM_1-
Out_TPCtrl-the first Read-write Catrol module EleDetect-symbol identification module
Decode-RAM the module for reading and writing of decoder module TPSRAM_3-the 3rd
The 4th RAM module for reading and writing Read-write Catrol module of RAMCtrl-second of TPSRAM_4-
RAMapb-code stream sending module
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
As shown in Figure 1, a kind of IRIG-B direct current code coding and decoding device, including the output of time receiving module 10, IRIG-B code
Module 20, IRIG-B code receiving module 30, time output module 40, coding/decoding module 50 and constant-temperature crystal oscillator 60, the volume solution
The signal input part of code module 50 is received respectively from time receiving module 10, constant-temperature crystal oscillator 60, IRIG-B code receiving module 30
The TOD time and pulse per second (PPS), synchronizing frequency, IRIG-B direct current code, coding/decoding module 50 signal output end output IRIG-B it is straight
Code, TOD time and pulse per second (PPS) are flowed respectively to IRIG-B code output module 20, the signal input part of time output module 40.This hair
The bright coding for not only realizing IRIG-B direct current code, modulation respectively in ARM microprocessor system MSS, FPGA modulation unit simultaneously
Row carries out, and demodulation, decoding carry out in FPGA demodulating unit, ARM microprocessor system MSS parallel respectively, and the present invention is also
Has the advantage that design is simple, time service precision is high, system is reliable and stable.
As shown in figure 4, the coding/decoding module 50 includes system on chip controller, collection inside the system on chip controller
At clock generation module Clock, FPGA modulation unit, FPGA demodulating unit, ARM microprocessor system MSS；
The clock generation module Clock receives the pulse per second (PPS), same respectively from time receiving module 10, constant-temperature crystal oscillator 60
The signal output end of synchronizing frequency, the clock generation module Clock connects FPGA modulation unit, FPGA demodulating unit, the micro- place ARM
The signal input part of device system MSS is managed, the input terminal of the FPGA modulation unit inputs pulse per second (PPS), the ARM microprocessor system
Unite MSS receive the TOD time from time receiving module 10, ARM microprocessor system MSS for the TOD time is encoded,
And the TOD time after coding is sent into FPGA modulation unit and is modulated to obtain synchronous IRIG-B direct current code, the FPGA
Modulation unit exports the signal input part of IRIG-B direct current code to IRIG-B code output module 20；
The FPGA demodulating unit receives the IRIG-B direct current code from IRIG-B code receiving module 30, FPGA demodulating unit
For being demodulated to IRIG-B direct current code, and by decoded IRIG-B direct current code be sent into ARM microprocessor system MSS in into
Row decoding, obtains the synchronous TOD time and pulse per second (PPS), ARM microprocessor system MSS, the FPGA demodulating unit exports respectively
The TOD time, pulse per second (PPS) to time output module 40 signal input part.
As shown in figure 5, the FPGA modulation unit includes code stream receiving module Reg_wrp, the first RAM module for reading and writing
TPSRAM_1, the 2nd RAM module for reading and writing TPSRAM_0 and the first Read-write Catrol module Out_TPCtrl；The code stream receives
Module Reg_wrp receives the TOD time after ARM microprocessor system MSS coding, the code stream receiving module Reg_wrp
Signal output end connect the first Read-write Catrol module Out_TPCtrl, the first RAM module for reading and writing TPSRAM_1, the 2nd RAM read
The signal input part of writing module TPSRAM_0, the first Read-write Catrol module Out_TPCtrl is for controlling the first RAM read-write
The read-write operation of module TPSRAM_1 and the 2nd RAM module for reading and writing TPSRAM_0, the first RAM module for reading and writing TPSRAM_1,
The output end of 2nd RAM module for reading and writing TPSRAM_0 is all connected with the signal input part of alternative selector MX2, the letter of the MX2
Number output end exports the signal input part of IRIG-B direct current code to IRIG-B code output module 20.
As shown in fig. 6, the FPGA demodulating unit includes symbol identification module EleDetect, decoder module Decode,
Three RAM module for reading and writing TPSRAM_3, the 4th RAM module for reading and writing TPSRAM_4, the second Read-write Catrol module RAMCtrl and code stream hair
Send module RAMapb；The symbol identification module EleDetect receives the IRIG-B direct current from IRIG-B code receiving module 30
The signal output end of code, symbol identification module EleDetect connects decoder module Decode, the second Read-write Catrol module
The signal input part of RAMCtrl, the second Read-write Catrol module RAMCtrl is for controlling the 3rd RAM module for reading and writing TPSRAM_
3 and the 4th RAM module for reading and writing TPSRAM_4 read-write operation, the 3rd RAM module for reading and writing TPSRAM_3, the 4th RAM read-write
The output end of module TPSRAM_4 is all connected with the signal input part of code stream sending module RAMapb, the code stream sending module
RAMapb is used to for decoded IRIG-B direct current code being sent into ARM microprocessor system MSS and be decoded.
The SmartFusion2 series of Microsemi company, system on chip controller chip model U.S. production
M2S025T chip；Has the high advantage of processing speed fast, low-power consumption, safety and reliability.
As shown in Fig. 2, the frame period of IRIG-B direct current code is 1 second, it is made of 100 symbols, each code element 10ms, symbol
Width is divided into tri- kinds of 8ms, 5ms and 2ms, respectively represents symbol " P ", " 1 ", " 0 ".For the ease of transmitting and extracting the letter in B code
Breath has a position identification marking in every 10 symbols, be referred to as P1, P2 ..., P9, P0, frame reference mark is known by position
Not Biao Zhi P0 and adjacent reference symbol Pr composition, the forward position of Pr is quasi- moment second of every frame, that is, when from the quasi- second
Carve, by the second, point, when, the temporal informations such as day encoded, ultimately form DC code.
As shown in figure 3, a kind of decoding method of IRIG-B direct current code coding and decoding device, core is straight according to IRIG-B
Code agreement is flowed, the corresponding every 1ms of the IRIG-B direct current code is considered as 1bit, otherwise it is low level 0 that having pulsewidth, which is high level 1,
Then in IRIG-B direct current code three kinds of symbols " P ", " 1 " and " 0 " be expressed as 1111111100 with binary data respectively,
1111100000 and 1100000000, then a frame IRIG-B direct current code is the binary code stream that 100 symbols are 1000bit.
Wherein coding method specific steps include:
S1, the ARM microprocessor system MSS receive the TOD from time receiving module 10 by TOD_Input serial ports
Time, and the TOD time received is resolved, obtain the second, point, when, day, the moon, year temporal information, and according to IRIG-B
Direct current code agreement, the temporal information is converted into symbol " P ", the form of " 1 ", " 0 " by ARM microprocessor system MSS, and is enriched
A frame IRIG-B code data of 100 symbols are obtained, that is, are extended to the time code stream of 1000bit；The ARM microprocessor system
Time code stream deposit length is in shaping array that 16bit size is 64 by MSS；The ARM microprocessor system MSS is rung
It should be interrupted from the pulse per second (PPS) PPS_in of the time receiving module 10, when the pulse per second (PPS) PPS_in is interrupted, ARM microprocessor
Time code stream in the shaping array is synchronized and is sent to FPGA modulation unit by system MSS；
S2, the code stream receiving module Reg_wrp receive the shaping array from ARM microprocessor system MSS in when
Between code stream, and be synchronously written in the first RAM module for reading and writing TPSRAM_1 and the 2nd RAM module for reading and writing TPSRAM_0, described first
RAM module for reading and writing TPSRAM_1 and the 2nd RAM module for reading and writing TPSRAM_0 uses ping-pong operation, the first Read-write Catrol module Out_
The 2nd RAM module for reading and writing TPSRAM_0 of control reads behaviour while TPCtrl controls the first RAM module for reading and writing TPSRAM_1 write operation
Make, controls the TPSRAM_1 read operation of RAM read through model while controlling the 2nd RAM module for reading and writing TPSRAM_0 write operation, so follow
Ring operation；
The response of S3, the clock generation module Clock from the pulse per second (PPS) PPS_in of the time receiving module 10 and
The 10MHz clock Clk10M_in of constant-temperature crystal oscillator 60, clock generation module Clock generate homologous 1KHz clock Clk1KHz_out
As the reading clock of the first RAM module for reading and writing TPSRAM_1 and the 2nd RAM module for reading and writing TPSRAM_0, the first RAM read-write
Module TPSRAM_1 and the 2nd RAM module for reading and writing TPSRAM_0 exports 1000bit in turn by data in EMS memory with 1bit word length,
Obtain the DC waveform of the IRIG-B direct current code synchronous with the pulse per second (PPS) PPS_in.
The coding/decoding method specific steps include:
S1, the symbol identification module EleDetect receive the IRIG-B direct current code from IRIG-B code receiving module 30,
According to IRIG-B direct current code agreement, symbol " P ", " 1 " and " 0 " is corresponded in automatic identification IRIG-B direct current code, and use 10bit respectively
Binary element is expressed as 1111111100,1111100000 and 1100000000, i.e. Element_Out [9:0]；Using with code
The homologous 10KHz clock Clk_10K of the local clock of first identification module EleDetect captures the rising edge of IRIG-B direct current code
And failing edge, it generates and local clock homologous rising edge Pos_Out and failing edge clock Neg_Out；
S2, the decoder module Decode are according to rising edge Pos_Out, the binary element generated in step S1
Element_In [9:0], the frame reference mark pp_flag of decoder module Decode automatic identification IRIG-B direct current code, by described
Frame reference mark pp_flag finds the frame head of IRIG-B direct current code, defeated then when the rising edge Pos_Out arrives
Binary element Element_In [9:0] out obtains the binary data of complete frame IRIG-B direct current code, works as decoder module
When Decode identifies the frame reference mark pp_flag, is started counting with the rising edge of the IRIG-B direct current code of input, work as meter
When full 99, the rising edge of next adjacent IRIG-B direct current code be subject to moment second indicate PPS_flag, by frame reference pulse PP_
Out and mark PPS_Out of quasi- moment second is sent into the port ARM microprocessor system MSS, and pulse per second (PPS) is sent to time output mould
The signal input part of block 40；
S3, the 3rd RAM module for reading and writing TPSRAM_3 and the 4th RAM module for reading and writing TPSRAM_4 use ping-pong operation,
The 4th RAM of control read-write while second Read-write Catrol module RAMCtrl controls the 3rd RAM module for reading and writing TPSRAM_3 write operation
Module TPSRAM_4 read operation controls the 3rd RAM module for reading and writing while controlling the 4th RAM module for reading and writing TPSRAM_4 write operation
TPSRAM_3 read operation, such circulate operation, the second Read-write Catrol module RAMCtrl control stream sending module RAMapb is by
Binary data in three RAM module for reading and writing TPSRAM_3 or the 4th RAM module for reading and writing TPSRAM_4 memory is sent to the micro- place ARM
In the bus for managing device system MSS；
When S4, shown ARM microprocessor system MSS response are interrupted from the frame reference pulse PP_Out, ARM micro process
The synchronous binary data read in bus of device system MSS, and be decoded, according to IRIG-B direct current code agreement, ARM micro process
Device system MSS extract in the binary data second, point, when, day, the moon, year temporal information and be converted into ASCII fromat
The TOD time；It is described when pulse per second (PPS) PPS_Out of the ARM microprocessor system MSS response from FPGA demodulating unit is interrupted
The synchronous signal input part that the TOD time is sent to output module 40 through TOD_Output serial ports of ARM microprocessor system MSS.
Claims (4)
1. a kind of decoding method of IRIG-B direct current code coding and decoding device, it is characterised in that: the IRIG-B direct current code compiles solution
Code device includes time receiving module (10), IRIG-B code output module (20), IRIG-B code receiving module (30), time output
Module (40), coding/decoding module (50) and constant-temperature crystal oscillator (60), the signal input part of the coding/decoding module (50), which receives, to be divided
It Lai Zi not time receiving module (10), constant-temperature crystal oscillator (60), the TOD time of IRIG-B code receiving module (30) and pulse per second (PPS), same
Synchronizing frequency, IRIG-B direct current code, signal output end output IRIG-B direct current code, TOD time and the second arteries and veins of coding/decoding module (50)
Punching is respectively to IRIG-B code output module (20), the signal input part of time output module (40)；
The coding/decoding module (50) includes system on chip controller, and the system on chip controller is internally integrated clock and generates mould
Block Clock, FPGA modulation unit, FPGA demodulating unit, ARM microprocessor system MSS；
The clock generation module Clock receives the pulse per second (PPS), same respectively from time receiving module (10), constant-temperature crystal oscillator (60)
The signal output end of synchronizing frequency, the clock generation module Clock connects FPGA modulation unit, FPGA demodulating unit, the micro- place ARM
The signal input part of device system MSS is managed, the input terminal of the FPGA modulation unit inputs pulse per second (PPS), the ARM microprocessor system
The MSS that unites receives the TOD time for coming from time receiving module (10), and ARM microprocessor system MSS is for compiling the TOD time
The TOD time after coding is simultaneously sent into FPGA modulation unit and is modulated to obtain synchronous IRIG-B direct current code by code, described
FPGA modulation unit exports the signal input part of IRIG-B direct current code to IRIG-B code output module (20)；
The FPGA demodulating unit receives the IRIG-B direct current code for coming from IRIG-B code receiving module (30), and FPGA demodulating unit is used
It is demodulated in IRIG-B direct current code, and decoded IRIG-B direct current code is sent into ARM microprocessor system MSS and is carried out
Decoding, obtains the synchronous TOD time and pulse per second (PPS), ARM microprocessor system MSS, the FPGA demodulating unit exports TOD respectively
Time, pulse per second (PPS) to time output module (40) signal input part；
The FPGA modulation unit includes code stream receiving module Reg_wrp, the first RAM module for reading and writing TPSRAM_1, the 2nd RAM reading
Writing module TPSRAM_0 and the first Read-write Catrol module Out_TPCtrl；The code stream receiving module Reg_wrp reception comes from
TOD time after ARM microprocessor system MSS coding, the signal output end connection first of the code stream receiving module Reg_wrp
The signal of Read-write Catrol module Out_TPCtrl, the first RAM module for reading and writing TPSRAM_1, the 2nd RAM module for reading and writing TPSRAM_0
Input terminal, the first Read-write Catrol module Out_TPCtrl is for controlling the first RAM module for reading and writing TPSRAM_1 and the 2nd RAM
The read-write operation of module for reading and writing TPSRAM_0, the first RAM module for reading and writing TPSRAM_1, the 2nd RAM module for reading and writing TPSRAM_
0 output end is all connected with the signal input part of alternative selector MX2, and the signal output end of the alternative selector MX2 is defeated
Out IRIG-B direct current code to IRIG-B code output module (20) signal input part；
The FPGA demodulating unit includes symbol identification module EleDetect, decoder module Decode, the 3rd RAM module for reading and writing
TPSRAM_3, the 4th RAM module for reading and writing TPSRAM_4, the second Read-write Catrol module RAMCtrl and code stream sending module RAMapb；
The symbol identification module EleDetect receives the IRIG-B direct current code for coming from IRIG-B code receiving module (30), symbol identification
The signal input of the signal output end connection decoder module Decode, the second Read-write Catrol module RAMCtrl of module EleDetect
End, the second Read-write Catrol module RAMCtrl read and write mould for controlling the 3rd RAM module for reading and writing TPSRAM_3 and the 4th RAM
The read-write operation of block TPSRAM_4, the 3rd RAM module for reading and writing TPSRAM_3, the 4th RAM module for reading and writing TPSRAM_4 it is defeated
Outlet is all connected with the signal input part of code stream sending module RAMapb, and the code stream sending module RAMapb is used for will be decoded
IRIG-B direct current code is sent into ARM microprocessor system MSS and is decoded；
The decoding method includes being considered as the corresponding every 1ms of the IRIG-B direct current code according to IRIG-B direct current code agreement
1bit, otherwise it is low level 0, then three kinds of symbols " P ", " 1 " and " 0 " are used respectively in IRIG-B direct current code that having pulsewidth, which is high level 1,
Binary data is expressed as 1111111100,1111100000 and 1100000000, then a frame IRIG-B direct current code is 100 symbols
The as binary code stream of 1000bit；
The signal output end of the decoder module Decode connects the second Read-write Catrol module RAMCtrl, the 3rd RAM module for reading and writing
The signal input part of TPSRAM_3 and the 4th RAM module for reading and writing TPSRAM_4.
2. a kind of decoding method of IRIG-B direct current code coding and decoding device as described in claim 1, it is characterised in that described
Coding method specific steps include:
S1, ARM microprocessor system MSS receive the TOD time for coming from time receiving module (10), and when to the TOD received
Between resolved, obtain the second, point, when, day, the moon, year temporal information, and according to IRIG-B direct current code agreement, ARM microprocessor
The temporal information is converted into symbol " P ", the form of " 1 ", " 0 " by system MSS, and is enriched and obtained a frame IRIG- of 100 symbols
B code data are extended to the time code stream of 1000bit；The time code stream is stored in whole by the ARM microprocessor system MSS
In figurate number group；The ARM microprocessor system MSS response is interrupted from the pulse per second (PPS) of the time receiving module (10), described
When pulse per second (PPS) is interrupted, ARM microprocessor system MSS, which synchronizes the time code stream in the shaping array, is sent to FPGA modulation list
Member；
S2, the code stream receiving module Reg_wrp receive the timing code in the shaping array from ARM microprocessor system MSS
Stream, and be synchronously written in the first RAM module for reading and writing TPSRAM_1 and the 2nd RAM module for reading and writing TPSRAM_0, the first RAM is read
Writing module TPSRAM_1 and the 2nd RAM module for reading and writing TPSRAM_0 uses ping-pong operation, the first Read-write Catrol module Out_
The 2nd RAM module for reading and writing TPSRAM_0 of control reads behaviour while TPCtrl controls the first RAM module for reading and writing TPSRAM_1 write operation
Make, controls the TPSRAM_1 read operation of RAM read through model while controlling the 2nd RAM module for reading and writing TPSRAM_0 write operation, so follow
Ring operation；
The response of S3, the clock generation module Clock are from the pulse per second (PPS) of the time receiving module (10) and constant-temperature crystal oscillator
(60) clock, clock generation module Clock generate homologous clock as the first RAM module for reading and writing TPSRAM_1 and
The reading clock of two RAM module for reading and writing TPSRAM_0, the first RAM module for reading and writing TPSRAM_1 and the 2nd RAM module for reading and writing TPSRAM_
0, in turn by data in EMS memory with 1bit word length, exports 1000bit, obtains the IRIG-B direct current code synchronous with the pulse per second (PPS)
DC waveform.
3. a kind of decoding method of IRIG-B direct current code coding and decoding device as described in claim 1, it is characterised in that described
Coding/decoding method specific steps include:
S1, the symbol identification module EleDetect receive the IRIG-B direct current code for coming from IRIG-B code receiving module (30), root
According to IRIG-B direct current code agreement, symbol " P ", " 1 " and " 0 " is corresponded in automatic identification IRIG-B direct current code, and uses 10bit bis- respectively
System symbol is expressed as 1111111100,1111100000 and 1100000000；Using with symbol identification module EleDetect's
Local homologous clock captures the rising edge and failing edge of IRIG-B direct current code, when generating the rising edge homologous with local clock
Clock and failing edge clock；
S2, the decoder module Decode are according to rising edge, the binary element generated in step S1, decoder module
The frame reference mark of Decode automatic identification IRIG-B direct current code, the frame of IRIG-B direct current code is found by the frame reference mark
Head exports binary element then when the rising edge arrives, obtain the two of complete frame IRIG-B direct current code into
Data processed are opened when decoder module Decode identifies the frame reference mark with the rising edge of the IRIG-B direct current code of input
Begin to count, when meter it is full 99 when, the rising edge of next adjacent IRIG-B direct current code be subject to moment second mark, decoder module
Frame reference pulse and mark of quasi- moment second are sent into the port ARM microprocessor system MSS by Decode, and when pulse per second (PPS) is sent to
Between output module (40) signal input part；
S3, the 3rd RAM module for reading and writing TPSRAM_3 and the 4th RAM module for reading and writing TPSRAM_4 use ping-pong operation, second
Read-write Catrol module RAMCtrl controls the 4th RAM module for reading and writing while controlling the 3rd RAM module for reading and writing TPSRAM_3 write operation
TPSRAM_4 read operation controls the 3rd RAM module for reading and writing while controlling the 4th RAM module for reading and writing TPSRAM_4 write operation
TPSRAM_3 read operation, such circulate operation, the second Read-write Catrol module RAMCtrl control stream sending module RAMapb is by
Binary data in three RAM module for reading and writing TPSRAM_3 or the 4th RAM module for reading and writing TPSRAM_4 memory is sent to the micro- place ARM
In the bus for managing device system MSS；
When S4, the ARM microprocessor system MSS response are interrupted from the frame reference pulse, ARM microprocessor system MSS
The synchronous binary data read in bus, and be decoded, according to IRIG-B direct current code agreement, ARM microprocessor system MSS
Extract in the binary data second, point, when, day, the moon, year temporal information and be converted into TOD time of ASCII fromat；Institute
When stating pulse per second (PPS) interruption of the MSS response from FPGA demodulating unit, the TOD time is sent out in the ARM microprocessor system MSS synchronization
It send to the signal input part of output module (40).
4. a kind of decoding method of IRIG-B direct current code coding and decoding device as described in claim 1, it is characterised in that: described
The M2S025T chip of the SmartFusion2 series of system on chip controller chip model Microsemi company, U.S. production.
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| CN107037722B (en) * | 2017-04-25 | 2019-12-13 | 华北计算技术研究所（中国电子科技集团公司第十五研究所） | time system terminal |
| CN107831696B (en) * | 2017-11-15 | 2020-07-28 | 许昌智能继电器股份有限公司 | IRIG-B direct current code decoding method |
| CN109687928A (en) * | 2018-11-22 | 2019-04-26 | 南京熊猫电子股份有限公司 | A kind of IRIG-B type code (DC) time service realization system and method based on FPGA |
| CN110083049B (en) * | 2019-04-28 | 2021-02-19 | 哈尔滨工程大学 | Decoding and accurate time service method of navigation system |
| CN110944019A (en) * | 2019-12-30 | 2020-03-31 | 嘉兴泰传光电有限公司 | Different time synchronizing signal self-selection input device based on FPGA |
| CN114415780A (en) * | 2021-12-30 | 2022-04-29 | 研祥智慧物联科技有限公司 | IRIG-B code-based time synchronization method and device |
| CN114422071B (en) * | 2022-01-26 | 2024-03-15 | 成都金诺信高科技有限公司 | IRIG-B (DC) signal rapid synchronization system and synchronization method |
| CN115567144B (en) * | 2022-11-30 | 2023-04-04 | 中国船舶集团有限公司第七〇七研究所 | Demodulation method and system of reference time 1PPS in IRIG-B code |
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| JP2004254149A (en) * | 2003-02-21 | 2004-09-09 | Nippon Telegr & Teleph Corp <Ntt> | Data transmission control method and system |
| CN202818360U (en) * | 2012-09-17 | 2013-03-20 | 南京澳德思电气有限公司 | IRIG-B modem based on FPGA |
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| CN202998116U (en) * | 2012-07-04 | 2013-06-12 | 深圳市星龙科技有限公司 | Pulse-per-second and IRIG-B direct-current code clock synchronization circuit and equipment |
| CN103346804B (en) * | 2013-07-30 | 2016-12-28 | 哈尔滨工业大学 | IRIG-B code coding-decoding system based on FPGA and encoding and decoding method thereof |
| CN103997331B (en) * | 2014-06-11 | 2017-03-22 | 四川九洲电器集团有限责任公司 | High-precision DC code encoding method and system based on FPGA |
| CN205490576U (en) * | 2016-01-28 | 2016-08-17 | 安徽四创电子股份有限公司 | Decoding device is compiled to IRIG -B direct current sign indicating number |
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| JP2004254149A (en) * | 2003-02-21 | 2004-09-09 | Nippon Telegr & Teleph Corp <Ntt> | Data transmission control method and system |
| CN202818360U (en) * | 2012-09-17 | 2013-03-20 | 南京澳德思电气有限公司 | IRIG-B modem based on FPGA |
| CN104808481A (en) * | 2015-05-14 | 2015-07-29 | 昆山市工业技术研究院有限责任公司 | Beidou and GPS (Global Positioning System) dual-mode timing embedded time synchronization equipment and software design method |
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