CN205490576U - Decoding device is compiled to IRIG -B direct current sign indicating number - Google Patents
Decoding device is compiled to IRIG -B direct current sign indicating number Download PDFInfo
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- CN205490576U CN205490576U CN201620099682.0U CN201620099682U CN205490576U CN 205490576 U CN205490576 U CN 205490576U CN 201620099682 U CN201620099682 U CN 201620099682U CN 205490576 U CN205490576 U CN 205490576U
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Abstract
The utility model belongs to the B sign indicating number time service field of synchronous time service, in particular to IRIG decoding device is compiled to B direct current sign indicating number. The utility model discloses a time receiving module, IRIG B sign indicating number output module, IRIG B sign indicating number receiving module, time output module, volume decoder module and constant temperature crystal oscillator, does the signal input part who compiles decoder module receive and comes from time receiving module, constant temperature crystal oscillator, IRIG respectively B sign indicating number receiving module's TOD time and second pulse, synchronous frequency, IRIG B direct current sign indicating number, does the signal output part who compiles decoder module export IRIG be B direct current sign indicating number, TOD time and second pulse respectively to IRIG B sign indicating number output module, time output module's signal input part. The utility model discloses do you not only realize IRIG the code of B direct current sign indicating number, modulation walk abreast in ARM microprocessor system MSS, FPGA modulation unit respectively and go on, demodulation, parallel the going on in FPGA demodulation unit, ARM microprocessor system MSS respectively of decoding, moreover the utility model discloses possess still that the design is simple, the time service precision high, the reliable and stable advantage of system.
Description
Technical field
This utility model belongs to the B code time service field of sync identification, particularly to a kind of IRIG-B direct current
Code coding and decoding device.
Background technology
IRIG-B code is the time format code of a kind of serial, the earliest by instrument group (IRIG) between U.S. target range
Propose, and be widely used in time synchronized transmission system.IRIG-B code has Global Access use, interface mark
Standardization, be applicable to the features such as long-distance transmissions, in China, Industry Control, communication, meteorology, space flight,
The test equipment in the fields such as power system measuring and protection all use IRIG-B international time standard as time
The time synchronizing standard of system equipment, and formulated corresponding national military standard.
DC code is IRIG-B direct current code, and the frame period of DC code is 1 second, is made up of, often 100 code elements
Individual code element 10ms, symbol width is divided into 8ms, 5ms and 2ms tri-kinds, represent respectively code element " P ", " 1 ",
“0”.For the ease of the information in transmission and extraction B code, every 10 code elements there is a location recognition
Mark, is called P1, P2 ..., P9, P0, frame reference mark be by location recognition mark P0 and
Adjacent reference symbol Pr composition, the forward position of Pr is i.e. quasi-moment second of every frame, namely from this standard
Second moment rises, by the second, point, time, the temporal information such as sky encode, ultimately form DC code.
The most domestic IRIG-B direct current code encoding and decoding mostly with FPGA as core controller, resource consumption
Amount is big, synchronization accuracy is low, work efficiency and poor stability.Therefore, a kind of more efficient encoding and decoding are needed badly
Device provides effective encoding and decoding to send out method.
Utility model content
This utility model is in order to overcome above-mentioned the deficiencies in the prior art, it is provided that a kind of IRIG-B direct current code
Coding and decoding device, this utility model not only achieves the coding of IRIG-B direct current code, modulation respectively at ARM
Microprocessor system MSS, FPGA modulating unit are carried out parallel, demodulates, decode respectively in FPGA solution
Adjust in unit, ARM microprocessor system MSS and carry out parallel, and this utility model is also equipped with time service essence
Degree is high, the reliable feature of system stability.
For achieving the above object, this utility model have employed techniques below measure:
A kind of IRIG-B direct current code coding and decoding device, including time receiver module, IRIG-B code output mould
Block, IRIG-B code receiver module, time output module, coding/decoding module and constant-temperature crystal oscillator, described
The signal input part of coding/decoding module receives respectively from time receiver module, constant-temperature crystal oscillator, IRIG-B
The TOD time of code receiver module and pulse per second (PPS), synchronizing frequency, IRIG-B direct current code, coding/decoding module
Signal output part output IRIG-B direct current code, TOD time and pulse per second (PPS) are respectively to IRIG-B code output mould
Block, the signal input part of time output module.
This utility model can also be realized further by techniques below measure.
Preferably, described coding/decoding module includes SOC(system on a chip) controller, in described SOC(system on a chip) controller
Portion's integrated clock generation module, FPGA modulating unit, FPGA demodulating unit, ARM microprocessor system
MSS；
Described clock generation module receive respectively from time receiver module, the pulse per second (PPS) of constant-temperature crystal oscillator, with
Synchronizing frequency, the signal output part of described clock generation module connects FPGA modulating unit, FPGA demodulates single
Unit, the signal input part of ARM microprocessor system MSS, the input input of described FPGA modulating unit
Pulse per second (PPS), described ARM microprocessor system MSS receives the TOD time from time receiver module, institute
The TOD time after the outfan output coding of ARM microprocessor system MSS of stating is to FPGA modulating unit
Input, described FPGA modulating unit output IRIG-B direct current code to IRIG-B code output module
Signal input part；
Described FPGA demodulating unit receives the IRIG-B direct current code from IRIG-B code receiver module, FPGA
The outfan output IRIG-B direct current code of demodulating unit to the input of ARM microprocessor system MSS,
Described ARM microprocessor system MSS, FPGA demodulating unit export respectively the TOD time, pulse per second (PPS) to time
Between the signal input part of output module.
Preferably, described FPGA modulating unit include code stream receiver module, a RAM module for reading and writing,
2nd RAM module for reading and writing and the first Read-write Catrol module；Described code stream receiver module receives from ARM
The TOD time after microprocessor system MSS coding, the signal output part of described code stream receiver module connects
First Read-write Catrol module, a RAM module for reading and writing, the signal input part of the 2nd RAM module for reading and writing,
The signal output part of described first Read-write Catrol module connects a RAM module for reading and writing, the 2nd RAM read-write
The signal input part of module, a described RAM module for reading and writing, the 2nd RAM module for reading and writing outfan equal
Connect the signal input part of alternative selector, the signal output part output of described alternative selector
IRIG-B direct current code is to the signal input part of IRIG-B code output module；
Described FPGA demodulating unit include code element identification module, decoder module, the 3rd RAM module for reading and writing,
4th RAM module for reading and writing, the second Read-write Catrol module and code stream sending module；Described code element identification module
Receive the IRIG-B direct current code from IRIG-B code receiver module, the signal output part of code element identification module
Connect decoder module, the signal input part of the second Read-write Catrol module, described second Read-write Catrol module
Signal output part connects the 3rd RAM module for reading and writing, the signal input part of the 4th RAM module for reading and writing, described
3rd RAM module for reading and writing, the outfan of the 4th RAM module for reading and writing are all connected with the signal of code stream sending module
Input, it is micro-to ARM that the outfan of described code stream sending module exports decoded IRIG-B direct current code
The input of processor system MSS.
Further, described SOC(system on a chip) controller chip model is that Microsemi company of the U.S. produces
The M2S025T chip of SmartFusion2 series.
The beneficial effects of the utility model are:
1), this utility model includes that time receiver module, IRIG-B code output module, IRIG-B code connect
Receive module, time output module, coding/decoding module and constant-temperature crystal oscillator, the letter of described coding/decoding module
Number input receives respectively from time receiver module, constant-temperature crystal oscillator, the TOD of IRIG-B code receiver module
Time and pulse per second (PPS), synchronizing frequency, IRIG-B direct current code, the signal output part output of coding/decoding module
IRIG-B direct current code, TOD time and pulse per second (PPS) are respectively to IRIG-B code output module, time output mould
The signal input part of block.This utility model not only achieves the coding of IRIG-B direct current code, modulation respectively
ARM microprocessor system MSS, FPGA modulating unit are carried out parallel, demodulates, decode respectively at FPGA
Demodulating unit, ARM microprocessor system MSS are carried out parallel, and this utility model is also equipped with design
Simply, time service precision height, the reliable advantage of system stability.
Be worth it is emphasized that: this utility model is only protected by above-mentioned physical unit and connects each thing
Manage device or physical platform that the circuit between parts is constituted, without regard to software section therein.
2), described SOC(system on a chip) controller chip model is that Microsemi company of the U.S. produces
The M2S025T chip of SmartFusion2 series, described SOC(system on a chip) controller is internally integrated clock and produces
Module, FPGA modulating unit, FPGA demodulating unit, ARM microprocessor system MSS；Possesses process speed
Degree is fast, low-power consumption, advantage that safety and reliability is high.
3), the coding and decoding device in this utility model is used to achieve the precision height of coding and decoding, and
The advantage that system running speed is fast.
Accompanying drawing explanation
Fig. 1 is the structural representation of this utility model IRIG-B direct current code coding and decoding device；
Fig. 2 is IRIG-B direct current code symbol diagram；
Fig. 3 is DC signal bit stream oscillogram；
Fig. 4 is the RTL view of coding/decoding module of the present utility model；
Fig. 5 is the RTL view of FPGA modulating unit of the present utility model；
Fig. 6 is the RTL view of FPGA demodulating unit of the present utility model.
In figure, the implication of label symbol is as follows:
10 time receiver module 20 IRIG-B code output modules
30 IRIG-B code receiver module 40 time output modules
50 coding/decoding module 60 constant-temperature crystal oscillators
Clock clock generation module Reg_wrp code stream receiver module
TPSRAM_1 the oneth RAM module for reading and writing TPSRAM_0 the 2nd RAM module for reading and writing
Out_TPCtrl the first Read-write Catrol module EleDetect code element identification module
Decode decoder module TPSRAM_3 the 3rd RAM module for reading and writing
TPSRAM_4 the 4th RAM module for reading and writing RAMCtrl the second Read-write Catrol module
RAMapb code stream sending module
Detailed description of the invention
Below in conjunction with the accompanying drawing in this utility model embodiment, to the technology in this utility model embodiment
Scheme is clearly and completely described, it is clear that described embodiment is only this utility model one
Divide embodiment rather than whole embodiments.Based on the embodiment in this utility model, this area is common
The every other embodiment that technical staff is obtained under not making creative work premise, broadly falls into this
The scope of utility model protection.
As it is shown in figure 1, a kind of IRIG-B direct current code coding and decoding device, including time receiver module 10,
IRIG-B code output module 20, IRIG-B code receiver module 30, time output module 40, encoding and decoding mould
Block 50 and constant-temperature crystal oscillator 60, the signal input part of described coding/decoding module 50 receive respectively from time
Between receiver module 10, constant-temperature crystal oscillator 60, the TOD time of IRIG-B code receiver module 30 and pulse per second (PPS),
Synchronizing frequency, IRIG-B direct current code, coding/decoding module 50 signal output part output IRIG-B direct current code,
TOD time and pulse per second (PPS) are defeated to the signal of IRIG-B code output module 20, time output module 40 respectively
Enter end.This utility model not only achieves the coding of IRIG-B direct current code, modulation respectively at the micro-place of ARM
Reason device system MSS, FPGA modulating unit are carried out parallel, demodulates, decode respectively at FPGA demodulation list
Unit, ARM microprocessor system MSS are carried out parallel, and this utility model is also equipped with designing simply,
Time service precision is high, the reliable advantage of system stability.
As shown in Figure 4, described coding/decoding module 50 includes SOC(system on a chip) controller, described SOC(system on a chip)
Controller is internally integrated clock generation module Clock, FPGA modulating unit, FPGA demodulating unit, ARM
Microprocessor system MSS；
Described clock generation module Clock receives respectively from time receiver module 10, constant-temperature crystal oscillator 60
Pulse per second (PPS), synchronizing frequency, the signal output part of described clock generation module Clock connects FPGA and adjusts
Unit processed, FPGA demodulating unit, the signal input part of ARM microprocessor system MSS, described FPGA
Modulating unit input input pulse per second (PPS), described ARM microprocessor system MSS receive from time indirect
Receive the TOD time of module 10, ARM microprocessor system MSS for the TOD time encoded and
The TOD time after coding is sent into the IRIG-B direct current being modulated obtaining synchronizing in FPGA modulating unit
Code, the signal of described FPGA modulating unit output IRIG-B direct current code to IRIG-B code output module 20
Input；
Described FPGA demodulating unit receives the IRIG-B direct current code from IRIG-B code receiver module 30,
FPGA demodulating unit is used for being demodulated IRIG-B direct current code, and by decoded IRIG-B direct current code
Send in ARM microprocessor system MSS and be decoded, obtain TOD time and pulse per second (PPS), the institute synchronized
State ARM microprocessor system MSS, FPGA demodulating unit exports TOD time, pulse per second (PPS) respectively to the time
The signal input part of output module 40.
As it is shown in figure 5, described FPGA modulating unit includes code stream receiver module Reg_wrp, a RAM
Module for reading and writing TPSRAM_1, the 2nd RAM module for reading and writing TPSRAM_0 and the first Read-write Catrol module
Out_TPCtrl；Described code stream receiver module Reg_wrp receives and compiles from ARM microprocessor system MSS
The TOD time after Ma, the signal output part of described code stream receiver module Reg_wrp connects the first read-write control
Molding block Out_TPCtrl, a RAM module for reading and writing TPSRAM_1, the 2nd RAM module for reading and writing
The signal input part of TPSRAM_0, described first Read-write Catrol module Out_TPCtrl is used for control first
RAM module for reading and writing TPSRAM_1 and the read-write operation of the 2nd RAM module for reading and writing TPSRAM_0, described
One RAM module for reading and writing TPSRAM_1, the outfan of the 2nd RAM module for reading and writing TPSRAM_0 are all connected with two
Select the signal input part of a selector MX2, the signal output part output IRIG-B direct current code of described MX2
Signal input part to IRIG-B code output module 20.
As shown in Figure 6, described FPGA demodulating unit includes code element identification module EleDetect, decoding mould
Block Decode, the 3rd RAM module for reading and writing TPSRAM_3, the 4th RAM module for reading and writing TPSRAM_4,
Two read-write control module RAMCtrl and code stream sending module RAMapb；Described code element identification module
EleDetect receives the IRIG-B direct current code from IRIG-B code receiver module 30, code element identification module
The signal output part of EleDetect connects decoder module Decode, the second Read-write Catrol module RAMCtrl
Signal input part, described second Read-write Catrol module RAMCtrl for control the 3rd RAM module for reading and writing
TPSRAM_3 and the read-write operation of the 4th RAM module for reading and writing TPSRAM_4, described 3rd RAM reads and writes mould
Block TPSRAM_3, the outfan of the 4th RAM module for reading and writing TPSRAM_4 are all connected with code stream sending module
The signal input part of RAMapb, described code stream sending module RAMapb is for by decoded IRIG-B
Direct current code is sent in ARM microprocessor system MSS and is decoded.
Described SOC(system on a chip) controller chip model is that Microsemi company of the U.S. produces
The M2S025T chip of SmartFusion2 series；Possess that processing speed is fast, low-power consumption, safety and can
By the advantage that property is high.
As in figure 2 it is shown, the frame period of IRIG-B direct current code is 1 second, it is made up of 100 code elements, each
Code element 10ms, symbol width is divided into 8ms, 5ms and 2ms tri-kinds, represent respectively code element " P ", " 1 ",
“0”.For the ease of the information in transmission and extraction B code, every 10 code elements there is a location recognition
Mark, is called P1, P2 ..., P9, P0, frame reference mark be by location recognition mark P0 and
Adjacent reference symbol Pr composition, the forward position of Pr is i.e. quasi-moment second of every frame, namely from this standard
Second moment rises, by the second, point, time, the temporal information such as sky encode, ultimately form DC code.
This utility model in use, can coordinate with software of the prior art and use.Below
In conjunction with software of the prior art, operation principle of the present utility model is described, it must be noted that
It is: the software matched with this utility model is not innovative part of the present utility model, is not this practicality
Novel ingredient.
As it is shown on figure 3, the decoding method of a kind of IRIG-B direct current code coding and decoding device, its core is
According to IRIG-B direct current code agreement, every 1ms corresponding for described IRIG-B direct current code is considered as 1bit, has
Pulsewidth is high level 1, is otherwise low level 0, then three kinds of code elements " P ", " 1 " in IRIG-B direct current code
" 0 " is expressed as 1111111100,1111100000 and 1100000000 with binary data respectively,
Then a frame IRIG-B direct current code is the binary code stream that 100 code elements are 1000bit.
Wherein coded method concrete steps include:
S1, described ARM microprocessor system MSS are received from time reception by TOD_Input serial ports
TOD time of module 10, and the TOD time received is resolved, obtain the second, point, time,
Day, the moon, the temporal information in year, and according to IRIG-B direct current code agreement, ARM microprocessor system MSS
Described temporal information is converted into code element " P ", " 1 ", the form of " 0 ", and enriches and obtain 100 code elements
Frame IRIG-B code data, i.e. expand to the time code stream of 1000bit；Described ARM microprocessor
Described time code stream is stored in the shaping array that a length of 16bit size is 64 by system MSS；Described
The response of ARM microprocessor system MSS is interrupted from the pulse per second (PPS) PPS_in of described time receiver module 10,
When described pulse per second (PPS) PPS_in interrupts, ARM microprocessor system MSS is by the time in described shaping array
Code stream synchronized transmission is to FPGA modulating unit；
S2, described code stream receiver module Reg_wrp receive the shaping from ARM microprocessor system MSS
Time code stream in array, and it is synchronously written a RAM module for reading and writing TPSRAM_1 and the 2nd RAM reading
In writing module TPSRAM_0, described RAM module for reading and writing TPSRAM_1 and a 2nd RAM module for reading and writing
TPSRAM_0 uses ping-pong operation, the first Read-write Catrol module Out_TPCtrl to control a RAM read-write
Control the 2nd RAM module for reading and writing TPSRAM_0 read operation while module TPSRAM_1 write operation, control
RAM read through model TPSRAM_1 read operation is controlled while 2nd RAM module for reading and writing TPSRAM_0 write operation,
So circulate operation；
S3, described clock generation module Clock response from the second arteries and veins of described time receiver module 10
Rush the 10MHz clock Clk10M_in of PPS_in and constant-temperature crystal oscillator 60, clock generation module Clock to produce
The 1KHz clock Clk1KHz_out of raw homology is as a described RAM module for reading and writing TPSRAM_1 and the
The reading clock of two RAM module for reading and writing TPSRAM_0, a RAM module for reading and writing TPSRAM_1 and the 2nd RAM
Module for reading and writing TPSRAM_0 in turn by data in EMS memory with 1bit word length, export 1000bit, obtain with
The DC waveform of the IRIG-B direct current code that described pulse per second (PPS) PPS_in synchronizes.
Described coding/decoding method concrete steps include:
S1, described code element identification module EleDetect receive from IRIG-B code receiver module 30
IRIG-B direct current code, according to IRIG-B direct current code agreement, identifies correspondence code in IRIG-B direct current code automatically
Unit " P ", " 1 " and " 0 ", and respectively with 10bit binary element be expressed as 1111111100,
1111100000 and 1100000000, i.e. Element_Out [9:0]；Use and code element identification module
The 10KHz clock Clk_10K of the local clock homology of EleDetect catches the upper of IRIG-B direct current code
Rise edge and trailing edge, produce the rising edge Pos_Out with local clock homology and trailing edge clock
Neg_Out；
S2, described decoder module Decode according in step S1 produce rising edge Pos_Out,
Binary element Element_In [9:0], decoder module Decode identify IRIG-B direct current code automatically
Frame reference mark pp_flag, is found the frame head of IRIG-B direct current code by described frame reference mark pp_flag,
Then when described rising edge Pos_Out arrives, output binary element Element_In [9:0],
Obtain the binary data of a complete frame IRIG-B direct current code, when decoder module Decode identifies institute
When stating frame reference mark pp_flag, start counting up with the rising edge of the IRIG-B direct current code of input, when
Meter full 99 time, the rising edge of next adjacent IRIG-B direct current code is i.e. as the criterion a second moment mark PPS_flag,
Frame reference pulse PP_Out and quasi-moment second are indicated that PPS_Out sends into ARM microprocessor system MSS
Port, and pulse per second (PPS) is sent the signal input part to time output module 40；
S3, described 3rd RAM module for reading and writing TPSRAM_3 and the 4th RAM module for reading and writing TPSRAM_4 adopt
With ping-pong operation, the second Read-write Catrol module RAMCtrl controls the 3rd RAM module for reading and writing TPSRAM_3
Control the 4th RAM module for reading and writing TPSRAM_4 read operation while write operation, control the 4th RAM read-write
The 3rd RAM module for reading and writing TPSRAM_3 read operation is controlled, so while module TPSRAM_4 write operation
Circulation operation, the second Read-write Catrol module RAMCtrl control stream sending module RAMapb is by the 3rd RAM
Binary data in module for reading and writing TPSRAM_3 or the 4th RAM module for reading and writing TPSRAM_4 internal memory sends
To the bus of ARM microprocessor system MSS；
The response of S4, shown ARM microprocessor system MSS is interrupted from described frame reference pulse PP_Out
Time, ARM microprocessor system MSS synchronizes to read the binary data in bus, and is decoded, root
According to IRIG-B direct current code agreement, ARM microprocessor system MSS extract in described binary data the second, point,
Time, day, the moon, the temporal information in year be converted into TOD time of ASCII fromat；The micro-place of described ARM
When reason device system MSS responds the pulse per second (PPS) PPS_Out interruption from FPGA demodulating unit, described ARM
Microprocessor system MSS synchronizes to send to output module 40 the TOD time through TOD_Output serial ports
Signal input part.
Claims (4)
- null1. an IRIG-B direct current code coding and decoding device，It is characterized in that: include time receiver module (10)、IRIG-B code output module (20)、IRIG-B code receiver module (30)、Time output module (40)、Coding/decoding module (50)、And constant-temperature crystal oscillator (60)，The signal input part of described coding/decoding module (50) receives respectively from time receiver module (10)、Constant-temperature crystal oscillator (60)、The TOD time of IRIG-B code receiver module (30) and pulse per second (PPS)、Synchronizing frequency、IRIG-B direct current code，The signal output part output IRIG-B direct current code of coding/decoding module (50)、TOD time and pulse per second (PPS) are respectively to IRIG-B code output module (20)、The signal input part of time output module (40).
- 2. a kind of IRIG-B direct current code coding and decoding device as claimed in claim 1, it is characterized in that: described coding/decoding module (50) includes that SOC(system on a chip) controller, described SOC(system on a chip) controller are internally integrated clock generation module Clock, FPGA modulating unit, FPGA demodulating unit, ARM microprocessor system MSS；Described clock generation module Clock receives respectively from time receiver module (10), the pulse per second (PPS) of constant-temperature crystal oscillator (60), synchronizing frequency, the signal output part of described clock generation module Clock connects FPGA modulating unit, FPGA demodulating unit, the signal input part of ARM microprocessor system MSS, the input input pulse per second (PPS) of described FPGA modulating unit, described ARM microprocessor system MSS receives the TOD time from time receiver module (10), the TOD time after the outfan output coding of described ARM microprocessor system MSS is to the input of FPGA modulating unit, described FPGA modulating unit output IRIG-B direct current code is to the signal input part of IRIG-B code output module (20)；Described FPGA demodulating unit receives the IRIG-B direct current code from IRIG-B code receiver module (30), the outfan output IRIG-B direct current code of FPGA demodulating unit is to the input of ARM microprocessor system MSS, and described ARM microprocessor system MSS, FPGA demodulating unit export TOD time, the signal input part of pulse per second (PPS) to time output module (40) respectively.
- 3. a kind of IRIG-B direct current code coding and decoding device as claimed in claim 2, it is characterised in that: described FPGA modulating unit includes code stream receiver module Reg_wrp, a RAM module for reading and writing TPSRAM_1, the 2nd RAM module for reading and writing TPSRAM_0 and the first Read-write Catrol module Out_TPCtrl；nullDescribed code stream receiver module Reg_wrp receives the TOD time after encoding from ARM microprocessor system MSS，The signal output part of described code stream receiver module Reg_wrp connects the first Read-write Catrol module Out_TPCtrl、Oneth RAM module for reading and writing TPSRAM_1、The signal input part of the 2nd RAM module for reading and writing TPSRAM_0，The signal output part of described first Read-write Catrol module Out_TPCtrl connects a RAM module for reading and writing TPSRAM_1、The signal input part of the 2nd RAM module for reading and writing TPSRAM_0，A described RAM module for reading and writing TPSRAM_1、The outfan of the 2nd RAM module for reading and writing TPSRAM_0 is all connected with the signal input part of alternative selector MX2，The signal output part output IRIG-B direct current code of described alternative selector MX2 is to the signal input part of IRIG-B code output module (20)；Described FPGA demodulating unit includes code element identification module EleDetect, decoder module Decode, the 3rd RAM module for reading and writing TPSRAM_3, the 4th RAM module for reading and writing TPSRAM_4, the second Read-write Catrol module RAMCtrl and code stream sending module RAMapb；nullDescribed code element identification module EleDetect receives the IRIG-B direct current code from IRIG-B code receiver module (30)，The signal output part of code element identification module EleDetect connects decoder module Decode、The signal input part of the second Read-write Catrol module RAMCtrl，The signal output part of described second Read-write Catrol module RAMCtrl connects the 3rd RAM module for reading and writing TPSRAM_3、The signal input part of the 4th RAM module for reading and writing TPSRAM_4，Described 3rd RAM module for reading and writing TPSRAM_3、The outfan of the 4th RAM module for reading and writing TPSRAM_4 is all connected with the signal input part of code stream sending module RAMapb，The outfan of described code stream sending module RAMapb exports decoded IRIG-B direct current code to the input of ARM microprocessor system MSS.
- 4. a kind of IRIG-B direct current code coding and decoding device as claimed in claim 2, it is characterised in that: described SOC(system on a chip) controller chip model is the M2S025T chip of the SmartFusion2 series that Microsemi company of the U.S. produces.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105553600A (en) * | 2016-01-28 | 2016-05-04 | 安徽四创电子股份有限公司 | IRIG-B direct current code coding and decoding device and coding and decoding method thereof |
| CN107994908A (en) * | 2017-11-22 | 2018-05-04 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | The method for improving B timing code decoding performances |
| CN113869175A (en) * | 2021-09-22 | 2021-12-31 | 成都金诺信高科技有限公司 | High-precision IRIG-B (AC) time code demodulation method based on FPGA + MCU |
| CN114415780A (en) * | 2021-12-30 | 2022-04-29 | 研祥智慧物联科技有限公司 | IRIG-B code-based time synchronization method and device |
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2016
- 2016-01-28 CN CN201620099682.0U patent/CN205490576U/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105553600A (en) * | 2016-01-28 | 2016-05-04 | 安徽四创电子股份有限公司 | IRIG-B direct current code coding and decoding device and coding and decoding method thereof |
| CN105553600B (en) * | 2016-01-28 | 2017-11-07 | 安徽四创电子股份有限公司 | A kind of IRIG B direct currents code coding and decoding device and its decoding method |
| CN107994908A (en) * | 2017-11-22 | 2018-05-04 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | The method for improving B timing code decoding performances |
| CN107994908B (en) * | 2017-11-22 | 2021-07-30 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Method for improving B time code decoding performance |
| CN113869175A (en) * | 2021-09-22 | 2021-12-31 | 成都金诺信高科技有限公司 | High-precision IRIG-B (AC) time code demodulation method based on FPGA + MCU |
| CN114415780A (en) * | 2021-12-30 | 2022-04-29 | 研祥智慧物联科技有限公司 | IRIG-B code-based time synchronization method and device |
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