CN104808481A - Beidou and GPS (Global Positioning System) dual-mode timing embedded time synchronization equipment and software design method - Google Patents
Beidou and GPS (Global Positioning System) dual-mode timing embedded time synchronization equipment and software design method Download PDFInfo
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- G—PHYSICS
- G04—HOROLOGY
- G04R—RADIO-CONTROLLED TIME-PIECES
- G04R20/00—Setting the time according to the time information carried or implied by the radio signal
- G04R20/02—Setting the time according to the time information carried or implied by the radio signal the radio signal being sent by a satellite, e.g. GPS
- G04R20/04—Tuning or receiving; Circuits therefor
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- G—PHYSICS
- G04—HOROLOGY
- G04R—RADIO-CONTROLLED TIME-PIECES
- G04R20/00—Setting the time according to the time information carried or implied by the radio signal
- G04R20/02—Setting the time according to the time information carried or implied by the radio signal the radio signal being sent by a satellite, e.g. GPS
- G04R20/06—Decoding time data; Circuits therefor
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Abstract
The invention discloses Beidou and GPS (Global Positioning System) dual-mode timing embedded time synchronization equipment and a software design method. The Beidou and GPS (Global Positioning System) dual-mode timing embedded time synchronization equipment takes a programmable logic device, a Beidou receiver, a GPS receiver and an embedded microcontroller as a core, and is also provided with an external hardware circuit integrated serial port, an IRIG-B (Inter-Range Instrumentation Group) code input isolation module, an IRIG-B (DC(Direct Current)) code differential output module, an IRIG-B (AC(Alternating Current)) code hardware output module and an IRIG-B (AC) code input decoding module, wherein the embedded microcontroller is connected with an embedded key and a liquid crystal display; an IRIG-B code system is designed by utilizing the programmable logic device and the embodied microcontroller; the current modes, the current time information and the mode states of the five modes, namely, GPS, Beidou, DC code decoding, AC code decoding and time keeping are integrated into a code stream, is transmitted to the embedded microcontroller, is subjected to serial port processing, and is displayed on the liquid crystal display; the requirement on integrating the functions of multi-satellite timing, high-precision time synchronous code encoding outputting and inputting decoding, as well as real-time time information display and mode switching is met.
Description
Technical field
The invention belongs to technical field of satellite time service, be specifically related to a kind of Big Dipper and GPS dual-mode handoff technique of adopting and realize the equipment of time synchronized and the software design approach of its internal processor.
Background technology
Time synchronism equipment is the equipment providing reference time information and frequency information to TT&C system, only has to achieve time synchronized between TT&C system and just can carry out other activities.The core of its technology is the transmission of the synchronous and timing code of time service, and along with the appearance of numerous time service mode and fast development, Time synchronization technique is also constantly advanced at last.
The transmission of timing code then is mainly carried out designing to IRIG-B code and uses, and format standard customizes the target range instrument group (Inter-Range Instrumentation Group, IRIG) in the target range commandant council of U.S. subordinate.As a kind of important serial time code for time synchronized, IRIG-B code is divided into direct current code (DC code) and alternating current code (AC code) two kinds of forms, is applied to target range measurement and control center, command of armed force center and electric system etc. widely.
The domestic development for time synchronism equipment experienced by one by the process being introduced into domestic production abroad.As far back as twentieth century fifties, because the experiment of weapon needs China to have purchased first set time synchronism equipment from the Soviet Union, demand afterwards in order to meet various experiment is domestic also have developed many eurypalynous terminals in succession, but because the standard that neither one is unified had once occurred that equipment was various in style, parameter is different, bulky and design concept complicated situation, the time encoding clock that it is form type code that China in 1984 have developed with IRIG-B code, because of its synchronization accuracy, the indices such as frequency and reliability all reaches requirement and in 1986 using the first-selected code of IRIG-B code as synchronizer.Though because manufacturer makes product there is subproblem for grasps unskillful of technical standard in a period of time thereafter, the synchronization criterion of country's promulgation afterwards made this situation be improved.From the nineties till now twenties years, country of the Chinese Academy of Sciences has also issued at time service center the time synchronism apparatus based on IRIG-B code in succession, but all comparatively single in the realization of function, such as realizes the generation etc. of direct current code or alternating current code based on GPS.Although these products are also for provide good standard in the industry, consider the restriction of partial condition, only having combines the Big Dipper of GPS and China's independent research carries out bimodulus time service and just can realize the synchronous of time better.
Current existing time synchronism equipment is all generally adopt single time service mode, for time synchronized code also just single coding or decoding and for real-time time information neither one Presentation Function.Along with the development of science and technology, slowly can not satisfy the demands for the time synchronized code coding and decoding precision also resting on national standard aspect.
Summary of the invention
In order to solve the problem, the invention provides a kind of Big Dipper and the embedded time synchronism equipment of GPS dual-mode time service and software design approach, this Big Dipper and the embedded time synchronism equipment of GPS dual-mode time service and software design approach overcomes the time service mode of above-mentioned such as time synchronized and functional realiey is single, the defect of time precision not in high-technology, meet that the multiple satellite time transfer mode, the precise synchronization code coding that are switched by software intelligence are exported, time synchronized code input decoding and real-time time information displaying with mode switch function in requirement integrally.
The present invention in order to the technical scheme solving its technical matters and adopt is:
A kind of Big Dipper and the embedded time synchronism equipment of GPS dual-mode time service, the Beidou receiver comprising programmable logic device (PLD) and be connected with described programmable logic device (PLD) respectively, GPS and embedded microcontroller, also be provided with the integrated serial ports of external hardware circuit be connected with described programmable logic device (PLD) respectively, IRIG-B (DC) code input isolation module, IRIG-B (DC) code difference output module, IRIG-B (AC) code hardware output module and IRIG-B (AC) code input decoder module, wherein, described programmable logic device (PLD) adopts EP2C8T144C8N, described embedded microcontroller adopts STM32F103RBT6, described embedded microcontroller has key-press input interface and LCD display output interface, described key-press input interface connects embedded button, described LCD display output interface connects embedded liquid crystal display, host computer is connected with the integrated serial ports of described external hardware circuit.
Say further, IRIG-B (AC) code hardware output module comprises the DA conversion chip, low-pass filter, operational amplifier and the transformer that connect successively.
Say further, IRIG-B (AC) code input decoder module has the isolating transformer, absolute value amplifying circuit, the Zero-cross comparator circuit that connect successively.
Say further, IRIG-B (DC) code input isolation module has isolating chip and insulating power supply.
Say further, described programmable logic device (PLD) is connected with described Beidou receiver and described GPS by I/O port.
Say further, described programmable logic device (PLD) is connected by I/O port with described IRIG-B (AC) code hardware output module.
Say further, described programmable logic device (PLD) and described IRIG-B (AC) code input the I/O port being reserved with between decoder module and carrying out pulse signal transmission.
Say further, described programmable logic device (PLD) is inputted isolation module with described IRIG-B (DC) code and is connected by I/O port.
The core concept of the software design approach of the above-mentioned Big Dipper and the embedded time synchronism equipment of GPS dual-mode time service is: utilize programmable logic device (PLD) and embedded microcontroller to carry out the system of time synchronized code IRIG-B code, by the mode of agreement, the state set of the present mode of GPS, the Big Dipper, the decoding of direct current code, alternating current code decoding, punctual five kinds of modes, current time information and pattern is formed in a code stream, be transferred to embedded microcontroller and carry out serial ports process operation, thus shown by liquid crystal display.
Say further, it is the modeling approach utilizing programmable logic device (PLD), send at programmable logic device (PLD) indoor design serial ports and receive general module, serial ports sends and receives general module and receive GNRMC code stream that Beidou receiver sends and the GPRMC code stream that GPS sends and design parsing module and extract time in code stream, pulse per second (PPS), locating information, thus Software Coding design is carried out to the direct current code of time synchronized code and liquid crystal display use is carried out to the Big Dipper/gps time information and locating information, selection as the Big Dipper and GPS pattern then carries out selection control by host computer or embedded button, IRIG-B (AC) code then forms module logic design development by IRIG-B (DC) code by alternating current code, for the decoded portion of IRIG-B code then by after hardware isolated process, software module design in conjunction with programmable logic device (PLD) inside carries out the extraction of temporal information, the Big Dipper the most at last, GPS, IRIG-B (DC) code is decoded, the present mode of the decoding of IRIG-B (AC) code and time five kinds of modes of keeping time, the state set of current time information and pattern is formed in a code stream, be transferred to after embedded microcontroller carries out serial ports process by the mode of protocol transmission, shown by embedded liquid crystal display.
Say further, wherein, the software design approach of the Big Dipper/GPS dual-mode time service part is as follows:
Temporal information, locating information and pulse per second (PPS) information is comprised in the $ GNRMC code stream that Beidou receiver sends and the $ GPRMC code stream that GPS sends, after utilizing programmable logic device (PLD) to extract relevant information, establishment model handover module, mode switch module by judging that switching command carries out the selection of the Big Dipper or GPS, thus exports pps pulse per second signal 1PPS and temporal information TOD;
Pattern is switched, here realized by two kinds of modes: one is that host computer switches, host computer utilizes serial ports to send a string command, and programmable logic device (PLD) in serial port command parsing module, extract mode command after being received by serial ports receiver module and then under switching the Big Dipper or GPS pattern, temporal information uses; Another kind is that embedded button switches, and by embedded button, carry out the selection of the Big Dipper or GPS pattern in display end, then send to programmable logic device (PLD) to process by self-defining protocol streams mode the change of information, and then implementation pattern switches;
The satellite time transfer pattern of system default uses GPS pattern, in the process of model selection, when the Big Dipper under current state or gps satellite receive invalid, then can be switched to self-defined time service pattern.
Furthermore, pattern is switched, the mode that programmable logic controller (PLC) is triggered by pulse per second (PPS) sends protocol command to embedded microcontroller p.s., embedded liquid crystal display then shows current time and pattern in real time, carries out the replacement of pattern when embedded button carries out then sending when pattern switches other protocol command to programmable logic device (PLD).
Say further, wherein, the software design approach of IRIG-B code coded portion is as follows:
The coding of codimg logic design primarily of IRIG-B (DC) code of IRIG-B code and coding two parts composition of IRIG-B (AC) code, the codimg logic design of IRIG-B (DC) code converts temporal information to direct current signal by a case statement, the codimg logic of IRIG-B (AC) code is then the digital form by design, direct current code conversion being become alternating current code, is convenient to follow-up hardware handles.
Furthermore, IRIG-B (DC) code codimg logic method for designing is as follows:
The symbol width of IRIG-B code is 10ms, so only need consider to represent when Logic Circuit Design is carried out in programmable logic device (PLD) inside, that 0,1 and the clock count value of position code three data and bimodulus time service provides between pulse per second (PPS) and the beginning flag of DC code is synchronous, the former three values are all carry out width setting by counter register, and the latter is then synchronous by starting register count method to realize after high level that pulse per second (PPS) detected;
Most important in coding module design is the use of state machine, complete coding forming process has been shifted by 54 states, three enabling signal c2 are divided in state machine, c5, c8, c2 is low level enabling signal, c5 is high level enabling signal, c8 is the enabling signal of position code, due to the Logic Circuit Design using the clock of 50MHz to carry out system, so each code element needs 500_000 clock period, when c2 starts the high level that hour counter need count 100_000 clock period, the low level of 400_000 clock period represents the low level " 0 " in direct current code, high level and position code method for expressing are analogized, in state machine, state 0 represents the startup c8 when pulse per second (PPS) high level arrives, when counter counts counts to closedown c8 steering state 1 when 19 ' d499_999 and width have reached 10ms, otherwise circular wait by three enabling signals all clear 0 in state 0, the binary-coded decimal that state 1 ~ 4 is used for producing a position current second exports, by judging that the low and high level of every starts c2 or c8, state 5 is index mark positions is that low level only need start c2, state 6 ~ 8 is used for producing the binary-coded decimal of ten output current second, and the method for generation is consistent with method for position second, state 10 ~ 18 is used for producing the output of current minute information, the output of information when state 20 ~ 26 is used for producing current, state 30 ~ 38,40 ~ 41 is used for producing the output of current number of days information, state 9,19,29,39 and state 52 are used for carrying out the generation of P1 ~ P9, state 53 is used for producing P0 for last state, finally will leave the 1ms time to forward the arrival that state 0 is used for waiting for pulse per second (PPS) high level to, thus makes pulse precision reach the highest, other state is all used to the output producing low level signal, after state machine setting, in order to ensure the integrality of the reception of front end data, carry out the renewal of temporal information when the rising edge of pulse per second (PPS) being detected, this can play the effect of refresh time p.s..
Furthermore, wherein, IRIG-B (AC) code codimg logic method for designing is as follows:
The digital signal of IRIG-B (AC) code obtains after being formed and being input to address generating module, sine value ROM storage list module and D/A conversion module by IRIG-B (DC) code.
Say further, wherein, IRIG-B (DC) code decode logic method for designing is as follows:
The design core of this module is the identification to code element, the 10kHz pulse produced by major clock frequency division is as the global clock of direct current code decoder module, DC code in transmitting procedure because the interference of passage can generating portion deformation, this just makes the width of each code element to change, so specify that when carrying out high level number and judging the clock number of " P " is 70 ~ 90, the clock number of logic " 0 " is 10 ~ 30, the clock number of logical one is 40 ~ 60, the width identifying code element can carry out judgement and the extraction of relevant information, mainly be divided into two parts: the extraction of pulse per second (PPS) and the extraction of temporal information:
The synchronous extraction of one .DC code pulse per second (PPS)
For the extraction of pulse per second (PPS), adopt at least one in following three kinds of methods:
1) accurate counting method
Adopt three states to carry out monitoring to the pulse per second (PPS) of DC code to extract, state S0 represents and when monitoring a 8ms pulsewidth after, jumps to state S1 otherwise continuous circulation searching; State S1 represents after again monitoring a 8ms pulsewidth, jumps to state S2, and no person jumps to state S0 and again monitors; State S2 represents that now inspected is to two 8ms pulsewidths, when the rising edge of a code element after PR being detected, jump to state S0 after giving an enabling signal and carry out continuation monitoring, this enabling signal then open time delay register time delay counting, giving a width as time delay 990ms is the high impulse of 1ms, and namely this high impulse is required pulse per second (PPS);
2) position mark detection method
Give the label that each identification code is different, label 0 from the label 10 of P9 to P0 successively decreases one by one, and three states in utilization state machine carry out the extraction of pulse per second (PPS), state S0 plays a monitoring pulsewidth and label is carried out to the effect of addition process, if next mode bit is PR, then now label should be 11, composes at once and is 0 and is checked through a 8ms pulsewidth, then need unlatching starting switch, be used for producing pulse per second (PPS); State S1 is then mainly used in the monitoring of state, jumps to state S2 when the pulsewidth detected is 8ms, otherwise turns back to state S0 continuation monitoring; The major function of state S2 is that the label giving current PR state puts 1;
3) waveform phase ' with ' method
The difference of the method and accurate counting method is only to need to count down to 989.5ms the time counted here, leaves 1.5ms as a pseudo-pulse per second (PPS) 1pps_1, finally DC code is carried out phase AND-operation with pseudo-pulse per second (PPS) thus obtain pulse per second (PPS);
Two. temporal information is extracted
Extraction for the time in code stream carries out global design by record, conversion and binary-coded decimal three modules here, the Main Function of logging modle is used to the clock number recording the label between every two location recognition mark P, the figure place corresponding to each code element and represent this code element high level width, the function of modular converter is that the cell count width that utilizes front end to extract and figure place are carried out entirety and judged thus draw every corresponding binary code, and the function of binary-coded decimal module is that the binary code that front end is extracted is transformed into corresponding binary-coded decimal.
Say further, wherein, IRIG-B (AC) code decode logic method for designing is as follows:
Deformation can be there is when AC signal is transmitted in the channel, the phenomenons such as decay, as the information in AC signal need extracted, just first must carry out waveform processing to it, after hardware handles is carried out to AC code, produced pulse signal and sinusoidal signal all need to be connected to the extraction carrying out amplitude in embedded microcontroller, this has just used external interrupt and the AD conversion function of STM32F103RBT6, due to the AC code amplitude of routine between 3 ~ 5V so first regulate slide rheostat to control between 1.8 ~ 3V by the amplitude of voltage according to designing requirement, again by judging whether the value collected is greater than this intermediate value of 1.4V and produces DC pulse, because the DC pulse that generated by embedded microcontroller is except than except the DC code time delay 250 μ s of standard, contained temporal information is the same, so the extracting method of just pulse per second (PPS) has difference on decode operation, pulse per second (PPS) is extracted and can only use described waveform phase "AND" method.
The invention has the beneficial effects as follows:
1) in the selection of time service pattern, the integrated Big Dipper and GPS two kinds, pattern adopt the process of host computer serial ports and the two kinds of mode collaborative works of embedded keystroke handling on switching;
2) integrated time synchronized code encoding and decoding integration in functions of the equipments;
3) utilize between embedded microcontroller and programmable logic device (PLD) and set up unique protocol channel, for showing the Big Dipper/GPS/ direct current code decoding/alternating current code decoding/self-defined punctual five kinds of times and state;
4) in the logical design of direct current code decoder module, propose novel mode and make direct current code precision exceed existing standard (standard 1us, encoding precision 80ns, decode precision 60ns) far away;
5) in the design of direct current code decoding hardware, isolation method is adopted to make programmable logic device (PLD) avoid breakdown problem;
6) in the design of alternating current code coding module, use comparatively advanced AD conversion chip to carry out circuit design, thus promote stability and the precision of alternating current code output;
7) in the design of alternating current code decoder module, use comparatively advanced embedded microcontroller to carry out circuit design, thus promote alternating current code decoding efficiency.
Accompanying drawing explanation
Fig. 1 is the theory diagram of the Big Dipper of the present invention and the embedded time synchronism equipment of GPS dual-mode time service;
Fig. 2 is programmable logic device (PLD) in house software Modeling and Design block diagram of the present invention;
Fig. 3 is programmable logic device (PLD) internal logic of the present invention design framework;
Fig. 4 is the Big Dipper of the present invention/GPS model selection switching flow figure;
Fig. 5 is the RTL view of IRIG-B of the present invention (DC) code coding module;
Fig. 6 is the RTL view of IRIG-B of the present invention (AC) code coding module;
Fig. 7 is the synchronous extraction method figure of DC code of the present invention pulse per second (PPS);
Fig. 8 is that DC code temporal information of the present invention extracts RTL view;
Fig. 9 is IRIG-B of the present invention (AC) code decoding overall design block diagram;
Figure 10 is the amplitude collecting flowchart figure of AC code of the present invention;
Figure 11 is the hardware elementary diagram of IRIG-B of the present invention (AC) code input decoder module;
Figure 12 is that embedded liquid crystal display modes of the present invention arranges figure.
Embodiment
Below by way of specific instantiation, the specific embodiment of the present invention is described, those skilled in the art can understand advantage of the present invention and effect easily by content disclosed in the present specification.The present invention also can be implemented in further, different ways, that is, not departing under disclosed category, can give different modifications and change.
Embodiment: a kind of Big Dipper and the embedded time synchronism equipment of GPS dual-mode time service, the Beidou receiver 2, GPS 3 and the embedded microcontroller 4 that comprise programmable logic device (PLD) 1 and be connected with described programmable logic device (PLD) respectively, also be provided with the integrated serial ports 5 of the external hardware circuit be connected with described programmable logic device (PLD) respectively, IRIG-B (DC) code inputs isolation module 6, IRIG-B (DC) code difference output module 7, IRIG-B (AC) code hardware output module 8 and IRIG-B (AC) code input decoder module 9, as shown in Figure 1.Wherein, described programmable logic device (PLD) adopts EP2C8T144C8N, described embedded microcontroller adopts STM32F103RBT6, described embedded microcontroller has key-press input interface and LCD display output interface, described key-press input interface connects embedded button, described LCD display output interface connects embedded liquid crystal display, and host computer is connected with the integrated serial ports of described external hardware circuit.
IRIG-B (AC) code hardware output module comprises the DA conversion chip, low-pass filter, operational amplifier and the transformer that connect successively, the digital signal of alternating current code that what programmable logic device (PLD) indoor design finally exported is, by DA conversion chip and subsequent treatment outputting analog signal, after DA conversion chip output difference sub-signal, in order to prevent interference, signal is carried out filtering process through 7 rank low-pass filters, due to the signal after device after filtering or differential signal, so differential signal will be become single-ended signal through operational amplifier.
IRIG-B (AC) code input decoder module has the isolating transformer, absolute value amplifying circuit, the Zero-cross comparator circuit that connect successively.IRIG-B (AC) code deforms the phenomenons such as decay after transmission, certainly need when decoding to carry out hardware handles to it, isolating transformer is to the AC signal of input be carried out every straight-through friendship process, absolute value amplifying circuit is used to produce the anti-phase AC signal of two-way constant amplitude, Zero-cross comparator circuit is the frequency signal in order to generate needed for decoding, and the hardware elementary diagram of IRIG-B (AC) code input decoder module as shown in figure 11.
IRIG-B (DC) code input isolation module has isolating chip and insulating power supply.
Described programmable logic device (PLD) is connected with described Beidou receiver and described GPS by I/O port.
Described programmable logic device (PLD) is connected by I/O port with described IRIG-B (AC) code hardware output module.
Described programmable logic device (PLD) and described IRIG-B (AC) code input the I/O port being reserved with between decoder module and carrying out pulse signal transmission.
Described programmable logic device (PLD) is inputted isolation module with described IRIG-B (DC) code and is connected by I/O port.
The software design approach of the above-mentioned Big Dipper and the embedded time synchronism equipment of GPS dual-mode time service, utilize the modeling approach of programmable logic device (PLD), send at programmable logic device (PLD) indoor design serial ports and receive general module, serial ports sends and receives general module and receive GNRMC code stream that Beidou receiver sends and the GPRMC code stream that GPS sends and design parsing module and extract time in code stream, pulse per second (PPS), locating information, thus Software Coding design is carried out to the direct current code of time synchronized code and liquid crystal display use is carried out to the Big Dipper/gps time information and locating information, selection as the Big Dipper and GPS pattern then carries out selection control by host computer or embedded button, IRIG-B (AC) code then forms module logic design development by IRIG-B (DC) code by alternating current code, programmable logic device (PLD) in house software Modeling and Design block diagram as shown in Figure 2.For the decoded portion of IRIG-B code then by after hardware isolated process, software module design in conjunction with programmable logic device (PLD) inside carries out the extraction of temporal information, the Big Dipper the most at last, GPS, IRIG-B (DC) code is decoded, the present mode of the decoding of IRIG-B (AC) code and time five kinds of modes of keeping time, the state set of current time information and pattern is formed in a code stream, be transferred to after embedded microcontroller carries out serial ports process by the mode of protocol transmission, shown (default conditions are GPS accepting state) by embedded liquid crystal display, as shown in figure 12.
Wherein, the software design approach of the Big Dipper/GPS dual-mode time service part is as follows:
Temporal information, locating information and pulse per second (PPS) information is comprised in the $ GNRMC code stream that Beidou receiver sends and the $ GPRMC code stream that GPS sends, after utilizing programmable logic device (PLD) to extract relevant information, establishment model handover module, mode switch module by judging that switching command carries out the selection of the Big Dipper or GPS, thus exports pps pulse per second signal 1PPS and temporal information TOD;
Pattern is switched, here realized by two kinds of modes: one is that host computer switches, host computer utilizes serial ports to send a string command, and programmable logic device (PLD) in serial port command parsing module, extract mode command after being received by serial ports receiver module and then under switching the Big Dipper or GPS pattern, temporal information uses; Another kind is that embedded button switches, by embedded button, the selection of the Big Dipper or GPS pattern is carried out in display end, programmable logic device (PLD) is sent to process by self-defining protocol streams mode the change of information again, and then implementation pattern switches, the priority of two kinds of switching modes is that host computer switches to master, embedded button switches to auxiliary.
The satellite time transfer pattern of system default uses GPS pattern, and in the process of model selection, when the Big Dipper under current state or gps satellite receive invalid, then can be switched to self-defined time service pattern, its Flow Chart Design as shown in Figure 4.
Pattern is switched, the mode that programmable logic controller (PLC) is triggered by pulse per second (PPS) sends protocol command to embedded microcontroller p.s., embedded liquid crystal display then shows current time and pattern in real time, carry out the replacement of pattern when embedded button carries out then sending when pattern switches other protocol command to programmable logic device (PLD), its logical design as shown in figure 12.
Wherein, the software design approach of IRIG-B code coded portion is as follows:
The coding of codimg logic design primarily of IRIG-B (DC) code of IRIG-B code and coding two parts composition of IRIG-B (AC) code, the codimg logic design of IRIG-B (DC) code converts temporal information to direct current signal by a case statement, the codimg logic of IRIG-B (AC) code is then the digital form by design, direct current code conversion being become alternating current code, is convenient to follow-up hardware handles.
IRIG-B (DC) code codimg logic method for designing is as follows:
The symbol width of IRIG-B code is 10ms, so only need consider to represent when Logic Circuit Design is carried out in programmable logic device (PLD) inside, that 0,1 and the clock count value of position code three data and bimodulus time service provides between pulse per second (PPS) and the beginning flag of DC code is synchronous, the former three values are all carry out width setting by counter register, and the latter is then synchronous by starting register count method to realize after high level that pulse per second (PPS) detected;
Most important in coding module design is the use of state machine, complete coding forming process has been shifted by 54 states, three enabling signal c2 are divided in state machine, c5, c8, c2 is low level enabling signal, c5 is high level enabling signal, c8 is the enabling signal of position code, due to the Logic Circuit Design using the clock of 50MHz to carry out system, so each code element needs 500_000 clock period, when c2 starts the high level that hour counter need count 100_000 clock period, the low level of 400_000 clock period represents the low level " 0 " in direct current code, high level and position code method for expressing are analogized, in state machine, state 0 represents the startup c8 when pulse per second (PPS) high level arrives, when counter counts counts to closedown c8 steering state 1 when 19 ' d499_999 and width have reached 10ms, otherwise circular wait by three enabling signals all clear 0 in state 0, the binary-coded decimal that state 1 ~ 4 is used for producing a position current second exports, by judging that the low and high level of every starts c2 or c8, state 5 is index mark positions is that low level only need start c2, state 6 ~ 8 is used for producing the binary-coded decimal of ten output current second, and the method for generation is consistent with method for position second, state 10 ~ 18 is used for producing the output of current minute information, the output of information when state 20 ~ 26 is used for producing current, state 30 ~ 38,40 ~ 41 is used for producing the output of current number of days information, state 9,19,29,39 and state 52 are used for carrying out the generation of P1 ~ P9, state 53 is used for producing P0 for last state, finally will leave the 1ms time to forward the arrival that state 0 is used for waiting for pulse per second (PPS) high level to, thus makes pulse precision reach the highest, other state is all used to the output producing low level signal, after state machine setting, in order to ensure the integrality of the reception of front end data, carry out the renewal of temporal information when the rising edge of pulse per second (PPS) being detected, this can play the effect of refresh time p.s., and the RTL view of IRIG-B (DC) code coding module as shown in Figure 5.
IRIG-B (AC) code codimg logic method for designing is as follows: it is be input to address generating module by IRIG-B (DC) code that the digital signal of IRIG-B (AC) code is formed, obtain after sine value ROM storage list module and D/A conversion module, three modules design the RTL view of generation as shown in Figure 6 in the programmable logic device, address generating module U1 is for generation of the address of sine wave output, consider that sinusoidal wave precision problem uses 1000 points to gather here, therefore the sine wave freuqency of 1kHz makes the clock frequency in AC code coding module be 1MHz, when the high level of DC code being detected, address each clock from 1024 adds 1 and is added to 2023 always, when the low level of DC code being detected, address each clock from 0 adds 1 and is added to 999 always, the design of address generating module is completed with this, sine value ROM storage list module U2 to utilize in altera corp Quartus II 9.0 rom of customization to construct .mif file thus carries out the sinusoidal wave number storage that the different but frequency of two kinds of amplitudes be all 1kHz, digital signal is mainly converted to the data of applicable DA conversion chip form by D/A conversion module U3.
IRIG-B (DC) code decode logic method for designing is as follows: the design core of this module is the identification to code element, the 10kHz pulse produced by major clock frequency division is as the global clock of direct current code decoder module, DC code in transmitting procedure because the interference of passage can generating portion deformation, this just makes the width of each code element to change, so specify that when carrying out high level number and judging the clock number of " P " is 70 ~ 90, the clock number of logic " 0 " is 10 ~ 30, the clock number of logical one is 40 ~ 60, the width identifying code element can carry out judgement and the extraction of relevant information, mainly be divided into two parts: the extraction of pulse per second (PPS) and the extraction of temporal information:
The synchronous extraction of one .DC code pulse per second (PPS)
For the extraction of pulse per second (PPS), adopt at least one in following three kinds of methods:
1) accurate counting method
Adopt three states to carry out monitoring to the pulse per second (PPS) of DC code to extract, state S0 represents and when monitoring a 8ms pulsewidth after, jumps to state S1 otherwise continuous circulation searching; State S1 represents after again monitoring a 8ms pulsewidth, jumps to state S2, and no person jumps to state S0 and again monitors; State S2 represents that now inspected is to two 8ms pulsewidths, when the rising edge of a code element after PR being detected, jump to state S0 after giving an enabling signal and carry out continuation monitoring, this enabling signal then open time delay register time delay counting, giving a width as time delay 990ms is the high impulse of 1ms, and namely this high impulse is required pulse per second (PPS), theoretical thought as shown in Figure 9;
2) position mark detection method
Give the label that each identification code is different, label 0 from the label 10 of P9 to P0 successively decreases one by one, and three states in utilization state machine carry out the extraction of pulse per second (PPS), state S0 plays a monitoring pulsewidth and label is carried out to the effect of addition process, if next mode bit is PR, then now label should be 11, composes at once and is 0 and is checked through a 8ms pulsewidth, then need unlatching starting switch, be used for producing pulse per second (PPS); State S1 is then mainly used in the monitoring of state, jumps to state S2 when the pulsewidth detected is 8ms, otherwise turns back to state S0 continuation monitoring; The major function of state S2 is that the label giving current PR state puts 1, and its theoretical thought as shown in Figure 9;
3) waveform phase ' with ' method
The difference of the method and accurate counting method is the time counted, here only need to count down to 989.5ms, leave 1.5ms as a pseudo-pulse per second (PPS) 1pps_1, finally DC code carried out phase AND-operation with pseudo-pulse per second (PPS) thus obtain pulse per second (PPS), its theoretical thought as shown in Figure 9;
Two. temporal information is extracted
Extraction for the time in code stream carries out global design by record, conversion and binary-coded decimal three modules here, the RTL view produced as shown in Figure 8, the Main Function of logging modle U2 is used to the clock number (temp) recording the label (biaoh) between every two location recognition mark P, the figure place (wei) corresponding to each code element and represent this code element high level width, clk is the clock signal of 10kHz, bcode is the input signal of direct current code, and pps is front-end demodulation pps pulse per second signal out; The function of modular converter U3 is that the cell count width that utilizes front end to extract and figure place are carried out entirety and judged thus draw every corresponding binary code; The function of binary-coded decimal module U4 is that the binary code that front end is extracted is transformed into corresponding binary-coded decimal, and label, by representing the time zone of each section, adds the data information extracted, therefore can carry out the reading of temporal information by label.
IRIG-B (AC) code decode logic method for designing is as follows: deformation can occur when AC signal is transmitted in the channel, the phenomenons such as decay, as the information in AC signal need extracted, just first must carry out waveform processing to it, after hardware handles is carried out to AC code, produced pulse signal and sinusoidal signal all need to be connected to the extraction carrying out amplitude in embedded microcontroller, this has just used external interrupt and the AD conversion function of STM32F103RBT6, due to the AC code amplitude of routine between 3 ~ 5V so first regulate slide rheostat to control between 1.8 ~ 3V by the amplitude of voltage according to designing requirement, again by judging whether the value collected is greater than this intermediate value of 1.4V and produces DC pulse, IRIG-B (AC) code decoding overall design block diagram as shown in Figure 9, the amplitude collecting flowchart figure of AC code as shown in Figure 10, because the DC pulse that generated by embedded microcontroller is except than except the DC code time delay 250 μ s of standard, contained temporal information is the same, so the extracting method of just pulse per second (PPS) has difference on decode operation, pulse per second (PPS) is extracted and can only use described waveform phase "AND" method.
Claims (17)
1. a Big Dipper and the embedded time synchronism equipment of GPS dual-mode time service, it is characterized in that: the Beidou receiver (2) comprising programmable logic device (PLD) (1) and be connected with described programmable logic device (PLD) respectively, GPS (3) and embedded microcontroller (4), also be provided with the integrated serial ports of external hardware circuit (5) be connected with described programmable logic device (PLD) respectively, IRIG-B (DC) code input isolation module (6), IRIG-B (DC) code difference output module (7), IRIG-B (AC) code hardware output module (8) and IRIG-B (AC) code input decoder module (9), wherein, described programmable logic device (PLD) adopts EP2C8T144C8N, described embedded microcontroller adopts STM32F103RBT6, described embedded microcontroller has key-press input interface and LCD display output interface, described key-press input interface connects embedded button, described LCD display output interface connects embedded liquid crystal display, host computer is connected with the integrated serial ports of described external hardware circuit.
2. the Big Dipper as claimed in claim 1 and the embedded time synchronism equipment of GPS dual-mode time service, is characterized in that: IRIG-B (AC) code hardware output module comprises the DA conversion chip, low-pass filter, operational amplifier and the transformer that connect successively.
3. the Big Dipper as claimed in claim 1 and the embedded time synchronism equipment of GPS dual-mode time service, is characterized in that: IRIG-B (AC) code input decoder module has the isolating transformer, absolute value amplifying circuit, the Zero-cross comparator circuit that connect successively.
4. the Big Dipper as claimed in claim 1 and the embedded time synchronism equipment of GPS dual-mode time service, is characterized in that: IRIG-B (DC) code input isolation module has isolating chip and insulating power supply.
5. the Big Dipper as claimed in claim 1 and the embedded time synchronism equipment of GPS dual-mode time service, is characterized in that: described programmable logic device (PLD) is connected with described Beidou receiver and described GPS by I/O port.
6. the Big Dipper as claimed in claim 1 and the embedded time synchronism equipment of GPS dual-mode time service, is characterized in that: described programmable logic device (PLD) is connected by I/O port with described IRIG-B (AC) code hardware output module.
7. the Big Dipper as claimed in claim 1 and the embedded time synchronism equipment of GPS dual-mode time service, is characterized in that: described programmable logic device (PLD) and described IRIG-B (AC) code input the I/O port being reserved with between decoder module and carrying out pulse signal transmission.
8. the Big Dipper as claimed in claim 1 and the embedded time synchronism equipment of GPS dual-mode time service, is characterized in that: described programmable logic device (PLD) is inputted isolation module with described IRIG-B (DC) code and is connected by I/O port.
9. the software design approach of a Big Dipper as claimed in claim 1 and the embedded time synchronism equipment of GPS dual-mode time service, it is characterized in that: utilize programmable logic device (PLD) and embedded microcontroller to carry out the system of time synchronized code IRIG-B code, by the mode of agreement, the state set of the present mode of GPS, the Big Dipper, the decoding of direct current code, alternating current code decoding, punctual five kinds of modes, current time information and pattern is formed in a code stream, be transferred to embedded microcontroller and carry out serial ports process operation, thus shown by liquid crystal display.
10. the software design approach of the Big Dipper as claimed in claim 9 and the embedded time synchronism equipment of GPS dual-mode time service, it is characterized in that: the modeling approach utilizing programmable logic device (PLD), send at programmable logic device (PLD) indoor design serial ports and receive general module, serial ports sends and receives general module and receive GNRMC code stream that Beidou receiver sends and the GPRMC code stream that GPS sends and design parsing module and extract time in code stream, pulse per second (PPS), locating information, thus Software Coding design is carried out to the direct current code of time synchronized code and liquid crystal display use is carried out to the Big Dipper/gps time information and locating information, selection as the Big Dipper and GPS pattern then carries out selection control by host computer or embedded button, IRIG-B (AC) code then forms module logic design development by IRIG-B (DC) code by alternating current code, for the decoded portion of IRIG-B code then by after hardware isolated process, software module design in conjunction with programmable logic device (PLD) inside carries out the extraction of temporal information, the Big Dipper the most at last, GPS, IRIG-B (DC) code is decoded, the present mode of the decoding of IRIG-B (AC) code and time five kinds of modes of keeping time, the state set of current time information and pattern is formed in a code stream, be transferred to after embedded microcontroller carries out serial ports process by the mode of protocol transmission, shown by embedded liquid crystal display.
The software design approach of 11. Big Dippeves as claimed in claim 10 and the embedded time synchronism equipment of GPS dual-mode time service, is characterized in that: the software design approach of the Big Dipper/GPS dual-mode time service part:
Temporal information, locating information and pulse per second (PPS) information is comprised in the $ GNRMC code stream that Beidou receiver sends and the $ GPRMC code stream that GPS sends, after utilizing programmable logic device (PLD) to extract relevant information, establishment model handover module, mode switch module by judging that switching command carries out the selection of the Big Dipper or GPS, thus exports pps pulse per second signal 1PPS and temporal information TOD;
Pattern is switched, here realized by two kinds of modes: one is that host computer switches, host computer utilizes serial ports to send a string command, and programmable logic device (PLD) in serial port command parsing module, extract mode command after being received by serial ports receiver module and then under switching the Big Dipper or GPS pattern, temporal information uses; Another kind is that embedded button switches, and by embedded button, carry out the selection of the Big Dipper or GPS pattern in display end, then send to programmable logic device (PLD) to process by self-defining protocol streams mode the change of information, and then implementation pattern switches;
The satellite time transfer pattern of system default uses GPS pattern, in the process of model selection, when the Big Dipper under current state or gps satellite receive invalid, then can be switched to self-defined time service pattern.
The software design approach of 12. Big Dippeves as claimed in claim 11 and the embedded time synchronism equipment of GPS dual-mode time service, it is characterized in that: pattern is switched, the mode that programmable logic controller (PLC) is triggered by pulse per second (PPS) sends protocol command to embedded microcontroller p.s., embedded liquid crystal display then shows current time and pattern in real time, carries out the replacement of pattern when embedded button carries out then sending when pattern switches other protocol command to programmable logic device (PLD).
The software design approach of 13. Big Dippeves as claimed in claim 10 and the embedded time synchronism equipment of GPS dual-mode time service, is characterized in that: the software design approach of IRIG-B code coded portion:
The coding of codimg logic design primarily of IRIG-B (DC) code of IRIG-B code and coding two parts composition of IRIG-B (AC) code, the codimg logic design of IRIG-B (DC) code converts temporal information to direct current signal by a case statement, the codimg logic of IRIG-B (AC) code is then the digital form by design, direct current code conversion being become alternating current code, is convenient to follow-up hardware handles.
The software design approach of 14. Big Dippeves as claimed in claim 13 and the embedded time synchronism equipment of GPS dual-mode time service, is characterized in that: IRIG-B (DC) code codimg logic method for designing:
The symbol width of IRIG-B code is 10ms, so only need consider to represent when Logic Circuit Design is carried out in programmable logic device (PLD) inside, that 0,1 and the clock count value of position code three data and bimodulus time service provides between pulse per second (PPS) and the beginning flag of DC code is synchronous, the former three values are all carry out width setting by counter register, and the latter is then synchronous by starting register count method to realize after high level that pulse per second (PPS) detected;
Most important in coding module design is the use of state machine, complete coding forming process has been shifted by 54 states, three enabling signal c2 are divided in state machine, c5, c8, c2 is low level enabling signal, c5 is high level enabling signal, c8 is the enabling signal of position code, due to the Logic Circuit Design using the clock of 50MHz to carry out system, so each code element needs 500_000 clock period, when c2 starts the high level that hour counter need count 100_000 clock period, the low level of 400_000 clock period represents the low level " 0 " in direct current code, high level and position code method for expressing are analogized, in state machine, state 0 represents the startup c8 when pulse per second (PPS) high level arrives, when counter counts counts to closedown c8 steering state 1 when 19 ' d499_999 and width have reached 10ms, otherwise circular wait by three enabling signals all clear 0 in state 0, the binary-coded decimal that state 1 ~ 4 is used for producing a position current second exports, by judging that the low and high level of every starts c2 or c8, state 5 is index mark positions is that low level only need start c2, state 6 ~ 8 is used for producing the binary-coded decimal of ten output current second, and the method for generation is consistent with method for position second, state 10 ~ 18 is used for producing the output of current minute information, the output of information when state 20 ~ 26 is used for producing current, state 30 ~ 38,40 ~ 41 is used for producing the output of current number of days information, state 9,19,29,39 and state 52 are used for carrying out the generation of P1 ~ P9, state 53 is used for producing P0 for last state, finally will leave the 1ms time to forward the arrival that state 0 is used for waiting for pulse per second (PPS) high level to, thus makes pulse precision reach the highest, other state is all used to the output producing low level signal, after state machine setting, in order to ensure the integrality of the reception of front end data, carry out the renewal of temporal information when the rising edge of pulse per second (PPS) being detected, this can play the effect of refresh time p.s..
The software design approach of 15. Big Dippeves as claimed in claim 13 and the embedded time synchronism equipment of GPS dual-mode time service, is characterized in that: IRIG-B (AC) code codimg logic method for designing:
The digital signal of IRIG-B (AC) code obtains after being formed and being input to address generating module, sine value ROM storage list module and D/A conversion module by IRIG-B (DC) code.
The software design approach of 16. Big Dippeves as claimed in claim 10 and the embedded time synchronism equipment of GPS dual-mode time service, is characterized in that: IRIG-B (DC) code decode logic method for designing:
The design core of this module is the identification to code element, the 10kHz pulse produced by major clock frequency division is as the global clock of direct current code decoder module, DC code in transmitting procedure because the interference of passage can generating portion deformation, this just makes the width of each code element to change, so specify that when carrying out high level number and judging the clock number of " P " is 70 ~ 90, the clock number of logic " 0 " is 10 ~ 30, the clock number of logical one is 40 ~ 60, the width identifying code element can carry out judgement and the extraction of relevant information, mainly be divided into two parts: the extraction of pulse per second (PPS) and the extraction of temporal information:
The synchronous extraction of one .DC code pulse per second (PPS)
For the extraction of pulse per second (PPS), adopt at least one in following three kinds of methods:
1) accurate counting method
Adopt three states to carry out monitoring to the pulse per second (PPS) of DC code to extract, state S0 represents and when monitoring a 8ms pulsewidth after, jumps to state S1 otherwise continuous circulation searching; State S1 represents after again monitoring a 8ms pulsewidth, jumps to state S2, and no person jumps to state S0 and again monitors; State S2 represents that now inspected is to two 8ms pulsewidths, when the rising edge of a code element after PR being detected, jump to state S0 after giving an enabling signal and carry out continuation monitoring, this enabling signal then open time delay register time delay counting, giving a width as time delay 990ms is the high impulse of 1ms, and namely this high impulse is required pulse per second (PPS);
2) position mark detection method
Give the label that each identification code is different, label 0 from the label 10 of P9 to P0 successively decreases one by one, and three states in utilization state machine carry out the extraction of pulse per second (PPS), state S0 plays a monitoring pulsewidth and label is carried out to the effect of addition process, if next mode bit is PR, then now label should be 11, composes at once and is 0 and is checked through a 8ms pulsewidth, then need unlatching starting switch, be used for producing pulse per second (PPS); State S1 is then mainly used in the monitoring of state, jumps to state S2 when the pulsewidth detected is 8ms, otherwise turns back to state S0 continuation monitoring; The major function of state S2 is that the label giving current PR state puts 1;
3) waveform phase ' with ' method
The difference of the method and accurate counting method is only to need to count down to 989.5ms the time counted here, leaves 1.5ms as a pseudo-pulse per second (PPS) 1pps_1, finally DC code is carried out phase AND-operation with pseudo-pulse per second (PPS) thus obtain pulse per second (PPS);
Two. temporal information is extracted
Extraction for the time in code stream carries out global design by record, conversion and binary-coded decimal three modules here, the Main Function of logging modle is used to the clock number recording the label between every two location recognition mark P, the figure place corresponding to each code element and represent this code element high level width, and the function of modular converter is that the cell count width that utilizes front end to extract and figure place are carried out entirety and judged thus draw every corresponding binary code; The function of binary-coded decimal module is that the binary code that front end is extracted is transformed into corresponding binary-coded decimal.
The software design approach of 17. Big Dippeves as claimed in claim 16 and the embedded time synchronism equipment of GPS dual-mode time service, is characterized in that: IRIG-B (AC) code decode logic method for designing:
Deformation can be there is when AC signal is transmitted in the channel, the phenomenons such as decay, as the information in AC signal need extracted, just first must carry out waveform processing to it, after hardware handles is carried out to AC code, produced pulse signal and sinusoidal signal all need to be connected to the extraction carrying out amplitude in embedded microcontroller, this has just used external interrupt and the AD conversion function of STM32F103RBT6, due to the AC code amplitude of routine between 3 ~ 5V so first regulate slide rheostat to control between 1.8 ~ 3V by the amplitude of voltage according to designing requirement, again by judging whether the value collected is greater than this intermediate value of 1.4V and produces DC pulse, because the DC pulse that generated by embedded microcontroller is except than except the DC code time delay 250 μ s of standard, contained temporal information is the same, so the extracting method of just pulse per second (PPS) has difference on decode operation, pulse per second (PPS) is extracted and can only use described waveform phase "AND" method.
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| CN105589084A (en) * | 2015-12-23 | 2016-05-18 | 杭州电子科技大学 | STM32-based Beidou time service positioning device |
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| CN107566071B (en) * | 2016-01-28 | 2019-04-16 | 安徽四创电子股份有限公司 | A kind of decoding method of IRIG-B direct current code coding and decoding device |
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| CN106484357B (en) * | 2016-12-28 | 2019-03-15 | 中国科学院长春光学精密机械与物理研究所 | A kind of display system and display methods of B timing code temporal information |
| CN108628157A (en) * | 2018-05-11 | 2018-10-09 | 北京航天科工世纪卫星科技有限公司 | A kind of Big Dipper time service based on VPX boards under complex environment and Time keeping system |
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| CN111123692B (en) * | 2019-11-28 | 2021-06-08 | 北京时代民芯科技有限公司 | Embedded time unified system based on IRIG-B code |
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| CN117675951A (en) * | 2024-02-01 | 2024-03-08 | 中国船舶集团有限公司第七〇七研究所 | Standard serial time code generation method and system capable of being configured externally |
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