CN107230669B - 具有埋入式电路的封装基材 - Google Patents

具有埋入式电路的封装基材 Download PDF

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CN107230669B
CN107230669B CN201710075243.5A CN201710075243A CN107230669B CN 107230669 B CN107230669 B CN 107230669B CN 201710075243 A CN201710075243 A CN 201710075243A CN 107230669 B CN107230669 B CN 107230669B
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胡迪群
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Abstract

本发明公开了一种具有埋入式电路的封装基材，封装基材包括第一重新分布层，第一重新分布层还包括第一电路以及第一介电层；第一电路埋设在第一介电层中，第一电路具有顶面与第一介电层顶面共平面；第一电路具有底面与第一介电层底面共平面。本发明具有埋入式电路的封装基材厚度较薄、在厚度方向上提高半导体芯片封装的密度，适合半导体封装技术的较高密度封装要求。

Description

具有埋入式电路的封装基材
技术领域
本发明涉及一种封装基材，特别涉及一种具有埋入式电路的封装基材，该些埋入式电路具有一个顶表面，该顶表面与介电层的顶表面呈共平面。
背景技术
如图1所示，美国专利US 9,287,250B2公开了一种用于芯片的封装基材，核心基材30配置在中间，顶部阻焊层70F配置在封装基材的顶侧上，底部阻焊层70S配置在封装基材的底侧上。第一电路层158Fa埋设在介电层150Fb中。第二电路层58S埋设在介电层150Sa中。请注意埋入式电路158Fa的电路158Fa厚度和介电层150Fb的厚度的关系，介电层150Fb的厚度远大于电路158Fa的厚度。类似地，介电层150Sa的厚度远大于电路58S的厚度。
随着半导体工业中半导体芯片封装技术的快速发展，半导体芯片的封装密度的需求越来越高。如图1所示用于芯片的封装基材使用了较厚的介电层，例如核心基材30，大量占据了基材的空间高度。如果电路顶表面上方的介电层可以变薄或是消除，则在厚度方向上提高半导体芯片封装的密度，将是非常有帮助的。
发明内容
针对现有技术的上述不足，根据本发明的实施例，希望提供一种厚度较薄、在厚度方向上提高半导体芯片封装的密度，适合半导体封装技术的较高密度封装要求的封装基材。
根据实施例，本发明提供的一种具有埋入式电路的封装基材，包括第一重新分布层；所述第一重新分布层包括第一介电层和埋设在第一介电层中的第一电路，其特征是，所述第一电路具有顶表面，与第一介电层的顶表面共平面。
根据一个实施例，本发明前述具有埋入式电路的封装基材中，所述第一电路具有底表面，与所述第一介电层的底表面共平面。
根据一个实施例，本发明前述具有埋入式电路的封装基材中，还包括第二重新分布层，第二重新分布层配置在所述第一重新分布层的底侧；所述第二重新分布层包括第二介电层和埋设在第二介电层中的第二电路；所述第二电路电性耦合到所述第一电路。
根据一个实施例，本发明前述具有埋入式电路的封装基材中，还包括至少一芯片，配置于该第一电路的上侧。
根据一个实施例，本发明前述具有埋入式电路的封装基材中，还包括多个焊锡球，配置于该第二电路的底侧。
根据一个实施例，本发明前述具有埋入式电路的封装基材中，还包括第三重新分布层，所述第三重新分布层包括第三介电层和埋设在第三介电层中的第三电路；所述第三电路具有顶表面，与第三介电层的顶表面共平面；所述第三电路电性耦合到所述第二电路。
根据一个实施例，本发明前述具有埋入式电路的封装基材中，所述第三电路具有底表面，与第三介电层的底表面共平面。
根据一个实施例，本发明前述具有埋入式电路的封装基材中，还包括至少一芯片，设置于该第三电路的底侧。
根据一个实施例，本发明前述具有埋入式电路的封装基材中，所述第二重新分布层具有延伸超出所述第一重新分布层和所述第三重新分布层之一的横向侧的延伸部分；至少一个金属焊垫，暴露在所述延伸部分的顶侧或是底侧。
根据一个实施例，本发明前述具有埋入式电路的封装基材中，还包括封装胶体，封装所述第一重新分布层的周边；所述第二重新分布层设置于所述封装胶体与所述第一重新分布层的底面；所述封装胶体的底面接触于所述第二介电层的顶面。
相对于现有技术，本发明提供的具有埋入式电路的封装基材，具有埋设在介电层中的电路，并且该电路的厚度等于埋设该电路的介电层的厚度。本发明提供的具有埋入式电路的封装基材厚度较薄，适合于用于半导体封装技术的较高密度封装要求。
附图说明
图1是现有技术中用于芯片的封装基材的结构示意图。
图2A～2B是本发明的第一实施例的结构示意图。
图3A～6B显示本发明第一实施例的制造方法。
图7是本发明的第二实施例的结构示意图。
图8A～8B显示本发明第二个实施例的制造方法。
图9是本发明第三实施例的结构示意图。
图10A～12B显示本发明第三实施例的制造方法。
其中：11C、13C、21C、31C、61C、63C、71C为电路；111、112、115为芯片；12D、14D、62D为非感光介电层；12V、14V、21V、32V、61V、62V、71V为金属通路；11D、13D、31D、33D、61D、63D、71D为光敏介电层；13、15P、25P、71P、72P为开口；14V为纵向导通金属；15、25为介电层；211、212为金属焊垫；26为焊锡球；28为延伸部；282为金属焊垫；600为封装基材单元；68为封装胶体。
具体实施方式
下面结合附图和具体实施例，进一步阐述本发明。这些实施例应理解为仅用于说明本发明而不用于限制本发明的保护范围。在阅读了本发明记载的内容之后，本领域技术人员可以对本发明作各种改动或修改，这些等效变化和修改同样落入本发明权利要求所限定的范围。
图2A～2B显示本发明的第一实施例。
如图2A所示，本发明的第一实施例提供的具有埋入式电路的封装基材，其包括第一重新分布层RDL1。第一重新分布层RDL1包括埋设在第一介电层11D中的第一电路11C。多个第一纵向导通金属12V电性耦合相邻的上下层电路层。第一电路11C的厚度等于第一介电层11D的厚度。多个第一纵向导通金属12V埋设在第二介电层12D中；多个第一纵向导通金属12V被配置在第一电路11C的底侧上。
第一重新分布层RDL1还包括埋设在第二介电层13D中的第二电路13C。多个纵向导通金属14V电性耦合相邻的上下层电路层。第二电路13C的厚度等于介电层13D的厚度。多个纵向导通金属14V埋设在介电层14D中；多个纵向导通金属14V被配置在第二电路13C的底侧上。
第一电路11C具有顶表面和底表面；顶表面与第一介电层11D的顶表面共平面，并且底表面与第一介电层11D的底表面共平面。
第二重新分布层RDL2配置在第一重新分布层RDL1的底侧上；第二重新分布层RDL2包括埋设在介电层21D中的至少一层第二电路21C。多个纵向导通金属21V电性耦合相邻的上下层电路层；第二重新分布层RDL2的第二电路21C电性耦合到第一重新分布层RDL1的第一电路11C；并且第二电路21C从第一电路11C的底侧向下扇出，使得第二纵向导通金属21V的密度小于第一纵向导通金属12V、14V的密度。每个第二电路21C的线宽大于每个第一电路11C的线宽。
至少一个芯片配置在第一电路11C的顶侧上，多个焊锡球26配置在第二电路21C的底侧上。
图2B显示电路埋设状态的3D视图。图2B显示多个电路11C，每个电路11C具有顶表面与介电层11D的顶表面共平面；每个电路11C具有底表面与介电层11D的底表面共平面。多个纵向导通金属12V穿过介电层12D，导通上下相邻层的电路层。
图3A～6B显示本发明第一实施例的制造方法。
如图3A所示，制作第二重新分布层RDL2。所述第二重新分布层RDL2具有埋设在介电层21D中的至少一个电路21C。电路21C具有多个顶部金属焊垫211和多个底部金属焊垫212；多个纵向导通金属21V电性耦合相邻的上下层电路层。介电层25配置在第二重新分布层RDL2的底侧上。
如图3B所示，在第二重新分布层RDL2的顶侧上施加非光敏介电层14D；以及在非光敏介电层14D的顶侧上施加光敏介电层13D。
如图3C所示，图案化光敏介电层13D以形成多个开口13；底部的非光敏介电层14D用作蚀刻停止层(etch stopper)。
如图4A所示，对介电层14D进行激光钻孔(laser drilling)来形成多个第二开口14；第二开口14暴露对应的下层金属焊垫211。
如图4B所示，金属填充，形成电路13C和多个纵向导通金属14V。
如图5A所示，如果需要，可以利用相似的工艺，在电路13C的顶侧上再形成一层电路11C和多个纵向导通金属12V。
如图5B所示，在电路11C的顶侧上施加顶部介电层15。
如图6A所示，在顶部介电层15的顶侧上形成多个顶部开口15P，暴露对应的下层金属焊垫；以及在底部介电层25的底侧上形成多个底部开口25P，暴露对应的上层金属焊垫。
如图6B所示，在电路11C的顶侧上安装至少一个芯片111，并且在底部金属焊垫212的底侧上种植多个焊锡球26。
图7显示本发明的第二实施例。
如图7所示，制作第三重新分布层RDL3于第二重新分布层RDL2的底侧。第三重新分布层RDL3具有埋设在介电层31D中的一个第三电路31C。多个第三纵向导通金属32V电性耦合相邻的上下层电路层。第三电路31C的厚度等于第三介电层31D的厚度。第三重新分布层RDL3的第三电路31C电性耦合到第二重新分布层RDL2的第二电路21C；并且第三电路31C从底侧向上扇出，使得第二纵向导通金属21V的密度小于第三纵向导通金属32V的密度。
第三重新分布层RDL3的第三电路31C具有顶表面和底表面；顶表面与介电层31D的顶表面共平面；并且底表面与第三介电层31D的底表面共平面。至少一芯片112配置于第三重布线路层RDL3的电路31C的底侧。介电层31D是光敏介电层。每个电路31C的线宽小于每个电路21C的线宽。
图7显示第二重新分布层RDL2具有延伸超过第一重新分布层RDL1和第三重新分布层RDL3的横向延伸部分28；并且多个金属焊垫282在延伸部28的顶侧或是底侧上裸露。
图8A～8B显示本发明第二个实施例的制造方法。
如图8A所示，制作第二重新分布层RDL2；制作第一重新分布层RDL1于第二重新分布层RDL2的顶侧上，其可以根据第一实施例所述的制造方法来制备。此外，制作第三重新分布层RDL3设置于第二重新分布层RDL2的底侧上。
第三重新分布层RDL3具有埋设在介电层31D中的至少一个第三电路31C。多个纵向导通金属32V电性耦合相邻的上下层电路层。如果需要，可以构建在电路31C的底侧上，制作另一第三电路33C，第三电路33C埋设于介电层33D中。
如图8B所示，至少一个芯片111可以安装在第一重新分布层RDL1的电路11C的顶侧上，并且至少一个芯片112可以安装在第三重新分布层RDL3的第三电路33C的底侧上。
图9显示本发明第三实施例。
图9显示与图12B相同的产品，为了便于比较，我们将图9以上下颠倒的方式配置。
如图9所示，本发明第三实施例提供的具有埋入式电路的封装基材，其包括封装胶体68，封装在顶部重新分布层RDL6的周边。顶部重新分布层RDL6具有埋设在介电层61D中的至少一个电路61C。电路61C的厚度等于介电层61D的厚度。必要时，可以增加另一电路63C于电路61C下层；电路63C埋设在介电层63D中的。电路63C的厚度等于介电层63D的厚度。介电层61D、63D是光敏介电层。
底部重新分布层RDL7配置在顶部重新分布层RDL6的底侧上。底部重新分布层RDL7具有埋设在介电层71D中的至少一个电路71C。多个顶部金属焊垫711配置在重新分布层RDL7的顶侧上。多个底部金属焊垫712配置在重新分布层RDL7的底侧上。多个纵向导通金属71V，电性耦合相邻的上下层电路层。底部重新分布层RDL7的电路71C电性耦合到顶部重新分布层RDL6的电路61C。底部重新分布层RDL7的纵向导通金属71V的密度小于顶部重新分布层RDL6的纵向导通金属61V的密度。多个焊锡球66被配置在电路71C的底部上，每个焊锡球66被配置在相应的底部金属焊垫712的底侧上。至少一个芯片115被配置在顶部重新分布层RDL6的顶侧上。
图10A～12B显示本发明第三实施例的制造方法。
如图10A所示，制造具有埋入式电路的封装基材。封装基材包括多个封装基材单元600，封装基材600具有埋设在第一介电层61D中的至少第一电路61C。多个纵向导通金属62V电性耦合相邻的上下层电路层。必要时，可以增加埋第二电路63C，第二电路63C埋设在第三介电层63D中。第一电路61C的厚度等于第一介电层61D的厚度。第三电路63C的厚度等于第三介电层63D的厚度。介电层61D、63D是光敏介电层，介电层62D是非光敏介电层。底部介电层65配置在第一电路61C的底侧上。
如图10B所示，切割图10A可以获得多个封装基材单元600。
如图11A所示，将多个封装基材单元600重新设置在暂时附加电路板上；以及将封装胶体68设置于封装基材单元600的周边，形成底部重新分布层RDL6。
如图11B所示，在底部重新分布层RDL6的顶侧上制造第二重新分布层RDL7。第二重新分配层RDL7的电路71C的每个电路的线宽大于底部重新分配层RDL6的电路61C的每个电路的线宽。第二重新分布层RDL7的每个单元的宽度，大于上方第一重新分布层RDL6的单元宽度。第二重新分布层RDL7延伸以覆盖于封装胶体68的顶侧。移除暂时附加电路板，并在重新分布层RDL7的顶部上形成多个开口72P，并且在底部重新分布层RDL6的底部上形成多个开口71P。
如图12A所示，在重新分布层RDL7的电路71C的顶侧上种植多个焊锡球66，并且在重新分布层RDL6的电路61C的底侧上安装至少一个芯片115。
如图12B所示，切割图12A，可以获得多个封装单元。

Claims (8)

1.一种具有埋入式电路的封装基材，包括第一重新分布层；所述第一重新分布层包括第一介电层和埋设在所述第一介电层中的第一电路，其特征是，所述第一电路具有顶表面，与所述第一介电层的顶表面共平面，且所述第一电路具有底表面，与所述第一介电层的底表面共平面；以及
第二重新分布层，所述第二重新分布层配置在所述第一重新分布层的底侧；所述第二重新分布层包括第二介电层和埋设在所述第二介电层中的第二电路；所述第二电路电性耦合到所述第一电路，其中所述第二重新分布层相邻所述第一重新分布层且共用一介电层，所述第二电路的线宽大于所述第一电路的线宽。
2.根据权利要求1所述的具有埋入式电路的封装基材，其特征是，还包括至少一芯片，配置于所述第一电路的上侧。
3.如权利要求2所述的具有埋入式电路的封装基材，其特征是，还包括多个焊锡球，配置于所述第二电路的底侧。
4.根据权利要求1所述的具有埋入式电路的封装基材，其特征是，还包括第三重新分布层，所述第三重新分布层包括第三介电层和埋设在所述第三介电层中的第三电路；所述第三电路具有顶表面，与所述第三介电层的顶表面共平面；所述第三电路电性耦合到所述第二电路。
5.根据权利要求4所述的具有埋入式电路的封装基材，其特征是，所述第三电路具有底表面，与所述第三介电层的底表面共平面。
6.如权利要求5所述的具有埋入式电路的封装基材，其特征是，还包括至少一芯片，设置于所述第三电路的底侧。
7.根据权利要求5所述的具有埋入式电路的封装基材，其特征是，所述第二重新分布层具有延伸超出所述第一重新分布层和所述第三重新分布层之一的横向侧的延伸部分；至少一个金属焊垫，暴露在所述延伸部分的顶侧或是底侧。
8.如权利要求1所述的具有埋入式电路的封装基材，其特征是，还包括封装胶体，封装所述第一重新分布层的周边；所述第二重新分布层设置于所述封装胶体与所述第一重新分布层的底面；所述封装胶体的底面接触于所述第二介电层的顶面。
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