CN107017167A - The manufacture method of trench-gate device with shield grid - Google Patents
The manufacture method of trench-gate device with shield grid Download PDFInfo
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- CN107017167A CN107017167A CN201710116796.0A CN201710116796A CN107017167A CN 107017167 A CN107017167 A CN 107017167A CN 201710116796 A CN201710116796 A CN 201710116796A CN 107017167 A CN107017167 A CN 107017167A
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- 238000000034 method Methods 0.000 title claims abstract description 69
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 152
- 229920005591 polysilicon Polymers 0.000 claims abstract description 151
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 17
- 238000002955 isolation Methods 0.000 claims abstract description 17
- 239000000203 mixture Substances 0.000 claims abstract description 8
- 239000000126 substance Substances 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 258
- 239000000758 substrate Substances 0.000 claims description 29
- 239000004065 semiconductor Substances 0.000 claims description 26
- 239000002184 metal Substances 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 230000008569 process Effects 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 230000003647 oxidation Effects 0.000 claims description 10
- 238000007254 oxidation reaction Methods 0.000 claims description 10
- 238000010276 construction Methods 0.000 claims description 8
- 239000011229 interlayer Substances 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 claims description 6
- 230000000737 periodic effect Effects 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 5
- 238000000407 epitaxy Methods 0.000 claims description 4
- 239000007943 implant Substances 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 238000003701 mechanical milling Methods 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 abstract description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 230000008859 change Effects 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000012856 packing Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Element Separation (AREA)
Abstract
The invention discloses a kind of manufacture method of the trench-gate device with shield grid, including step：First epitaxial layer and chemical wet etching formation groove；Sequentially form the first oxide layer and first layer polysilicon；First layer polysilicon is carried out back to obtain polysilicon shield grid quarter；Carry out HDP CVD and deposit the second oxide layer by the top section filling of groove；Carry out oxide layer wet method return carve make in groove only polysilicon shield grid surface member-retaining portion thickness the second oxide layer；HDP CVD the 3rd oxide layers of deposit are carried out to carry out the top of groove to be filled up completely with without cavity；Carry out oxide layer wet method return carve formed by remain in polysilicon shield grid surface second and three oxide layer superposition inter polysilicon isolate oxide layer；Form gate dielectric layer；Form second layer polysilicon and composition polysilicon gate.The present invention improves the thickness evenness of inter polysilicon isolation oxide layer and prevents the generation in cavity, improves the isolation performance that inter polysilicon isolates oxide layer.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacture method, more particularly to a kind of trench gate with shield grid
The manufacture method of device.
Background technology
As shown in Figure 1A to Fig. 1 J, be the existing trench-gate device with shield grid each step of manufacture method in device
Structural representation；The manufacture method of the existing trench-gate device with shield grid comprises the following steps：
Step 1: as shown in Figure 1A there is provided the first epitaxial layer 101, forming hard on the surface of the first epitaxial layer 101 and covering
Mold layer 102, the hard mask layers 102 are made up of oxide layer.Using lithographic etch process first epitaxial layer 101 grid
Groove 103 is formed in the forming region of pole.
Generally, the first epitaxial layer 101 is is formed at semiconductor substrate surface, and Semiconductor substrate is generally silicon substrate, first
Epitaxial layer 101 is silicon epitaxy layer.The Semiconductor substrate has the first conduction type heavy doping, the back side of the Semiconductor substrate
For forming drain electrode, there is first epitaxial layer 101 first conduction type to be lightly doped, and first epitaxial layer 101 is used for shape
Into the drift region of trench-gate device.
Step 2: as shown in Figure 1B, in the lower surface of groove 103 and sidewall surfaces the first oxide layer 104 of formation, institute
State the first oxide layer 104 and also extend into the outer surface of groove 103.
As shown in Figure 1 C, first layer polysilicon 105, the first layer polycrystalline are formed on the surface of the first oxide layer 104
The groove 103 is filled up completely with by silicon 105.
Step 3: carrying out back carving to the first layer polysilicon 105, this time is carved described the outside the groove 103
One layer of polysilicon 105 is removed completely, and the first layer polysilicon 105 positioned at the top of groove 103 is removed, by retaining
The first layer polysilicon 105 composition polysilicon shield grid 105 in the bottom of groove 103, refer to shown in Fig. 1 D.
Step 4: as referring to figure 1E, carrying out wet method and returning the groove carved at the top of the polysilicon shield grid 105
First oxide layer 104 of 103 sides is removed.During wet etching, due to the surface of the polysilicon shield grid 105
There is no oxide layer, therefore inevitably produced in the both sides of the polysilicon shield grid 105 by the quilt of the first oxide layer 104
The sunk structure produced after etching.
Step 5: as shown in fig. 1F, deposited and aoxidized using high-density plasma chemical vapor deposition (HDP CVD) technique
Layer 106.Being filled up completely with the groove 103 of oxide layer 106 is required in this step, but with the width of groove 103
Less than reduction, the oxide layer 106 can be internally formed cavity 201 in the groove 103；Moreover, the oxide layer 106 is not yet
The sunk structure produced in the both sides of the polysilicon shield grid 105 can be filled up completely with, so as to produce the cavity shown in Fig. 1 F
202。
Step 6: as shown in Figure 1 G, carrying out CMP and all removing to expose the first extension by the oxide layer outside groove 103
Layer 101.Oxide layer outside groove 103 includes oxide layer 106 and hard mask layers 102 described in its bottom or first oxidation
The residual of layer 104.
As shown in fig. 1H, carry out wet method time quarter removing the oxide layer 106 positioned at the top of groove 103, by protecting
Stay the formation inter polysilicon isolation oxide layer 106 of the oxide layer 106 in the surface of polysilicon shield grid 105.By Fig. 1 H institutes
Show and understand, the thickness of inter polysilicon isolation oxide layer 106 is simultaneously uneven, and this is due to the presence in cavity 201 so that wet etching
Depression 203 is formed in inter polysilicon isolation oxide layer 106 afterwards, the thinner thickness at depression 203；Meanwhile, in inter polysilicon
The bottom of the both sides of isolating oxide layer 106 remains with cavity 202.
Step 8: as shown in Figure 1 I, the groove 103 at the top of polysilicon shield grid 105 forms grid oxygen sideways
Change layer 107.
Step 9: as shown in figure iJ, forming second layer polysilicon 108, the second layer polysilicon 108 will be formed with described
Gate oxide 107 and the groove 103 of inter polysilicon isolation oxide layer 106 are filled up completely with, by being filled in the groove
The second layer polysilicon 108 composition polysilicon gate 108 at 103 tops.
After the polysilicon gate 108 is formed, in addition to step：
The second conduction type well region is formed in first epitaxial layer 101, the polysilicon gate 108 passes through the trap
Area, the polysilicon gate 108 covers the well region and for forming raceway groove in well region side from side.
Carry out the first conduction type heavily-doped implant and form source region on the surface of the second conduction type well region.
Interlayer film is formed in Semiconductor substrate front.
Contact hole through the interlayer film is formed using lithographic etch process.
Form front metal layer and the front metal layer is patterned to form source electrode and grid, the source electrode passes through
The source region connection of corresponding contact hole and bottom, the grid passes through corresponding contact hole and the polysilicon gate of bottom
108 connections.Preferably, the polysilicon shield grid 105 are connected to the source electrode also by corresponding contact hole.
Thinning back side is carried out to the Semiconductor substrate；
The Semiconductor substrate back side after being thinned forms the drain region of the first conduction type heavy doping；In the drain region
The back side forms metal layer on back, and drain electrode is formed by the metal layer on back.
When the trench-gate device is N-type device, the first conduction type is N-type, and the second conduction type is p-type.When described
Trench-gate device is P-type device, and the first conduction type is p-type, and the second conduction type is N-type.
Generally, what is formed in the device unit construction that trench-gate device is alternately arranged including multiple cycles, step one is described
Groove is multiple including what is be alternately arranged, and each described groove and a device unit construction are corresponding.Correspondence cycle row
The structure of row, pitch size is the width of the groove 103 and the sum of spacing, when pitch is more than 1.5 microns, step
The phenomenon that cavity 201 and 202 is produced in rapid five is not obvious, and device can obtain excellent grid source isolation effect, i.e., described polysilicon
Between isolating oxide layer 106 isolation effect it is preferable so that be connected to the polysilicon shield grid 105 of source electrode and as grid knot
The isolation effect of the polysilicon gate 108 of structure is good.
But it is less than 1.5 microns of up-down structure shield grids particularly with pitch less than or equal to 1.0 microns for pitch
For groove MOSFET device, due to being limited by the depth-to-width ratio that HDP CVD oxide layers are filled, cavity can be produced in step 5
201 and 202, above-mentioned process easily causes the institute between control gate i.e. polysilicon gate 108 and the polysilicon shield grid 105
State the uneven or even short circuit of the thickness of inter polysilicon isolation oxide layer 106.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of manufacture method of the trench-gate device with shield grid, energy
Oxide layer is isolated using the thicker inter polysilicon of HDP CVD depositing technics formation and the thickness that inter polysilicon isolates oxide layer is improved
Uniformity and the generation for preventing cavity, so as to improve the isolation performance that inter polysilicon isolates oxide layer.
In order to solve the above technical problems, the manufacture method for the trench-gate device with shield grid that the present invention is provided is included such as
Lower step：
Step 1: provide the first epitaxial layer, using lithographic etch process first epitaxial layer grid forming region
Middle formation groove.
Step 2: in the trench bottom surfaces and sidewall surfaces the first oxide layer of formation, first oxide layer is also prolonged
Reach the groove outer surface；In the described first oxidation layer surface formation first layer polysilicon, the first layer polysilicon will
The groove is filled up completely with.
Step 3: carrying out back carving to the first layer polysilicon, this time is carved the first layer outside the groove is more
Crystal silicon is removed completely, and the first layer polysilicon at the top of the groove is removed, by remaining in the channel bottom
The first layer polysilicon composition polysilicon shield grid.
Step 4: depositing the second oxide layer using HDP CVD techniques, second oxide layer is by the top of the groove
Described the first of the groove side surface filled and be covered at the top of the polysilicon shield grid is divided to aoxidize layer surface and described
The surface of polysilicon shield grid, second oxide layer also extends into the groove outer surface.
Carved Step 5: carrying out wet method and returning by described second of the groove side surface at the top of the polysilicon shield grid
Oxide layer and first oxide layer remove and will be formed in completely second oxidation on the polysilicon shield grid surface
The segment thickness of layer is removed, and the polycrystalline is reduced by second oxide layer for remaining in the polysilicon shield grid surface
The depth-to-width ratio of the groove at the top of silicon shield grid.
Step 6: depositing the 3rd oxide layer using HDP CVD techniques, the 3rd oxide layer is complete by the top of the groove
Full packing simultaneously extends to the groove outer surface；Utilize second oxide layer for remaining in the polysilicon shield grid surface
The characteristic of the depth-to-width ratio of the groove at the top of the polysilicon shield grid is reduced, makes the 3rd oxide layer to the ditch
The top of groove carries out being filled up completely with without cavity.
Step 7: the oxide layer outside the groove is all removed and exposed described using chemical mechanical milling tech
First epi-layer surface；
Carry out wet method and return the 3rd oxide layer removal carved at the top of the groove, by remaining in the polysilicon
Second oxide layer and the 3rd oxide layer on shield grid surface are superimposed to form inter polysilicon isolation oxide layer.
Step 8: the groove side surface formation gate dielectric layer at the top of the polysilicon shield grid.
Step 9: forming second layer polysilicon, the second layer polysilicon will be formed with the gate dielectric layer and described many
The groove of isolating oxide layer is filled up completely between crystal silicon, is constituted by being filled in the second layer polysilicon at the top of the groove
Polysilicon gate.
Further improve is that step 9, which is formed after the second layer polysilicon, also to be included to the second layer polysilicon
The step of carve, this time all removes the second layer polysilicon outside the groove after carving, by remaining in the ditch
Second layer polysilicon composition polysilicon gate at the top of groove.
Further improve is that trench-gate device is included in the device unit construction being alternately arranged in multiple cycles, step one
The groove formed is multiple including what is be alternately arranged, and each described groove and a device unit construction are corresponding.
Further improve is that there is the first epitaxial layer described in step one first conduction type to be lightly doped, described first
Epitaxial layer is used for the drift region for forming trench-gate device, and first epitaxial layer is formed at the first conduction type heavy doping
The semiconductor substrate surface, the back side of the Semiconductor substrate is used to form drain electrode.
Further improve is that the Semiconductor substrate is silicon substrate, and first epitaxial layer is silicon epitaxy layer, described the
One oxide layer, second oxide layer and the 3rd oxide layer are all silicon oxide layer.
Further improve be, the width of the groove of periodic arrangement and spacing and less than 1.5 microns.
Further improve be, the width of the groove of periodic arrangement and spacing and less than 1 micron.
Further improve is, after the polysilicon gate is formed, in addition to step：
The second conduction type well region is formed in first epitaxial layer, the polysilicon gate passes through the well region, described
Polysilicon gate covers the well region and for forming raceway groove in well region side from side.
Carry out the first conduction type heavily-doped implant and form source region on the surface of the second conduction type well region.
Interlayer film is formed in Semiconductor substrate front.
Contact hole through the interlayer film is formed using lithographic etch process.
Form front metal layer and the front metal layer is patterned to form source electrode and grid, the source electrode passes through
The source region connection of corresponding contact hole and bottom, the grid passes through corresponding contact hole and the polysilicon gate of bottom
Connection.
Further improve be, trench-gate device is trench gate mosfet, in addition to step：
Thinning back side is carried out to the Semiconductor substrate.
The Semiconductor substrate back side after being thinned forms the drain region of the first conduction type heavy doping.
Metal layer on back is formed at the back side in the drain region, drain electrode is formed by the metal layer on back.
Further improve is that the polysilicon shield grid are connected to the source electrode also by corresponding contact hole.
Further improve is that the gate dielectric layer in step 8 is the gate oxide using thermal oxidation technology formation.
Further improve is to be additionally included in first epi-layer surface before the photoetching process in step one to be formed firmly
The hard mask layers are sequentially etched after matter mask layer, photoetching process and first epitaxial layer forms the groove.
Further improve is that the hard mask layers are made up of oxide layer.
Further improve is that the trench-gate device is N-type device, and the first conduction type is N-type, the second conduction type
For p-type；Or, the trench-gate device is P-type device, and the first conduction type is p-type, and the second conduction type is N-type.
The present invention does not carry out oxide layer directly by being formed at quarter after polysilicon shield grid to first layer polysilicon time
Return the first oxide layer carved and remove the groove side surface at the top of polysilicon shield grid, but use HDP CVD techniques deposit second
Oxide layer carries out endless full packing to top channel, due to being endless full packing, therefore the second oxide layer of filling will not be formed in itself
Any cavity.
Afterwards, return and carve in the wet method for carrying out oxide layer, the wet method is returned in carving technology, due on the surface of polysilicon shield grid
It is formed with the second oxide layer, therefore wet method is returned carving technology and can realized the of the groove side surface at the top of polysilicon shield grid
Dioxide layer and the first oxide layer remove and will be formed in completely the portion of second oxide layer on polysilicon shield grid surface
Thickness is divided to be removed, so, meeting is in the second oxide layer of polysilicon shield grid surface member-retaining portion thickness, the second oxygen retained
Change layer, which is equal to, reduces the remaining depth at the top of groove, therefore can reduce the depth-to-width ratio of the groove at the top of polysilicon shield grid.
Simultaneously as the second oxide layer is remained with the surface of polysilicon shield grid, therefore the oxide layer of polysilicon shield grid both sides will not
Produce sunk structure.
Because the second oxide layer by reservation reduces the depth-to-width ratio of remaining groove, therefore subsequent step six is carried out
HDP CVD techniques can realize being filled up completely with without cavity to groove when depositing three oxide layers；Simultaneously as the 3rd oxide layer
The oxide layer of polysilicon shield grid both sides will not produce sunk structure before filling, therefore will not also produce by these sunk structure institutes
The cavity brought.
Due to inside the 3rd oxide layer without cavity and polycrystalline shield grid both sides also without cavity, therefore to the 3rd oxide layer carry out
Wet method, which is returned, can obtain thickness uniformly after quarter and the inter polysilicon without empty structure isolates oxide layer.
From the foregoing, it will be observed that the present invention can isolate oxide layer using the thicker inter polysilicon of HDP CVD depositing technics formation and carry
High inter polysilicon isolates the thickness evenness of oxide layer and prevents the generation in cavity, so as to improve inter polysilicon isolation oxidation
The isolation performance of layer, can improve device gate source isolation effect.
Brief description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description：
Figure 1A-Fig. 1 J are the device architecture signals in each step of manufacture method of the existing trench-gate device with shield grid
Figure；
Fig. 2 is present invention method flow chart；
Fig. 3 A- Fig. 3 K are the device architecture schematic diagrames in each step of present invention method.
Embodiment
As shown in Fig. 2 being present invention method flow chart；It is tool of the embodiment of the present invention as shown in Fig. 3 A to Fig. 3 K
There is the device architecture schematic diagram in each step of manufacture method of the trench-gate device of shield grid；The embodiment of the present invention has shield grid
The manufacture method of trench-gate device comprise the following steps：
Step 1: forming hard mask layers on the surface of the first epitaxial layer 1 there is provided the first epitaxial layer 1 as shown in Figure 3A
2, grid forming region is defined using photoetching process, the hard mask layers 2 and first epitaxial layer 1 are sequentially etched afterwards
Form the groove 3.In present invention method, the hard mask layers 2 are made up of oxide layer.
Trench-gate device includes the groove 3 formed in the device unit construction being alternately arranged in multiple cycles, step one
Multiple including what is be alternately arranged, each described groove 3 is corresponding with a device unit construction.
There is first epitaxial layer 1 first conduction type to be lightly doped, and first epitaxial layer 1 is used to form trench gate device
The drift region of part, first epitaxial layer 1 is formed at the semiconductor substrate surface with the first conduction type heavy doping, institute
Stating the back side of Semiconductor substrate is used to form drain electrode.
Preferably, the Semiconductor substrate is silicon substrate, and first epitaxial layer 1 is silicon epitaxy layer；The first follow-up oxygen
It is all silicon oxide layer to change layer 4, the second oxide layer 6 and the 3rd oxide layer 7.
Preferably, the width of the groove 3 of periodic arrangement and spacing and less than 1.5 microns.More preferably it is selected as, the cycle
Arrangement the groove 3 width and spacing and less than 1 micron.
Step 2: as shown in Figure 3 B, in the lower surface of groove 3 and sidewall surfaces the first oxide layer 4 of formation, described the
One oxide layer 4 also extends into the outer surface of groove 3.
As shown in Figure 3 C, first layer polysilicon 5 is formed on the surface of the first oxide layer 4, the first layer polysilicon 5 will
The groove 3 is filled up completely with.
Step 3: as shown in Figure 3 D, carrying out back carving to the first layer polysilicon 5, this time is carved outside the groove 3
The first layer polysilicon 5 is removed completely, and the first layer polysilicon 5 positioned at the top of groove 3 is removed, by retaining
The first layer polysilicon 5 composition polysilicon shield grid 5 in the bottom of groove 3.
Step 4: as shown in FIGURE 3 E, the second oxide layer 6 is deposited using HDP CVD techniques, second oxide layer 6 is by institute
State groove 3 top section fill and be covered in the top of the polysilicon shield grid 5 the side of the groove 3 first oxygen
Change the surface of layer 4 and the surface of the polysilicon shield grid 5, second oxide layer 6 also extends into the external table of groove 3
Face.
Step 5: as illustrated in Figure 3 F, carrying out wet method and returning the groove 3 carved at the top of the polysilicon shield grid 5
Second oxide layer 6 and first oxide layer 4 of side remove and will be formed in completely the table of polysilicon shield grid 5
The segment thickness of second oxide layer 6 in face is removed, by second oxygen for remaining in the surface of polysilicon shield grid 5
Change layer 6 to reduce the depth-to-width ratio of the groove 3 at the top of the polysilicon shield grid 5.
Further, since being formed with second oxide layer 6 on the surface of polysilicon shield grid 5, the wet of oxide layer is carried out
Method is returned will not form depression when carving in the surface both sides of the polysilicon shield grid 5, can understand with reference to accompanying drawing 3F and Fig. 1 E.
Step 6: as shown in Figure 3 G, the 3rd oxide layer 7 is deposited using HDP CVD techniques, the 3rd oxide layer 7 is by institute
The top for stating groove 3 is filled up completely with and extends to the outer surface of groove 3；Using remaining in the table of polysilicon shield grid 5
Second oxide layer 6 in face reduces the characteristic of the depth-to-width ratio of the groove 3 at the top of the polysilicon shield grid 5, makes
The top of 7 pairs of the 3rd oxide layer groove 3 carries out being filled up completely with without cavity.It can be managed with reference to accompanying drawing 3G and Fig. 1 F
Solution.
Step 7: as shown in figure 3h, the oxide layer outside the groove 3 is all gone using chemical mechanical milling tech
Remove and expose the surface of the first epitaxial layer 1.
As shown in fig. 31, carry out wet method time quarter removing the 3rd oxide layer 7 positioned at the top of groove 3, by protecting
Stay and form polysilicon spacer in second oxide layer 6 on the surface of polysilicon shield grid 5 and the 3rd oxide layer 7 superposition
From oxide layer 7a.It can understand with reference to accompanying drawing 3I and Fig. 1 H.
Step 8: as shown in figure 3j, the groove 3 at the top of polysilicon shield grid 5 forms gate dielectric layer sideways
8.Preferably, the gate dielectric layer 8 is the gate oxide using thermal oxidation technology formation.
Step 9: as shown in Fig. 3 K, forming second layer polysilicon 9, the second layer polysilicon 9 will be formed with the grid and be situated between
Matter layer 8 and the inter polysilicon isolation oxide layer 7a groove 3 are filled up completely with；The second layer polysilicon 9 is returned
The step of quarter, this time all removes the second layer polysilicon 9 outside the groove 3 after carving, and is pushed up by remaining in the groove 3
The second layer polysilicon 9 composition polysilicon gate 9 in portion.
After the polysilicon gate 9 is formed, in addition to step：
The second conduction type well region is formed in first epitaxial layer 1, the polysilicon gate 9 passes through the well region, institute
State polysilicon gate 9 and cover the well region and for forming raceway groove in well region side from side.
Carry out the first conduction type heavily-doped implant and form source region on the surface of the second conduction type well region.
Interlayer film is formed in Semiconductor substrate front.
Contact hole through the interlayer film is formed using lithographic etch process.
Form front metal layer and the front metal layer is patterned to form source electrode and grid, the source electrode passes through
The source region connection of corresponding contact hole and bottom, the grid passes through corresponding contact hole and the polysilicon gate of bottom
9 connections.
Trench-gate device is the gate MOSFET of groove 3, in addition to step：
Thinning back side is carried out to the Semiconductor substrate.
The Semiconductor substrate back side after being thinned forms the drain region of the first conduction type heavy doping.
Metal layer on back is formed at the back side in the drain region, drain electrode is formed by the metal layer on back.
The polysilicon shield grid 5 are connected to the source electrode also by corresponding contact hole.
In present invention method, the trench-gate device is N-type device, and the first conduction type is N-type, and second is conductive
Type is p-type.In other embodiments method, also can be：The trench-gate device is P-type device, and the first conduction type is P
Type, the second conduction type is N-type.
The present invention is described in detail above by specific embodiment, but these not constitute the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, and these also should
It is considered as protection scope of the present invention.
Claims (14)
1. a kind of manufacture method of the trench-gate device with shield grid, it is characterised in that comprise the following steps：
Step 1: provide the first epitaxial layer, using lithographic etch process in the grid forming region of first epitaxial layer shape
Into groove；
Step 2: in the trench bottom surfaces and sidewall surfaces the first oxide layer of formation, first oxide layer is also extended into
The groove outer surface；In the described first oxidation layer surface formation first layer polysilicon, the first layer polysilicon will be described
Groove is filled up completely with；
Step 3: carrying out back carving to the first layer polysilicon, this time is carved the first layer polysilicon outside the groove
Remove completely, and the first layer polysilicon at the top of the groove is removed, by the institute for remaining in the channel bottom
State first layer polysilicon composition polysilicon shield grid；
Step 4: depositing the second oxide layer using HDP CVD techniques, second oxide layer fills out the top section of the groove
The first oxidation layer surface for the groove side surface filled and be covered at the top of the polysilicon shield grid and the polycrystalline
The surface of silicon shield grid, second oxide layer also extends into the groove outer surface；
Carved Step 5: carrying out wet method and returning by second oxidation of the groove side surface at the top of the polysilicon shield grid
Layer and first oxide layer remove and will be formed in completely second oxide layer on the polysilicon shield grid surface
Segment thickness is removed, and the polysilicon screen is reduced by second oxide layer for remaining in the polysilicon shield grid surface
Cover the depth-to-width ratio of the groove at the top of grid；
Step 6: depositing the 3rd oxide layer using HDP CVD techniques, the 3rd oxide layer fills out at the top of the groove completely
Fill and extend to the groove outer surface；Reduced using second oxide layer for remaining in the polysilicon shield grid surface
The characteristic of the depth-to-width ratio of the groove at the top of the polysilicon shield grid, makes the 3rd oxide layer to the groove
Top carries out being filled up completely with without cavity；
Step 7: the oxide layer outside the groove is all removed using chemical mechanical milling tech and exposes described first
Epi-layer surface；
Carry out wet method and return the 3rd oxide layer removal carved at the top of the groove, by remaining in the polysilicon shield
Second oxide layer and the 3rd oxide layer on grid surface are superimposed to form inter polysilicon isolation oxide layer；
Step 8: the groove side surface formation gate dielectric layer at the top of the polysilicon shield grid；
Step 9: forming second layer polysilicon, the second layer polysilicon will be formed with the gate dielectric layer and the polysilicon
Between the groove of isolating oxide layer be filled up completely with, constitute polycrystalline by being filled in the second layer polysilicon at the top of the groove
Si-gate.
2. there is the manufacture method of the trench-gate device of shield grid as claimed in claim 1, it is characterised in that：Step 9 is formed
By the groove after the step of also including to the second layer polysilicon carve after the second layer polysilicon, this time quarter
The outside second layer polysilicon is all removed, and polysilicon is constituted by remaining in the second layer polysilicon at the top of the groove
Grid.
3. there is the manufacture method of the trench-gate device of shield grid as claimed in claim 1 or 2, it is characterised in that：Trench gate
The groove that device includes being formed in the device unit construction being alternately arranged in multiple cycles, step one is more including what is be alternately arranged
Individual, each described groove and a device unit construction are corresponding.
4. there is the manufacture method of the trench-gate device of shield grid as claimed in claim 3, it is characterised in that：Institute in step one
State the first epitaxial layer to be lightly doped with the first conduction type, first epitaxial layer is used for the drift region for forming trench-gate device,
First epitaxial layer is formed at the semiconductor substrate surface with the first conduction type heavy doping, the Semiconductor substrate
The back side be used for form drain electrode.
5. there is the manufacture method of the trench-gate device of shield grid as claimed in claim 4, it is characterised in that：The semiconductor
Substrate is silicon substrate, and first epitaxial layer is silicon epitaxy layer, first oxide layer, second oxide layer and the described 3rd
Oxide layer is all silicon oxide layer.
6. there is the manufacture method of the trench-gate device of shield grid as claimed in claim 3, it is characterised in that：Periodic arrangement
The width of the groove and spacing and less than 1.5 microns.
7. there is the manufacture method of the trench-gate device of shield grid as claimed in claim 6, it is characterised in that：Periodic arrangement
The width of the groove and spacing and less than 1 micron.
8. there is the manufacture method of the trench-gate device of shield grid as claimed in claim 4, it is characterised in that：It is described being formed
After polysilicon gate, in addition to step：
The second conduction type well region is formed in first epitaxial layer, the polysilicon gate passes through the well region, the polycrystalline
Si-gate covers the well region and for forming raceway groove in well region side from side；
Carry out the first conduction type heavily-doped implant and form source region on the surface of the second conduction type well region；
Interlayer film is formed in Semiconductor substrate front；
Contact hole through the interlayer film is formed using lithographic etch process；
Form front metal layer and the front metal layer is patterned to form source electrode and grid, the source electrode passes through correspondence
Contact hole and bottom source region connection, the grid passes through corresponding contact hole and the polysilicon gate of bottom and connects
Connect.
9. there is the manufacture method of the trench-gate device of shield grid as claimed in claim 8, it is characterised in that trench-gate device
For trench gate mosfet, in addition to step：
Thinning back side is carried out to the Semiconductor substrate；
The Semiconductor substrate back side after being thinned forms the drain region of the first conduction type heavy doping；
Metal layer on back is formed at the back side in the drain region, drain electrode is formed by the metal layer on back.
10. there is the manufacture method of the trench-gate device of shield grid as claimed in claim 8, it is characterised in that：The polycrystalline
Silicon shield grid is connected to the source electrode also by corresponding contact hole.
11. there is the manufacture method of the trench-gate device of shield grid as claimed in claim 1, it is characterised in that：In step 8
The gate dielectric layer be using thermal oxidation technology formation gate oxide.
12. there is the manufacture method of the trench-gate device of shield grid as claimed in claim 1, it is characterised in that：In step one
Photoetching process before be additionally included in after first epi-layer surface formation hard mask layers, photoetching process be sequentially etched it is described
Hard mask layers and first epitaxial layer form the groove.
13. there is the manufacture method of the trench-gate device of shield grid as claimed in claim 12, it is characterised in that：The hard
Mask layer is made up of oxide layer.
14. the manufacture method of the trench-gate device with shield grid as described in any claim in claim 4 to 13, its
It is characterised by：The trench-gate device is N-type device, and the first conduction type is N-type, and the second conduction type is p-type；Or, institute
Trench-gate device is stated for P-type device, the first conduction type is p-type, the second conduction type is N-type.
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