CN105957811A - Method for manufacturing trench gate power devices with shielded gate - Google Patents
Method for manufacturing trench gate power devices with shielded gate Download PDFInfo
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- CN105957811A CN105957811A CN201610269824.8A CN201610269824A CN105957811A CN 105957811 A CN105957811 A CN 105957811A CN 201610269824 A CN201610269824 A CN 201610269824A CN 105957811 A CN105957811 A CN 105957811A
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- 238000000034 method Methods 0.000 title claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 87
- 229920005591 polysilicon Polymers 0.000 claims abstract description 84
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 71
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 71
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 45
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 45
- 239000010703 silicon Substances 0.000 claims abstract description 45
- 238000002955 isolation Methods 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 239000005380 borophosphosilicate glass Substances 0.000 claims abstract 4
- 239000010410 layer Substances 0.000 claims description 167
- 230000015572 biosynthetic process Effects 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 14
- 238000005516 engineering process Methods 0.000 claims description 11
- 230000003647 oxidation Effects 0.000 claims description 11
- 238000007254 oxidation reaction Methods 0.000 claims description 11
- 238000000407 epitaxy Methods 0.000 claims description 10
- 238000011049 filling Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- 238000001259 photo etching Methods 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 239000011229 interlayer Substances 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 239000007943 implant Substances 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 3
- 238000006396 nitration reaction Methods 0.000 claims description 3
- 125000006850 spacer group Chemical group 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims 1
- 230000001413 cellular effect Effects 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 238000010276 construction Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical group [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a method for manufacturing trench gate power devices with shielded gate. The method comprises the following steps: 1) providing a silicon substrate and forming a trench at the bottom of the silicon substrate; 2) forming a first silicon oxide layer and a shielded gate at the bottom of the trench; 3) forming a second silicon oxide layer; 4) depositing a BPSG film and carrying out backflow planarization so as to completely fill in the top of the trench with the BPSG film and the second silicon oxide layer; 5) performing silicon oxide etch-back to form a polysilicon isolation dielectric layer consisting of the BPSG film after etch-back treatment and the second silicon oxide layer; and 6) forming a gate dielectric layer and a polysilicon gate at the top of the trench. With the method of the invention, the size of one unit structure of a device can be reduced for a thin gate dielectric layer so as to reduce the device's conduction voltage drop for low-voltage applications.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacture method, particularly relate to the manufacture method that one has the trench-gate power devices of shield grid (Shield Gate Trench, SGT).
Background technology
The trench-gate power devices with shield grid needs to be formed shield grid in the bottom of trench gate, and shield grid and trench gate the most all use polysilicon to form, and needs to be isolated by inter polysilicon isolation dielectric layer between shield grid and trench gate.In existing method, inter polysilicon isolation dielectric layer has two kinds of forming methods, the first is by after shield grid is formed, use high-density plasma chemical vapor deposition (HDP CVD) technique silicon oxide deposition to fill the groove at shield grid top, carry out back silicon oxide afterwards carving formation inter polysilicon isolation dielectric layer；Second method is that this inter polysilicon isolation dielectric layer and the gate oxide being positioned at top channel side use thermal oxidation technology to concurrently form by using the method for thermal oxidation technology to form inter polysilicon isolation dielectric layer.
As it is shown in figure 1, be the structural representation of the trench-gate power devices with shield grid that existing first method is formed；As a example by N-type device, it is formed with N-type epitaxy layer 102 on the surface of N-type semiconductor substrate such as silicon substrate 101, the N-type epitaxy layer 102 of area of grid is formed with groove, the top of groove is formed with the shield grid 104 being made up of polysilicon, and between shield grid 104 and groove side surface, isolation has dielectric layer such as silicon oxide layer 103.After forming shield grid 104, it is formed by HDP CVD technique formation silicon oxide, silicon oxide is carried out densification and carries out cmp (CMP) and wet method is returned and formed inter polysilicon isolation dielectric layer 105a quarter；Form gate dielectric layer such as gate oxide 106 afterwards and fill polysilicon and return the top formation trench gate i.e. polysilicon gate 107 being engraved in groove.The most also include p-type trap 108, the source region 109 of N+ district composition, interlayer film 110, contact hole 111, well region contact area 112, the forming step of front metal layer 113, finally front metal layer 113 is patterned formation source electrode and grid.
The advantage of the first process existing is that the thickness of inter polysilicon isolation dielectric layer 105a can return the time at quarter by wet method and accurately controls, and process window is bigger.Shortcoming is that groove depth-to-width ratio is required by the filling of HDP CVD, and the stepping i.e. cellular size (cell pitch) causing device cell is bigger, limits its application on low pressure metal-oxide-semiconductor.The conducting district of general device is formed by the arrangement of multiple cellular constructions, and cellular construction includes an interval between groove and groove, the size of a unit i.e. pitch be the width of groove and the spacing of groove with.
As in figure 2 it is shown, be the structural representation of the trench-gate power devices with shield grid that existing second method is formed；The formation process being only inter polysilicon isolation dielectric layer in place of difference with existing first method is different, in existing second method: after shield grid 104 is formed, inter polysilicon isolation dielectric layer 105b and gate oxide 106 is concurrently formed by thermal oxidation technology, inter polysilicon isolation dielectric layer 105b is by the top polysilicon silicon of shield grid 104 is aoxidized formation, and gate oxide 106 is that the oxidation of the silicon to groove side surface is formed.The second process step is simple, forms isolation from oxygen SiClx by once oxidation on the polysilicon while growth grid oxygen.But the thermal oxidation silicon mass ratio of grown on polysilicon is poor, it is necessary to obtain sufficiently thick isolation from oxygen SiClx by increasing the thickness of gate oxidation silicon；This threshold voltage (VT) that can affect device and non-clamped inductive load switching process (unclamped inductive switching, UIS) ability.
Summary of the invention
The technical problem to be solved is to provide the manufacture method of a kind of trench-gate power devices with shield grid, can reduce the cellular construction size of device and can obtain thin gate dielectric layer, it is thus possible to reduce the conduction voltage drop of device, it is achieved low pressure applications.
For solving above-mentioned technical problem, the manufacture method of the trench-gate power devices with shield grid that the present invention provides, comprise the steps:
Step one, provide a silicon substrate, carry out chemical wet etching in described silicon substrate, form groove.
Step 2, the shield grid being made up of the first polysilicon layer in the formation of the bottom of described groove, between described shield grid and described groove side surface and lower surface, isolation has the first silicon oxide layer, and the surface of described first silicon oxide layer is less than or equal to the surface of described shield grid.
Step 3, employing thermal oxidation technology form the second silicon oxide layer, and described second silicon oxide layer is formed at the described surface of silicon outside described shield grid top surface and the described groove side surface at described first silicon oxide layer top and described groove.
Step 4, deposition bpsg film also carry out backflow planarization to described bpsg film, and described groove top is filled up completely with together with described second silicon oxide layer by the described bpsg film after planarization；Described groove is filled together with described second silicon oxide layer to improve the filling capacity of described groove and for reducing the size of described groove in conjunction with described bpsg film.
Step 5, described bpsg film and described second silicon oxide layer are carried out silicon oxide return and carve and described bpsg film and described second silicon oxide layer after being returned quarter by described silicon oxide form inter polysilicon isolation dielectric layer, isolate dielectric layer between described polycrystalline silicon and be positioned at described shield grid top and described inter polysilicon is isolated the thickness of dielectric layer and returned carving technology control by described silicon oxide.
Step 6, forming gate dielectric layer and polysilicon gate at the described groove top being formed with described inter polysilicon isolation dielectric layer, described gate dielectric layer is formed at the side at described groove top, and described groove top is filled up completely with by described polysilicon gate.
Further improving is to be formed with silicon epitaxy layer in described surface of silicon in step one, and described groove is formed in described silicon epitaxy layer.
Further improve and be, step one is formed described groove and includes the most step by step:
Hard mask layers is formed in described surface of silicon.
By the formation region of the photoetching offset plate figure definition groove that photoetching process is formed.
Etching technics is used the hard mask layers forming region of described groove to be removed.
Remove described photoetching offset plate figure, for mask, described groove formed the silicon in region with the described hard mask layers after etching and perform etching and form described groove.
Remove described hard mask layers.
Further improving is that described hard mask layers is made up of oxide layer or is added nitration case by oxide layer and forms.
Further improve is that step 2 includes the most step by step:
Form the first silicon oxide layer in the side of described groove and lower surface, described first silicon oxide layer also extends into outside described groove.
Depositing the first polysilicon layer to will be formed with the described groove of described first silicon oxide layer and be filled up completely with, described first polysilicon layer also extends into the described first silicon oxide layer surface outside described groove.
Carrying out polysilicon and return quarter, described first polysilicon layer after this polysilicon returns quarter is positioned at described channel bottom and forms described shield grid.
Carry out silicon oxide and return quarter, this silicon oxide after returning quarter described first silicon oxide layer described channel bottom and realize between described shield grid and described groove side surface and lower surface isolate.
Further improve is that step 6 includes the most step by step:
Forming described gate dielectric layer in the side at the described groove top being formed with described inter polysilicon isolation dielectric layer, described gate dielectric layer also extends into outside described groove.
Filling the second polysilicon layer at the described groove top being formed with described gate dielectric layer, described second polysilicon layer also extends into the described gate dielectric layer surface outside described groove.
Carrying out polysilicon and return quarter, described second polysilicon layer after this polysilicon returns quarter is filled described groove top and forms described polysilicon gate.
Further improving is that described gate dielectric layer is grid silicon oxide layer.
Further improving is, after step 6, also to comprise the steps:
Step 7, carrying out ion implanting and thermal annealing and advance technique to form well region in described silicon substrate, described polysilicon gate covers described well region from side and the described well region surface by the covering of described polysilicon gate side is used for forming raceway groove.
Step 8, carry out heavily doped source be infused in described well region surface formed source region.
Step 9, form interlayer film, contact hole and front metal layer in described silicon substrate front, described front metal layer is carried out chemical wet etching and forms source electrode and grid, described source electrode is contacted with described source region and described shield grid by contact hole, and described grid is contacted with described polysilicon gate by contact hole.
Step 10, the described silicon substrate back side carried out thinning and forms heavily doped drain region, forming metal layer on back as drain electrode at the back side in described drain region.
Further improving is that trench-gate power devices is groove power MOSFET element.
Further improve and be, after the opening of contact hole described in step 9 is formed, metal filled before, be additionally included in the bottom of the contact hole contacted with described source region and carry out heavily-doped implant and form the step of well region contact area.
The groove at shield grid top is filled by combination together with the second silicon oxide layer that the bpsg film that the present invention is refluxed is formed with thermal oxidation technology, the reflux characteristic utilizing bpsg film can increase the filling capacity to groove, thus reduce the size of groove, namely the present invention is relative to existing first method, the present invention is higher to the filling capacity of groove, it is possible to realize the filling of the groove to less width, and the reducing of groove width, the size of whole device unit construction can be reduced, pitch can be reduced, thus beneficially can reduce the conduction voltage drop of device, realize the device application in low pressure.
Additionally, the present invention inter polysilicon isolation dielectric layer be bpsg film and the second silicon oxide layer are carried out back quarter after obtain, not only thickness can be precisely controlled, and the formation process of inter polysilicon isolation dielectric layer and gate dielectric layer is separately, it is thus possible to eliminate negative effects different to the requirement of thickness between inter polysilicon isolation dielectric layer and gate dielectric layer, sufficiently thin gate dielectric layer can be obtained while the inter polysilicon that can obtain adequate thickness isolates dielectric layer, it is possible to obtain good VT and UIS ability, be further conducive to device in the application of low pressure.
Accompanying drawing explanation
The present invention is further detailed explanation with detailed description of the invention below in conjunction with the accompanying drawings:
Fig. 1 is the structural representation of the trench-gate power devices with shield grid that existing first method is formed；
Fig. 2 is the structural representation of the trench-gate power devices with shield grid that existing second method is formed；
Fig. 3 is embodiment of the present invention method flow diagram；
Fig. 4 A-Fig. 4 O is the device architecture schematic diagram in each step of embodiment of the present invention method.
Detailed description of the invention
As it is shown on figure 3, be embodiment of the present invention method flow diagram；As shown in Fig. 4 A to Fig. 4 O, it it is the device architecture schematic diagram in each step of embodiment of the present invention method.The manufacture method of the trench-gate power devices that the embodiment of the present invention has shield grid 4 comprises the steps:
Step one, as shown in Figure 4 A a, it is provided that silicon substrate 1, carries out chemical wet etching and forms groove 303 in described silicon substrate 1.
Preferably, being formed with silicon epitaxy layer 2 on described silicon substrate 1 surface, described groove 303 is formed in described silicon epitaxy layer 2.
Form described groove 303 to include the most step by step:
As shown in Figure 4 B, hard mask layers 301 is formed on described silicon substrate 1 surface.Described hard mask layers 301 is formed by oxide layer or is added nitration case by oxide layer and forms.
By the formation region of the photoetching offset plate figure definition groove 303 that photoetching process is formed.
Etching technics is used the hard mask layers 301 forming region of described groove 303 to be removed.
As shown in Figure 4 C, described photoresist 302 figure is removed.As shown in Figure 4 D, for mask, the silicon forming region of described groove 303 is performed etching the described groove 303 of formation with the described hard mask layers 301 after etching.
As shown in Figure 4 E, described hard mask layers 301 is removed.
Step 2, the shield grid 4 being made up of the first polysilicon layer 4 in the formation of the bottom of described groove 303, between described shield grid 4 and described groove 303 side and lower surface, isolation has the first silicon oxide layer 3, and the surface of described first silicon oxide layer 3 is less than or equal to the surface of described shield grid 4.
Preferably, step 2 includes the most step by step:
As illustrated in figure 4f, forming the first silicon oxide layer 3 in the side of described groove 303 and lower surface, it is outside that described first silicon oxide layer 3 also extends into described groove 303.
As shown in Figure 4 G, depositing the first polysilicon layer 4 and will be formed with the described groove 303 of described first silicon oxide layer 3 and be filled up completely with, described first polysilicon layer 4 also extends into described first silicon oxide layer 3 surface outside described groove 303.
As shown at figure 4h, carrying out polysilicon and return quarter, described first polysilicon layer 4 after this polysilicon returns quarter is positioned at bottom described groove 303 and forms described shield grid 4.
As shown at figure 4h, carry out silicon oxide and return quarter, this silicon oxide after returning quarter described first silicon oxide layer 3 bottom described groove 303 and realize between described shield grid 4 and described groove 303 side and lower surface isolate.
Step 3, as shown in fig. 41, thermal oxidation technology is used to form described silicon substrate 1 surface that the second silicon oxide layer 5a, described second silicon oxide layer 5a are formed at outside described shield grid 4 top surface and described groove 303 side at described first silicon oxide layer 3 top and described groove 303.
Step 4, as shown in fig. 4j, deposits bpsg film 5b；As shown in Figure 4 K, described bpsg film 5b carrying out backflow planarization, described groove 303 top is filled up completely with together with described second silicon oxide layer 5a by the described bpsg film 5b after planarization；Described groove 303 is filled together with described second silicon oxide layer 5a to improve the filling capacity of described groove 303 and for reducing the size of described groove 303 in conjunction with described bpsg film 5b.Namely the embodiment of the present invention can reduce the size of device cellular and i.e. reduce pitch such that it is able to be adapted to carry out the low pressure applications of device.
Step 5, as illustrated in fig. 4l, described bpsg film 5b and described second silicon oxide layer 5a carries out silicon oxide return and carve and described bpsg film 5b and described second silicon oxide layer 5a after being returned quarter by described silicon oxide form inter polysilicon isolation dielectric layer, isolate dielectric layer between described polycrystalline silicon and be positioned at described shield grid 4 top and described inter polysilicon is isolated the thickness of dielectric layer and returned carving technology control by described silicon oxide.
Step 6, forming gate dielectric layer 6 and polysilicon gate 7 at described groove 303 top being formed with described inter polysilicon isolation dielectric layer, described gate dielectric layer 6 is formed at the side at described groove 303 top, and described groove 303 top is filled up completely with by described polysilicon gate 7.
Preferably, step 6 includes the most step by step:
As shown in fig. 4m, forming described gate dielectric layer 6 in the side at described groove 303 top being formed with described inter polysilicon isolation dielectric layer, it is outside that described gate dielectric layer 6 also extends into described groove 303.Described gate dielectric layer 6 is grid silicon oxide layer.
As shown in Fig. 4 N, filling the second polysilicon layer 7 at described groove 303 top being formed with described gate dielectric layer 6, described second polysilicon layer 7 also extends into described gate dielectric layer 6 surface outside described groove 303；
As shown in Fig. 4 N, carrying out polysilicon and return quarter, described second polysilicon layer 7 after this polysilicon returns quarter is filled described groove 303 top and forms described polysilicon gate 7.
Step 7, as shown in Fig. 4 N, carry out ion implanting and thermal annealing and advance technique to form well region 8 in described silicon substrate 1, described polysilicon gate 7 covers described well region 8 from side and described well region 8 surface by the covering of described polysilicon gate 7 side is used for forming raceway groove.
Step 8, as shown in Fig. 4 N, carry out heavily doped source be infused in described well region 8 surface formed source region 9.
Step 9, as shown in Fig. 4 N, interlayer film 10, contact hole 11 and front metal layer 13 is formed in described silicon substrate 1 front, described front metal layer 13 is carried out chemical wet etching and forms source electrode and grid, described source electrode is contacted with described source region 9 and described shield grid 4 by contact hole 11, and described grid is contacted with described polysilicon gate 7 by contact hole 11.
After the opening of described contact hole 11 is formed, metal filled before, be additionally included in the bottom of the contact hole 11 contacted with described source region 9 and carry out heavily-doped implant and form the step of well region contact area 12.
The trench-gate power devices of the embodiment of the present invention is groove power MOSFET element, also includes:
Step 10, described silicon substrate 1 back side carried out thinning and forms heavily doped drain region, forming metal layer on back as drain electrode at the back side in described drain region.
When the trench-gate power devices of the embodiment of the present invention is N-type device, described silicon substrate 1, described silicon epitaxy layer 2, described source region 9 and described drain region are all n-type doping, and described well region 8 is p-well.When the trench-gate power devices of the embodiment of the present invention is P-type device, described silicon substrate 1, described silicon epitaxy layer 2, described source region 9 and described drain region are all p-type doping, and described well region 8 is N trap.
Embodiment of the present invention method can break through the silicon oxide of HDPCVD formation simultaneously and limit with hot oxygen the pitch restriction of device as the gate oxide thickness of spacer medium as spacer medium；It is thus possible to reduce the unit size of device, if making 1.2 μm pitch,Device below gate oxide thickness；So that the groove power MOS device that low-voltage and low-power dissipation separate gate power MOS pipe i.e. has shield grid is possibly realized.Separate gate power MOS pipe the most on the market mostly is the application of more than 30V, can make 20V separate gate power MOS pipe after using embodiment of the present invention method.
Above by specific embodiment, the present invention is described in detail, but these have not been construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art it may also be made that many deformation and improves, and these also should be regarded as protection scope of the present invention.
Claims (10)
1. the manufacture method of a trench-gate power devices with shield grid, it is characterised in that comprise the steps:
Step one, provide a silicon substrate, carry out chemical wet etching in described silicon substrate, form groove；
Step 2, the shield grid being made up of the first polysilicon layer in the formation of the bottom of described groove, described shield grid and institute
State between groove side surface and lower surface isolation and have the first silicon oxide layer, the surface of described first silicon oxide layer less than or etc.
Surface in described shield grid；
Step 3, employing thermal oxidation technology form the second silicon oxide layer, and described second silicon oxide layer is formed at described shielding
Described silicon substrate outside grid top surface and the described groove side surface at described first silicon oxide layer top and described groove
Surface；
Step 4, deposition bpsg film also carry out backflow planarization, the described BPSG after planarization to described bpsg film
Described groove top is filled up completely with together with described second silicon oxide layer by film；In conjunction with described bpsg film and described second
Silicon oxide layer fills described groove together to improve the filling capacity of described groove and for reducing the size of described groove；
Step 5, described bpsg film and described second silicon oxide layer are carried out silicon oxide return quarter and returned by described silicon oxide
Described bpsg film after quarter and described second silicon oxide layer composition inter polysilicon isolation dielectric layer, between described polycrystalline silicon
Spacer medium layer is positioned at the thickness of described shield grid top and described inter polysilicon isolation dielectric layer by described silicon oxide
Return carving technology to control；
Step 6, form gate dielectric layer and polycrystalline at the described groove top being formed with described inter polysilicon isolation dielectric layer
Si-gate, described gate dielectric layer is formed at the side at described groove top, and described polysilicon gate is by complete for described groove top
Fill.
There is the manufacture method of the trench-gate power devices of shield grid the most as claimed in claim 1, it is characterised in that:
Being formed with silicon epitaxy layer in described surface of silicon in step one, described groove is formed in described silicon epitaxy layer.
There is the manufacture method of the trench-gate power devices of shield grid the most as claimed in claim 1 or 2, its feature
It is: step one is formed described groove and includes the most step by step:
Hard mask layers is formed in described surface of silicon；
By the formation region of the photoetching offset plate figure definition groove that photoetching process is formed；
Etching technics is used the hard mask layers forming region of described groove to be removed；
Remove described photoetching offset plate figure, with the described hard mask layers after etching for the mask formation region to described groove
Silicon perform etching formation described groove；
Remove described hard mask layers.
There is the manufacture method of the trench-gate power devices of shield grid the most as claimed in claim 3, it is characterised in that:
Described hard mask layers is made up of oxide layer or is added nitration case by oxide layer and forms.
There is the manufacture method of the trench-gate power devices of shield grid the most as claimed in claim 1, it is characterised in that:
Step 2 includes the most step by step:
Form the first silicon oxide layer in the side of described groove and lower surface, described first silicon oxide layer also extends into institute
State outside groove；
Deposit the first polysilicon layer to will be formed with the described groove of described first silicon oxide layer and be filled up completely with, described more than first
Crystal silicon layer also extends into the described first silicon oxide layer surface outside described groove；
Carrying out polysilicon and return quarter, described first polysilicon layer after this polysilicon returns quarter is positioned at described channel bottom and forms
Described shield grid；
Carry out silicon oxide and return quarter, this silicon oxide after returning quarter described first silicon oxide layer be positioned at described channel bottom and realize institute
State and isolate between shield grid and described groove side surface and lower surface.
There is the manufacture method of the trench-gate power devices of shield grid the most as claimed in claim 1, it is characterised in that:
Step 6 includes the most step by step:
Described gate dielectric layer, institute is formed in the side at the described groove top being formed with described inter polysilicon isolation dielectric layer
State gate dielectric layer to also extend into outside described groove；
Filling the second polysilicon layer at the described groove top being formed with described gate dielectric layer, described second polysilicon layer is also
Extend to the described gate dielectric layer surface outside described groove；
Carrying out polysilicon and return quarter, described second polysilicon layer after this polysilicon returns quarter is filled described groove top and forms
Described polysilicon gate.
7. the manufacture method of the trench-gate power devices with shield grid as described in claim 1 or 6, its feature
It is: described gate dielectric layer is grid silicon oxide layer.
There is the manufacture method of the trench-gate power devices of shield grid the most as claimed in claim 1, it is characterised in that:
After step 6, also comprise the steps:
Step 7, carry out ion implanting and thermal annealing and advance technique to form well region, described polysilicon in described silicon substrate
Grid cover described well region from side and the described well region surface by the covering of described polysilicon gate side is used for forming raceway groove；
Step 8, carry out heavily doped source be infused in described well region surface formed source region；
Step 9, form interlayer film, contact hole and front metal layer in described silicon substrate front, to described front metal
Layer carries out chemical wet etching and forms source electrode and grid, and described source electrode is connect by contact hole and described source region and described shield grid
Touching, described grid is contacted with described polysilicon gate by contact hole；
Step 10, the described silicon substrate back side is carried out thinning and forms heavily doped drain region, in the back side shape in described drain region
Become metal layer on back as drain electrode.
There is the manufacture method of the trench-gate power devices of shield grid the most as claimed in claim 8, it is characterised in that:
Trench-gate power devices is groove power MOSFET element.
There is the manufacture method of the trench-gate power devices of shield grid the most as claimed in claim 8, it is characterised in that:
The opening of contact hole described in step 9 formed after, metal filled before, be additionally included in the contact contacted with described source region
The bottom in hole carries out heavily-doped implant and forms the step of well region contact area.
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| CN109830620A (en) * | 2019-02-18 | 2019-05-31 | 京东方科技集团股份有限公司 | Display base plate and preparation method thereof, display device |
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| CN113299557A (en) * | 2021-06-24 | 2021-08-24 | 绍兴中芯集成电路制造股份有限公司 | Shielded gate field effect transistor and method of forming the same |
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