CN113192826A - Shielded gate trench device and method of making same - Google Patents
Shielded gate trench device and method of making same Download PDFInfo
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- CN113192826A CN113192826A CN202110461247.3A CN202110461247A CN113192826A CN 113192826 A CN113192826 A CN 113192826A CN 202110461247 A CN202110461247 A CN 202110461247A CN 113192826 A CN113192826 A CN 113192826A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 238000002955 isolation Methods 0.000 claims abstract description 189
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000007772 electrode material Substances 0.000 claims abstract description 29
- 238000005530 etching Methods 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 24
- 238000000151 deposition Methods 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims description 33
- 230000008569 process Effects 0.000 claims description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 8
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
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- 238000001312 dry etching Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
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- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
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- 229910052732 germanium Inorganic materials 0.000 description 1
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- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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Abstract
The invention provides a manufacturing method of a shielded grid groove device, which comprises the following steps: providing a semiconductor substrate, wherein a device unit area and an electrode connecting area are formed on the semiconductor substrate, the electrode connecting area is connected with the device unit area, a first groove is formed in the device unit area, a shielding grid is formed in the first groove, a second groove is formed in the electrode connecting area, and an electrode material is formed in the groove; depositing a first isolation layer; partially etching the first isolation layer on the shielding grid, completely etching the first isolation layer on the side wall of the first direction of the first groove, and reserving the first isolation layer on the side wall of the electrode connection region of the second direction of the second groove; forming a second isolation layer on the first isolation layer; and completely etching the second isolation layer on the side wall of the first groove in the first direction, and reserving the second isolation layer on the side wall of the electrode connecting region in the second direction of the second groove.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a shielded gate trench device and a manufacturing method thereof.
Background
Since the invention of power MOS technology, the technology has made many important developments and great advances. In recent years, new device structures and new manufacturing processes for power MOS technology have continually emerged to achieve two of the most basic goals: maximum power handling capability, minimum power consumption. Trench mosfet (trench mos) technology is one of the most important technological drivers to achieve this goal. Originally, the Trench MOS technology was invented to increase the channel density of planar devices to improve the current handling capability of the devices, but the channel density and drift resistance are not ideal enough.
Therefore, the industry further provides a new Trench MOS structure, which can not only reduce the channel density, but also further reduce the resistance of the drift region. Among the new Trench MOS structures, the shielded Gate/discrete Gate (Shield Gate/Split Gate) Trench technology is most representative, and the shielded Gate Trench power device is also commonly referred to as an SGT device, and the first polysilicon layer, i.e., the shielded polysilicon (Shield), can be used as an "in-vivo field plate" to reduce the electric field in the drift region, so as to reduce the resistance of the drift region, so the Shield-Gate/Split Gate technology generally has lower on resistance and higher breakdown voltage.
In the SGT (Shielded Gate Trench) process, a layer of SiO is deposited between the shield electrode and the Gate2The Inter-Poly Oxide film is used as an IPO (Inter-Poly Oxide) film to play an isolation role, and the deposition of the Inter-Poly Oxide film is usually realized by adopting a Full HDPCVD (High density plasma chemical vapor deposition) and an etching-back process after the Source Poly (Source polysilicon) deposition, wherein the maximum aspect ratio of the filling of the High density plasma chemical vapor deposition is 3:1 at present. For LV SGT (Low Voltage Shielded Gate Trench device), Trench CD (channel size) is small, and the aspect ratio when depositing an inter-polysilicon oxide film is large, resulting in: 1) void appears in Trench when Full HDP is deposited, which causes uncontrollable thickness of an oxide film between polycrystalline silicon; 2) when Partial HDP (Partial high density plasma chemical vapor deposition) is deposited, the oxide (oxide layer) in the Source Poly link up (Source polysilicon electrode connection) region is too thin to play an isolation role.
Disclosure of Invention
The invention aims to provide a shielded gate trench device and a manufacturing method thereof, and aims to solve the technical problems that the thickness of an oxide film between polycrystalline silicon in a device unit area is controllable, and the oxide film between polycrystalline silicon in an electrode connecting area plays an isolating role.
To solve the above technical problem, the present invention provides a method for manufacturing a shielded gate trench device, comprising
Providing a semiconductor substrate, wherein a device unit area and an electrode connecting area are formed on the semiconductor substrate, the electrode connecting area is connected with the device unit area, a first groove is formed in the device unit area, a shielding grid is formed in the first groove, a second groove is formed in the electrode connecting area, and an electrode material is formed in the groove;
depositing a first isolation layer, wherein the first isolation layer fills part of the first trench and covers the side wall of the first trench and the surface of the shielding gate, the first isolation layer also extends to the outer surface of the first trench, and the first isolation layer covers the surface of the electrode material;
partially etching the first isolation layer on the shielding gate, completely etching the first isolation layer on the side wall of the first direction of the first groove, and reserving the first isolation layer on the side wall of the electrode connection region in the second direction of the second groove;
forming a second isolation layer on the first isolation layer, wherein the second isolation layer fills part of the first trench and covers the side wall of the first trench and the surface of the first isolation layer, the second isolation layer also extends to the surface of the first isolation layer outside the first trench, and the second isolation layer covers the surface of the first isolation layer of the electrode material;
partially etching the second isolation layer on the shielding gate, completely etching the second isolation layer on the side wall of the first direction of the first groove, and reserving the second isolation layer on the side wall of the electrode connection region in the second direction of the second groove; wherein the first direction and the second direction are perpendicular.
Optionally, before the first isolation layer is etched, a first mask layer is covered on the electrode material of the electrode connection region, and the first mask layer covers the top and the side wall of the electrode connection region, so that the first isolation layer on the top and the side wall of the electrode connection region is prevented from being etched.
Optionally, the first mask layer is a photoresist.
Optionally, before etching the second isolation layer, a second mask layer is covered on the electrode material of the electrode connection region, and the second mask layer covers the top and the side wall of the electrode connection region, so as to prevent the second isolation layer on the top and the side wall of the electrode connection region from being etched.
Optionally, the second mask layer is a photoresist.
Optionally, a wet etching process is used for etching the first isolation layer and the second isolation layer.
Optionally, the first isolation layer and the second isolation layer are deposited by high-density plasma chemical vapor deposition.
Optionally, after the second isolation layer is etched, a gate material is deposited, and the gate material covers the second isolation layer and the side wall of the first trench and fills the first trench to form a gate.
Optionally, the electrode material of the electrode connection region is connected to the shielding gate of the device unit region.
Based on the same inventive concept, the present invention also provides a shielded gate trench device, comprising:
the semiconductor substrate is provided with a device unit area and an electrode connecting area, the electrode connecting area is connected with the device unit area, a first groove is formed in the device unit area, a shielding grid is formed in the first groove, a second groove is formed in the electrode connecting area, and electrode materials are formed in the grooves;
the shielding grid is sequentially provided with a first isolation layer, a second isolation layer and a grid electrode, the first isolation layer and the second isolation layer are used for isolating the shielding grid and the grid electrode, and the first isolation layer and the second isolation layer are also used for isolating the grid electrode of the device unit area from the electrode connecting area.
In the shielded gate trench device and the method for manufacturing the same according to the present invention, a first isolation layer is deposited on a device cell region and an electrode connection region, the first isolation layer does not fill the first trench and the second trench, then the first isolation layer on the shielded gate is partially etched, the first isolation layer on the sidewall of the first direction of the first trench is completely etched, and the first isolation layer on the sidewall of the electrode connection region of the second direction of the second trench is retained, then a second isolation layer is deposited on the device cell region and the electrode connection region, the second isolation layer also does not fill the first trench and the second trench, the second isolation layer is partially etched, the second isolation layer on the sidewall of the first direction of the first trench is completely etched, and the second isolation layer on the sidewall of the electrode connection region of the second direction of the second trench is retained, through the mode, the thickness of the first isolation layer and the second isolation layer (the polycrystalline silicon oxide film and the IPO) of the device unit area is controllable, no cavity is generated, and meanwhile, the thickness of the first isolation layer and the second isolation layer (the polycrystalline silicon oxide film and the IPO) of the electrode connection area is thick enough to play a role in isolation.
Drawings
FIG. 1 is a schematic flow chart of a method of fabricating a shielded gate trench device in accordance with an embodiment of the present invention;
FIGS. 2 a-7 a are schematic cross-sectional views of a device cell region in a first direction, corresponding to steps of a method of fabricating a shielded gate trench device according to an embodiment of the present invention;
FIGS. 2 b-6 b are schematic cross-sectional views of electrode connection regions in a second direction corresponding to steps of a method of fabricating a shielded gate trench device according to an embodiment of the present invention;
in the figure, the position of the upper end of the main shaft,
10-a semiconductor substrate; 11-a first trench; 12-a second dielectric layer; 13 a-a shield grid; 13 b-electrode material; 14 a-a first isolation layer; 14 b-a second barrier layer; 15-a first dielectric layer; 16-a silicon nitride layer; 17-a gate; 18 a-a first mask layer; 18 b-second mask layer.
Detailed Description
A shielded gate trench device and a method for fabricating the same according to the present invention will be described in further detail with reference to the accompanying drawings and embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
FIG. 1 is a schematic flow chart of a method of fabricating a shielded gate trench device in accordance with an embodiment of the present invention; as shown in fig. 1, the present embodiment provides a method for manufacturing a shielded gate trench device, including:
step S10, providing a semiconductor substrate, where a device cell region and an electrode connection region are formed on the semiconductor substrate, and the electrode connection region is connected to the device cell region, where a first trench is formed in the device cell region, a shielding gate is formed in the first trench, a second trench is formed in the electrode connection region, and an electrode material is formed in the second trench.
Step S20, depositing a first isolation layer, where the first isolation layer fills and covers a portion of the first trench on the sidewall of the first trench and the surface of the shield gate, and the first isolation layer further extends to the outer surface of the first trench, and the first isolation layer covers the surface of the electrode material.
Step S30, partially etching the first isolation layer on the shield gate, completely etching the first isolation layer on the sidewall of the first direction of the first trench, and leaving the first isolation layer on the sidewall of the electrode connection region in the second direction of the second trench.
Step S40, forming a second isolation layer on the first isolation layer, where the second isolation layer fills and covers a portion of the first trench and the surface of the first isolation layer, and the second isolation layer further extends to the surface of the first isolation layer outside the first trench, and the second isolation layer covers the surface of the first isolation layer of the electrode material.
Step S50, partially etching the second isolation layer on the shield gate, completely etching the second isolation layer on the sidewall of the first direction of the first trench, and leaving the second isolation layer on the sidewall of the electrode connection region in the second direction of the second trench; wherein the first direction and the second direction are perpendicular.
FIGS. 2 a-7 a are schematic cross-sectional views of a device cell region in a first direction corresponding to steps of a method for fabricating a shielded gate trench device according to an embodiment of the present invention; FIGS. 2 b-6 b are schematic cross-sectional views of electrode connection regions in a second direction corresponding to steps of a method of fabricating a shielded gate trench device according to an embodiment of the present invention; the following describes in detail an embodiment of the present invention with reference to fig. 2a to 7a and fig. 2b to 6 b.
Referring to fig. 2a and 2b, step S10 is executed to provide a semiconductor substrate 10, where the semiconductor substrate 10 is formed with a device cell region and an electrode connection region, and the electrode connection region is connected to the device cell region, where the device cell region is formed with a first trench 11, a shielding gate 13a is formed in the first trench 11, the electrode connection region is formed with a second trench, and an electrode material 13b is formed in the second trench. And the electrode material of the electrode connecting area is connected with the shielding grid of the device unit area.
In this embodiment, the semiconductor substrate 10 may be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a Silicon On Insulator (SOI) substrate, a Germanium On Insulator (GOI) substrate, a glass substrate, or other III-V compound substrate, and the material and structure of the semiconductor substrate 10 are not limited in this embodiment.
In the present embodiment, a semiconductor substrate 10 is provided, a first dielectric layer 15 and a silicon nitride layer 16 are deposited on the semiconductor substrate 10, and the first dielectric layer 15 and the silicon nitride layer 16 may be formed by chemical vapor deposition; an oxide film (not shown in the figure) is further deposited on the silicon nitride layer 16, the first dielectric layer 15, the silicon nitride layer 16 and the oxide film form a hard mask layer, then, the patterned photoresist covers the hard mask layer to define the position of the first groove 11, a dry etching process is performed under the protection of the photoresist, the pattern of the photoresist is transferred onto the hard mask layer, then the consumed patterned photoresist is removed, the dry etching process is performed under the protection of the hard mask layer to form the first groove 11, and the first groove 11 penetrates through the hard mask layer and extends into the semiconductor substrate 10. The second dielectric layer 12 is deposited by using a tubular thermal oxidation method to repair damage to the semiconductor substrate 10 caused by dry etching, the second dielectric layer 12 can also play a role in isolating the shielding gate 13a from the semiconductor substrate 10, and since the second dielectric layer 12 at the bottom of the trench deposited by thermal oxidation is thinner than the second dielectric layer 12 at the side wall of the trench, an oxide layer (not shown in the figure) is deposited by using a CVD process after the second dielectric layer 12 is deposited, so as to thicken oxides on the surface and the bottom of the trench.
Referring to fig. 3a and 3b, step S20 is performed to deposit a first isolation layer 14a, where the first isolation layer 14a fills a portion of the first trench 11 and covers sidewalls of the first trench 11 and a surface of the shielding gate 13a, the first isolation layer 14a further extends to an outer surface of the first trench 11, and the first isolation layer 14a covers a surface of the electrode material 13 b.
In this embodiment, the first isolation layer 14a is, for example, an Inter-Poly Oxide (IPO), the first isolation layer 14a is deposited by a High Density Plasma Chemical Vapor Deposition (HDPCVD) process, and a deposition rate ratio of the HDPCVD process on the sidewall and the bottom of the first trench is 1:2 to 1: 4.
Referring to fig. 4a and 4b, in step S30, the first isolation layer 14a on the shield gate 13a is partially etched, the first isolation layer 14a on the sidewall of the first direction of the first trench 11 is completely etched, and the first isolation layer 14a on the sidewall of the electrode connection region in the second direction of the second trench is remained. The complete etching of the first isolation layer 14a on the sidewall of the first trench 11 in the first direction may also reduce the aspect ratio during the second deposition of the isolation layer.
With reference to fig. 4b, before etching the first isolation layer 14a, a first mask layer 18a is covered on the first isolation layer 14a on the electrode material 13b of the electrode connection region, and the first mask layer 18a covers the top and the sidewall of the electrode connection region, so as to prevent the first isolation layer 14a on the top and the sidewall of the electrode connection region from being etched.
In this embodiment, a wet etching process is used to etch the first isolation layer 14 a. The first mask layer 18a is, for example, a photoresist. The first masking layer 18a protects the first isolation layer 14a on the top and sidewalls of the electrode connection region from etching.
After the wet etching process for the first isolation layer 14a is completed, the first mask layer 18a is removed, and a method for removing the first mask layer 18a is, for example, an ashing process.
When the first isolation layer 14a is etched, the first isolation layer 14a on the sidewall of the first trench is completely etched because the isolation layer on the sidewall of the first trench needs an oxide layer with high quality, and therefore, after the first isolation layer 14a on the sidewall of the first trench is completely etched, a tubular thermal oxidation process is used to deposit an oxide layer, and the oxide layer covers the sidewall of the first trench and the first isolation layer 14 a.
Referring to fig. 5a and 5b, step S40 is performed to form a second isolation layer 14b on the first isolation layer 14a, where the second isolation layer 14b fills a portion of the first trench 11 and covers the sidewall of the first trench and the surface of the first isolation layer 14a, the second isolation layer 14b further extends to the surface of the first isolation layer 14a outside the first trench, and the second isolation layer 14b covers the surface of the first isolation layer 14a of the electrode material 13 b.
In this embodiment, the second isolation layer 14b is, for example, an Inter-Poly Oxide (IPO), the second isolation layer 14b is deposited by a High Density Plasma Chemical Vapor Deposition (HDPCVD) process, and a deposition rate ratio of the HDPCVD process on the sidewall and the bottom of the first trench is 1:2 to 1: 4.
Referring to fig. 6a and 6b, step S50 is performed to partially etch the second isolation layer 14b on the shield gate, fully etch the second isolation layer 14b on the sidewall of the first trench in the first direction, and leave the second isolation layer 14b on the top and sidewall of the electrode connection region in the second direction of the second trench.
With reference to fig. 6b, before etching the second isolation layer 14b, a second mask layer 18b is covered on the second isolation layer 14b on the electrode material 13b of the electrode connection region, and the second mask layer 18b covers the top and the sidewall of the electrode connection region, so as to prevent the second isolation layer 14b on the top and the sidewall of the electrode connection region from being etched.
In this embodiment, a wet etching process is used to etch the second isolation layer 14 b. The second mask layer 18b is, for example, a photoresist. The second masking layer 18b protects the second isolation layer 14b on top and sidewalls of the electrode connection region from etching.
After the wet etching process for the second isolation layer 14b is completed, the second mask layer 18b is removed, and a method for removing the second mask layer 18b is, for example, an ashing process.
When the second isolation layer 14b is etched, the second isolation layer 14b on the sidewall of the first trench 11 is completely etched, because the isolation layer on the sidewall of the first trench 11 needs an oxide layer with high quality, and therefore, after the second isolation layer 14b on the sidewall of the first trench 11 is completely etched, an oxide layer (not shown in the figure) is deposited by using a tubular thermal oxidation process, and the oxide layer covers the sidewall of the first trench 11 and the second isolation layer 14 b.
Referring to fig. 7a, after the second isolation layer 14b is etched, a gate material is deposited, the gate material covers the second isolation layer 14b and the sidewall of the first trench, and fills the first trench 11 to form a gate 17.
In this embodiment, the deposited gate material covers the second isolation layer 14b and the sidewalls of the first trench, fills the first trench 11, and extends onto the semiconductor substrate 10. The gate material above the silicon nitride layer 16 is removed by Chemical Mechanical Polishing (CMP) to form the gate 17.
Through the first deposition of the first isolation layer 14a and the second deposition of the second isolation layer 14b, the first trench 11 is not filled with the first isolation layer 14a and the second isolation layer 14b, so that no void occurs, and the thicknesses of the first isolation layer 14a and the second isolation layer 14b are controllable through two deposition processes and two wet etching processes. Meanwhile, in the two wet etching processes, the top and the side wall of the electrode material 13b of the electrode connection region are covered with the first mask layer 18a and the second mask layer 18b, so that the first isolation layer 14a and the second isolation layer 14b of the top and the side wall of the electrode material 13b of the electrode connection region can be protected from being etched, and the first isolation layer 14a and the second isolation layer 14b of the top and the side wall of the electrode material 13b of the electrode connection region are thick enough to play a role in isolation.
Based on the same inventive concept, the present invention also provides a shielded gate trench device, comprising:
a semiconductor substrate 10, wherein a device unit region and an electrode connection region are formed on the semiconductor substrate 10, the electrode connection region is connected with the device unit region, a first trench 11 is formed in the device unit region, a shielding gate 13a is formed in the first trench 11, a second trench is formed in the electrode connection region, and an electrode material 13b is formed in the trench;
the shielding gate 13a is sequentially provided with a first isolation layer 14a, a second isolation layer 14b and a gate 17, the first isolation layer 14a and the second isolation layer 14b are used for isolating the shielding gate 13a from the gate 17, and the first isolation layer 14a and the second isolation layer 14b are also used for isolating the gate of the device unit region from the electrode connection region.
In summary, in the shielded gate trench device and the method for manufacturing the same according to the present invention, a first isolation layer is deposited on a device cell region and an electrode connection region, the first isolation layer does not fill the first trench and the second trench, then the first isolation layer on the shielded gate is partially etched, the first isolation layer on the sidewall of the first trench in the first direction is completely etched, and the first isolation layer on the sidewall of the electrode connection region in the second direction of the second trench is retained, then a second isolation layer is deposited on the device cell region and the electrode connection region, the second isolation layer does not fill the first trench and the second trench, the second isolation layer is partially etched, the second isolation layer on the sidewall of the first direction of the first trench is completely etched, and the second isolation layer on the sidewall of the electrode connection region in the second direction of the second trench is retained, through the mode, the thickness of the first isolation layer and the second isolation layer (the polycrystalline silicon oxide film and the IPO) of the device unit area is controllable, no cavity is generated, and meanwhile, the thickness of the first isolation layer and the second isolation layer (the polycrystalline silicon oxide film and the IPO) of the electrode connection area is thick enough to play a role in isolation.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A method of fabricating a shielded gate trench device, comprising
Providing a semiconductor substrate, wherein a device unit area and an electrode connecting area are formed on the semiconductor substrate, the electrode connecting area is connected with the device unit area, a first groove is formed in the device unit area, a shielding grid is formed in the first groove, a second groove is formed in the electrode connecting area, and an electrode material is formed in the groove;
depositing a first isolation layer, wherein the first isolation layer fills part of the first trench and covers the side wall of the first trench and the surface of the shielding gate, the first isolation layer also extends to the outer surface of the first trench, and the first isolation layer covers the surface of the electrode material;
partially etching the first isolation layer on the shielding gate, completely etching the first isolation layer on the side wall of the first direction of the first groove, and reserving the first isolation layer on the side wall of the electrode connection region in the second direction of the second groove;
forming a second isolation layer on the first isolation layer, wherein the second isolation layer fills part of the first trench and covers the side wall of the first trench and the surface of the first isolation layer, the second isolation layer also extends to the surface of the first isolation layer outside the first trench, and the second isolation layer covers the surface of the first isolation layer of the electrode material;
partially etching a second isolation layer on the shielding grid, completely etching the second isolation layer on the side wall of the first direction of the first groove, and reserving the second isolation layer on the side wall of the electrode connection region in the second direction of the second groove; wherein the first direction and the second direction are perpendicular.
2. The method of claim 1, wherein a first mask layer is applied over the electrode material of the electrode connection region before the first isolation layer is etched, the first mask layer covering a top and sidewalls of the electrode connection region to prevent the first isolation layer from being etched.
3. The method of manufacturing a shielded gate trench device of claim 2 wherein the first masking layer is a photoresist.
4. The method of claim 1, wherein a second mask layer is applied over the electrode material of the electrode connection region before etching the second isolation layer, the second mask layer covering a top and sidewalls of the electrode connection region to prevent the second isolation layer from being etched.
5. The method of manufacturing a shielded gate trench device of claim 4 wherein the second masking layer is photoresist.
6. The method of manufacturing a shielded gate trench device as defined in claim 1 wherein the etching of the first and second spacers is by a wet etch process.
7. The method of manufacturing a shielded gate trench device of claim 1 wherein depositing the first isolation layer and the second isolation layer uses high density plasma chemical vapor deposition.
8. The method of claim 1, wherein etching the second spacer is followed by depositing a gate material that covers the second spacer and sidewalls of the first trench and fills the first trench to form a gate.
9. The method of manufacturing a shielded gate trench device of claim 8 wherein an electrode material of said electrode connection region is connected to a shield gate of said device cell region.
10. A shielded gate trench device, comprising:
the semiconductor substrate is provided with a device unit area and an electrode connecting area, the electrode connecting area is connected with the device unit area, a first groove is formed in the device unit area, a shielding grid is formed in the first groove, a second groove is formed in the electrode connecting area, and electrode materials are formed in the grooves;
the shielding grid is sequentially provided with a first isolation layer, a second isolation layer and a grid electrode, the first isolation layer and the second isolation layer are used for isolating the shielding grid and the grid electrode, and the first isolation layer and the second isolation layer are also used for isolating the grid electrode of the device unit area from the electrode connecting area.
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